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LAB 3 PROBLEM _ 2 TEST BENCH

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LAB 3 PROBLEM _ 2 TEST BENCH Powered By Docstoc
					module test1_v;

       // Inputs
       reg clock;
       reg clear;
       reg a0;
       reg a1;

       // Outputs
       wire g;

       // Instantiate the Unit Under Test (UUT)
       lab3part2 uut (
                .clock(clock),
                .clear(clear),
                .a0(a0),
                .a1(a1),
                .g(g)
       );



               initial begin
   clock=1;
   forever begin
   #100 clock = ~clock;
   end
        end


       initial begin
                 // Initialize Inputs
                 clear = 0;
                 a0 = 0;
                 a1 = 0;

                  // Wait 100 ns for global reset to finish
                  #200;

                  clear = 1;
                  a0 = 0;
                  a1 = 0;

                  // Wait 100 ns for global reset to finish
                  #200;


                  a0 = 0;
                  a1 = 0;

                  // Wait 100 ns for global reset to finish
                  #200;


                  a0 = 0;
                  a1 = 0;
// Wait 100 ns for global reset to finish
#200;

a0 = 0;
a1 = 1;

// Wait 100 ns for global reset to finish
#200;


a0 = 0;
a1 = 1;

// Wait 100 ns for global reset to finish
#200;


a0 = 0;
a1 = 1;

// Wait 100 ns for global reset to finish
#200;

a0 = 0;
a1 = 1;

// Wait 100 ns for global reset to finish
#200;

a0 = 1;
a1 = 0;

// Wait 100 ns for global reset to finish
#200;


a0 = 1;
a1 = 0;

// Wait 100 ns for global reset to finish
#200;


a0 = 1;
a1 = 0;

// Wait 100 ns for global reset to finish
#200;

a0 = 1;
a1 = 0;


a0 = 1;
a1 = 1;
            // Wait 100 ns for global reset to finish
            #200;


            a0 = 1;
            a1 = 1;

            // Wait 100 ns for global reset to finish
            #200;


            a0 = 1;
            a1 = 1;

            // Wait 100 ns for global reset to finish
            #200;

            a0 = 1;
            a1 = 1;


      end

endmodule

				
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