EE 3120 LAB4

Document Sample
EE 3120 LAB4 Powered By Docstoc
					                     EE 3120
LAB 4: SEQUENTIAL LOGIC DESIGN USING VERILOG
          Lab Report by: Armando Sierra
         Email: axs085500@utdallas.edu
       Partners: Juan Sierra, Michael Garcia
Introduction:
         The purpose of this experiment is to understand and use different options
available in Verilog HDL to decribe logic circuits (finite state machine), design and
implement counters, and to design and implement practical finite state machines.We
designed an oven controller with a circuit attached that turns the oven on, off, or leaves
it as it is depending on the temperature. The second design was a stack controller that
keeps count of the number of elements in the stack, which has 8 different states
including an overflow and an underflow.

Problem Description:
       The first problem required the design of an oven controller attached to a circuitry
with output (H) and (L), which are asserted when the temperature rises above h or falls
below l respectively. Also the oven is turned on when the temperature falls below l,
turned off when it rises above h, or remains in the same state if the temperature is
between h and l. To design this circuit, first we created the following truth table.

   H         L      ON/OFF
   0         1          1
   1         0          0
   0         0        Priv.
                      state
   1         1       Undef.


From the truth table, we can see see that there would be two states ON/OFF in a mealy
state diagram. The diagram is shown in the next section of this report.

        The second design problem was a stack controller with three functions
PUSH/POP/EXCHNG. The stack controller can have a maximum a of five elements and
the following errors can occur: underflow if pop is performed with zero elements, or an
exchange with less that two elements, or overflow in a push is performed with five
elements. Using the specifics of the problem, the following truth table can be created.

PUSH         PULL          EXCHANGE       ELEMENTS       UNF           OVF
0            0             0              000            0             0
0            0             1              000            1             0
1            0             0              001            0             0
0            0             1              001            1             0
1            0             0              010            0             0
0            0             1              010            0             0
1            0             0              011            0             0
0             0           1              011           0             0
1             0           0              100           0             0
0             0           1              100           0             0
1             0           0              101           0             0
0             0           1              101           0             0
1             0           0              101           0             1
0             1           0              100           0             0
0             1           0              011           0             0
0             1           0              010           0             0
0             1           0              001           0             0
0             1           0              000           0             0
0             1           0              000           1             0


From the truth table we have states 0,1,2,3,4,5,ovf, unf. The mealy state machine is
shown in the next section of this report.

System analysis/ Circuit Diagram:
Problem #1:




Problem #2:
Verilog Code:
Problem #1:

module oven(h, l, reset, clock, q
 );
 input h, l, reset, clock;
 output q;
 reg q;

  and(a, ~h, q);
  or(data, l, a);

  always@(negedge clock)
    q=data&reset;

endmodule

Problem #2:

module part2(push, pop, exchng, clk, rst, unf, ovf, q2, q1, q0
 );

   input push, pop, exchng, clk, rst;
   output unf, ovf, q2, q1, q0;
   wire d2_push, d1_push, d0_push;
   wire d2_pop, d1_pop, d0_pop;
   wire d2_exchng, d1_exchng, d0_exchng;
   wire unf_pop, unf_exchng;
   wire d2, d1, d0;
   wire [2:0] in;

   assign in={push, pop, exchng};
   assign d2_push=q2|push&q1&q0;
   assign d1_push=push&~q2&~q1&q0|~push&q1|q1&~q0;
   assign d0_push=~push&q0|push&q2|push&~q2&~q0;
   assign ovfa=push&q2&q0;
   assign d2_pop=~pop&q2|q2&q0;
   assign d1_pop=~pop&q1|q1&q0|pop&q2&~q0;
   assign d0_pop=~pop&q0|pop&q2&~q0|pop&q1&~q0;
   assign unf_pop=pop&~q2&~q1&~q0;
   assign d2_exchng=q2;
   assign d1_exchng=q1;
   assign d0_exchng=q0;
   assign unf_exchng=exchng&~q2&~q1;
   assign unfa=unf_pop|unf_exchng;

   mux mux1(in, d2_push, d2_pop, d2_exchng, q2, d2);
   mux mux2(in, d1_push, d1_pop, d1_exchng, q1, d1);
   mux mux3(in, d0_push, d0_pop, d0_exchng, q0, d0);
   Dff overflow(ovfa, clk, rst, ovf);
   Dff underflow(unfa, clk, rst, unf);

   Dff state2(d2, clk, rst, q2);
   Dff state1(d1, clk, rst, q1);
   Dff state0(d0, clk, rst, q0);

endmodule

module mux(in, a, b, c, q, out
 );
  input [2:0] in;
  input a, b, c, q;
  output out;
  wire out1, out2, out3;

   and(out1, ~in[2], ~in[1], ~in[0], q);
   and(out2, ~in[2], ~in[1], in[0], c);
   and(out3, ~in[2], in[1], ~in[0], b);
   and(out4, ~in[2], in[1], in[0], q);

   and(out5, in[2], ~in[1], ~in[0], a);
   and(out6, in[2], ~in[1], in[0], q);
   and(out7, in[2], in[1], ~in[0], q);
   and(out8, in[2], in[1], in[0], q);

   or(out, out1, out2, out3, out4, out5, out6, out7, out8);

endmodule

module Dff(data, clk, rst, q
 );
  input data, clk, rst;
  output q;
  reg q;

   always@(posedge clk)
   if(~rst) begin
     q=0;
  end else begin
     q=data;

  end

endmodule
Test Bench:
Problem #1:

module oven_tb;

  // Inputs
  reg h;
  reg l;
  reg reset;
  reg clock;

  // Outputs
  wire q;


  // Instantiate the Unit Under Test (UUT)

  oven uut (
     .h(h),
     .l(l),
     .reset(reset),
     .clock(clock),
     .q(q)
  );

  initial begin
  clock = 1;
  forever begin
     #25 clock=~clock;
  end
  end


  initial begin
     // Initialize Inputs
     reset=0; h=0; l=0; #100;
     reset=0; h=0; l=1; #100;
     reset=0; h=1; l=0; #100;
     reset=0; h=1; l=1; #100;

    reset=1; h=0; l=0; #100;
    reset=1; h=0; l=1; #100;
    reset=1; h=1; l=0; #100;
    reset=1; h=1; l=1; #100;
    reset=1; h=0; l=0; #100;

  end

endmodule
Problem #2:

module part2_tb;

  // Inputs

  reg push;
  reg pop;
  reg exchng;
  reg clk;
  reg rst;

  // Outputs
  wire unf;
  wire ovf;
  wire q2;
  wire q1;
  wire q0;


  // Instantiate the Unit Under Test (UUT)
  part2 uut (

    .push(push),
    .pop(pop),
    .exchng(exchng),
    .clk(clk),
    .rst(rst),
    .unf(unf),
    .ovf(ovf),
    .q2(q2),
    .q1(q1),
    .q0(q0)
  );
  initial begin
     clk<=0; rst<=0;
  end

  always begin
    #10 clk=~clk;
  end

  initial begin
     #20;
     rst=1;
     push=0;pop=0;exchng=0;#20;
     push=0;pop=1;exchng=0;#20;
     push=0;pop=0;exchng=0;#20;
     push=0;pop=0;exchng=1;#20;
     push=0;pop=0;exchng=0;#20;
     push=1;pop=0;exchng=0;#20;
    push=0;pop=0;exchng=0;#20;
    push=0;pop=0;exchng=1;#20;
    push=0;pop=0;exchng=0;#20;
    push=1;pop=0;exchng=0;#20;
    push=0;pop=0;exchng=0;#20;
    push=0;pop=0;exchng=1;#20;
    push=0;pop=0;exchng=0;#20;
    push=1;pop=0;exchng=0;#20;
    push=0;pop=0;exchng=0;#20;
    push=0;pop=0;exchng=1;#20;
    push=0;pop=0;exchng=0;#20;
    push=1;pop=0;exchng=0;#20;
    push=0;pop=0;exchng=0;#20;
    push=0;pop=0;exchng=1;#20;
    push=0;pop=0;exchng=0;#20;
    push=1;pop=0;exchng=0;#20;
    push=0;pop=0;exchng=0;#20;
    push=0;pop=0;exchng=1;#20;
    push=0;pop=0;exchng=0;#20;
    push=1;pop=0;exchng=0;#20;
    push=0;pop=0;exchng=0;#20;
    push=0;pop=0;exchng=1;#20;
    push=0;pop=0;exchng=0;#20;

    push=0;pop=1;exchng=0;#20;
    push=0;pop=0;exchng=0;#20;
    push=0;pop=1;exchng=0;#20;
    push=0;pop=0;exchng=0;#20;
    push=0;pop=1;exchng=0;#20;
    push=0;pop=0;exchng=0;#20;
    push=0;pop=1;exchng=0;#20;
    push=0;pop=0;exchng=0;#20;
    push=0;pop=1;exchng=0;#20;
    push=0;pop=0;exchng=0;#20;
    push=0;pop=1;exchng=0;#20;
    push=0;pop=0;exchng=0;#20;
    push=0;pop=0;exchng=1;#20;
    push=0;pop=0;exchng=0;#20;

    end

endmodule
User Constrain File:
Problem #1:

NET clock LOC=”P81”;
NET reset LOC=”P82”;
NET h LOC=”P83”;
NET l LOC=”P84”;
NET q LOC=”P44”;

Problem #2:

NET clk LOC=”P81”;
NET rst LOC=”P82”;
NET push LOC=”P83”;
NET pop LOC=”P84”;
NET exchng LOC=”P86”;
NET unf LOC=”P44”;
NET ovf LOC=”P45”;
NET q0 LOC=”P46”;
NET q1 LOC=”P47”;
NET q2 LOC=”P48”;


Waveforms/ Results:
Problem#1:
Problem#2:




Conclusions:
        This experiment covered sequential logic design using verilog, more specifically state
machines. We designed and implemented an oven controller, and a stack controller. The oven
controller only had two states: ON and OFF, and the state definition depended on the
temperature range of the oven. The stack controller had eight different states since it could hold
a maximum of five elements ( states 0→5) and underflow and overflow states. This experiment
was essential in gaining a deeper understanding of fine state machines, and their verilog
implementation.

				
DOCUMENT INFO
Shared By:
Categories:
Tags:
Stats:
views:5
posted:2/15/2012
language:English
pages:10