# DCLAB_3

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```					         LAB 3: Sequential Logic Elements: Flip Flops and Registers

Lab Report By: Michael Garcia

Partners: Juan Sierra Rubio, Armando Rubio

Email: mxg091000@utdallas.edu

EE 3120 Lab Report #2                                                 Page 1
Introduction:
The purpose of first experiment is to familiarize and introduce the students to different
type of Flip-flops, understand and design flip-flops with synchronous and asynchronous
inputs, use D flip-flops to design and implement a universal shift register and use
address decoders and parallel in, parallel out registers to implement a register file
suitable for a small microprocessor.

Problem Description:
Problem 1:

In the first part of the experiment, we were asked to use combinational logic elements to
design a D flip flop with active low synchronous clear input which will force the flip flop
state to 0 synchronous with the clock. In order to accomplish this task, my team decided
to implement a simple two case block that achieve this goal. This is possible dude to the
fact that D Flip flops are simple memory component and they tent to keep any given
value at longest clear is not given, such as shown in the truth table blow.

Diagram of a D Flip Flop:

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EE 3120 Lab Report #2                                                               Page 2
Problem 2:
The second part of the first experiment, we were asked design a frequency divider
Using the given D flip flop from the previous experiment and as few additional gates as
possible to design a frequency divider circuit which will divide the input clock frequency
by 1,2, 4, 8. Besides the clock and clear inputs, the divider receives a 2bit control input,
a1 a0 which specifies the divide by amount (a1a0 = 00: divide by 1, a1a0 = 01: divide by
2, a1a0 = 10: divide by 4, a1a0 = 11: divide by 8). In order to design the following circuit,
our group decided to use the D flip flops that were designed in the previous experiment
and use the A0 and A1 as an AND element, such as flow controller. in this design the
A0 is 0, then the gates are aligned and only the given vales are passed to the output
clock, this of course only directs the desired output out hence creating a frequency
divider. The design is made of two different modules the D flip flops and the chip which
is the controller for the divide by frequency divider.

----------------------------------------------------------------------------

EE 3120 Lab Report #2                                                                 Page 3
Problem 3:
On the third problem we were asked to desing a three by eight rewgister file that accepts three

---------------------------------------------------------------------------------------

Data In Bus

Data Out Bus
RW

R/W input

Data In
Data out
Register

Block

Data Bus   Data Bus
Selected Reg      Selected Reg

Decoder

---------------------------------------------------------------------------------------
Circuit Diagram:
Problem 1:

---------------------------------------------------------------------------------------

---------------------------------------------------------------------------------------

EE 3120 Lab Report #2                                                                      Page 4
Problem 2:

"1"
T                                  T                                             T
Q                                Q                                            Q

Clock                              Clock                                         Clock

R

R

R
Reset

Clock

A1

Output
A2

Problem 3:

Data In Bus

Data Out Bus
RW
R/W input

Data In
Data out

Register

Block

Data Bus      Data Bus
Selected Reg         Selected Reg

Decoder

EE 3120 Lab Report #2                                                                                                          Page 5
Verilog Code:
Problem 1:

---------------------------------------------------------------------------------------
module part1(data, clk, clr, q, q_n
);
input data, clr, clk;
output q, q_n;

and(d, data, clr);            // in order to synchronize clr, we ANDed it with data so it’d be operated with clk
nand(s, d, clk);
nand(r, ~d, clk);
nand(q, s, q_n);
nand(q_n, r, q);

endmodule

---------------------------------------------------------------------------------------

Problem 2:

---------------------------------------------------------------------------------------
module Diff (D, clock, clear, Q, Q2);

input D; input clock; input clear;

output Q; output Q2;

reg Q, Q2;

always @(posedge clock)

begin

if (clear==0)

begin

EE 3120 Lab Report #2                                                                                                        Page 6
assign Q=0;

assign Q2=1;

end

else

begin

if (D ==0) begin

assign Q=0;

assign Q2=1;

end

else

begin

assign Q=1;

assign Q2=0;

end

end

end

endmodule

module part2(clock, clear, a0, a1, g);
input clock, clear, a0, a1;
output g;
wire wq, wqn, q1, q1n, q2, q2n, w1, w2, w3, w4, w5, w6,w7, w8, w9, w10, w11;
assign w9 = wqn;
Diff DFF0(w9, clock, clear, wq, wqn);
xor (w10, w1, w2);
and (w3, w1, w2);
xor (w11, w4, w3);
Diff DFF1(w10, clock, clear, q1, q1n);
Diff DFF2(w11, clock, clear, q2, q2n);
assign w1 = wq;
assign w2 = q1;

EE 3120 Lab Report #2                                                             Page 7
assign w4 = q2;
and (w5, ~a0, ~a1, clock);
and (w6, a0, ~a1, wq);
and (w7, ~a0, a1, w2);
and (w8, a0, a1, q2);
or (g, w5, w6, w7, w8);
endmodule

-------------------------------------------------------------------------------------

Problem 3:

---------------------------------------------------------------------------------------
module register(address, datain, dataout, d00, d01, d02, d03, d04, d05, d06, d07, RW, clear,
clock);
input [2:0]datain;
output [2:0]dataout;
reg dataout;
output d00;
output d01;
output d02;
output d03;
output d04;
output d05;
output d06;
output d07;
input RW;
input clear;
input clock;

wire   [2:0]   out0;
wire   [2:0]   out1;
wire   [2:0]   out2;
wire   [2:0]   out3;
wire   [2:0]   out4;
wire   [2:0]   out5;
wire   [2:0]   out6;
wire   [2:0]   out7;
wire   [7:0]   regpick;

registerinternal    registerinternal1(datain,   RW,   clock,   regpick[0],   clear,   d00,   out0);
registerinternal    registerinternal2(datain,   RW,   clock,   regpick[1],   clear,   d01,   out1);
registerinternal    registerinternal3(datain,   RW,   clock,   regpick[2],   clear,   d02,   out2);
registerinternal    registerinternal4(datain,   RW,   clock,   regpick[3],   clear,   d03,   out3);
registerinternal    registerinternal5(datain,   RW,   clock,   regpick[4],   clear,   d04,   out4);

EE 3120 Lab Report #2                                                                                 Page 8
registerinternal registerinternal6(datain, RW, clock, regpick[5], clear, d05, out5);
registerinternal registerinternal7(datain, RW, clock, regpick[6], clear, d06, out6);
registerinternal registerinternal8(datain, RW, clock, regpick[7], clear, d07, out7);

always @ (posedge clock)

begin

3'b000:   dataout   =   out0;
3'b001:   dataout   =   out1;
3'b010:   dataout   =   out2;
3'b011:   dataout   =   out3;
3'b100:   dataout   =   out4;
3'b101:   dataout   =   out5;
3'b110:   dataout   =   out6;
3'b111:   dataout   =   out7;

endcase

end

endmodule

`timescale 1ns / 1ps

output [7:0] regpick;
reg [7:0] regpick;

begin

3'b000:   regpick   =   8'b00000001;
3'b001:   regpick   =   8'b00000010;
3'b010:   regpick   =   8'b00000100;
3'b011:   regpick   =   8'b00001000;
3'b100:   regpick   =   8'b00010000;
3'b101:   regpick   =   8'b00100000;
3'b110:   regpick   =   8'b01000000;
3'b111:   regpick   =   8'b10000000;

endcase

end

endmodule

`timescale 1ns / 1ps

module registerinternal(datainput, RW, clock, regpick, clear, dQ, dataout);
input [2:0]datainput;
input RW;
input clock;
input regpick;
input clear;
output [2:0]dQ;
output [2:0]dataout;
reg [2:0]dataout;

wire [2:0] t;

mydff mydff0(datainput[0], clock, clear, dQ[0], t[0]);

EE 3120 Lab Report #2                                                                  Page 9
mydff mydff1(datainput[1], clock, clear, dQ[1], t[1]);
mydff mydff2(datainput[2], clock, clear, dQ[2], t[2]);

always @ (posedge clock)

begin

if (clear == 1)

begin

dataout[0] = 0;
dataout[1] = 0;
dataout[2] = 0;

end

else

begin

if (regpick == 1)
begin

case(RW)

1: begin
dataout[0] = datainput[0];
dataout[1] = datainput[1];
dataout[2] = datainput[2];
end

endcase

case(RW)

0: begin
dataout[0] = dQ[0];
dataout[1] = dQ[1];
dataout[2] = dQ[2];
end

endcase
end

end

end

endmodule

Note: When we tried to implement this code on the board it did not work in class. This is our final and
edited version. We know that code is fine and works well please contact me if there is any problem.

EE 3120 Lab Report #2                                                                             Page 10
Test Bench:
Problem 1:

---------------------------------------------------------------------------------------

module part1_tb;

// Inputs
reg data;
reg clk;
reg clr;

// Outputs
wire q;
wire q_n;

// Instantiate the Unit Under Test (UUT)
part1 uut (
.data(data),
.clk(clk),
.clr(clr),
.q(q),
.q_n(q_n)
);

initial begin
clr=1; data=1; #10;
clk=1; #10; clk=0; #10;
data=0; #10;
clk=1; #10; clk=0; #10;
clr=0; data=1; #10;
clk=1; #10; clk=0; #10;
data=0; #10;
clk=1; #10; clk=0; #10;

clr=1; data=1; #10;
clk=1; #10; clk=0; #10;
clr=0; #10;
clk=1; #10; clk=0; #10;

end
endmodule

EE 3120 Lab Report #2                                                            Page 11
-------------------------------------------------------------------------------------
Problem 2:

---------------------------------------------------------------------------------------
module Tb_v;
reg clock; reg clear; reg a0; reg a1;
wire g;
part2 uut ( .clock(clock), .clear(clear),
.a0(a0), .a1(a1), .g(g));
initial begin
clock=1;

forever begin
#100 clock = ~clock;
end end
initial begin
clear=0;
a0 = 0;a1 = 0; #200;
clear = 1;
a0 = 0;a1 = 1; #200;
a0 = 1;a1 = 0; #200;
a0 = 1;a1 = 1; #200;
end
endmodule

---------------------------------------------------------------------------------------

Problem 3:
module registertb_v;

// Inputs
reg datain;
reg RW;
reg clear;
reg clock;

// Outputs
wire dataout;
wire d00;
wire d01;

EE 3120 Lab Report #2                                                            Page 12
wire d02;
wire d03;
wire d04;
wire d05;
wire d06;
wire d07;

// Instantiate the Unit Under Test (UUT)
register uut (
.datain(datain),
.dataout(dataout),
.d00(d00),
.d01(d01),
.d02(d02),
.d03(d03),
.d04(d04),
.d05(d05),
.d06(d06),
.d07(d07),
.RW(RW),
.clear(clear),
.clock(clock)
);

//initial begin
// Initialize Inputs
//#100 clear = 0;
// clear = 1;
// datain = 0;
// RW= 0;
// end
initial begin
clock=0;
forever begin
#5;
clock=~clock;
end
end

initial begin
datain = 011; address = 000; RW = 1;#15;
datain = 010; address = 001; RW = 1;#15;
datain = 101; address = 010; RW = 1;#15;
datain = 100; address = 011; RW = 1;#15;
datain = 010; address = 100; RW = 1;#15;
datain = 011; address = 101; RW = 1;#15;

datain = 011; address = 000; RW = 0;#15;
datain = 010; address = 001; RW = 0;#15;
datain = 010; address = 010; RW = 0;#15;
datain = 010; address = 011; RW = 0;#15;
datain = 010; address = 100; RW = 0;#15;
datain = 010; address = 101; RW = 0;#15;

datain = 011; address = 000; RW = 1;#15;
datain = 010; address = 001; RW = 1;#15;
datain = 101; address = 010; RW = 1;#15;
datain = 100; address = 011; RW = 1;#15;
datain = 010; address = 100; RW = 1;#15;
datain = 011; address = 101; RW = 1;#15;

datain = 011; address = 000; RW = 0;#15;
datain = 010; address = 001; RW = 0;#15;
datain = 010; address = 010; RW = 0;#15;
datain = 010; address = 011; RW = 0;#15;
datain = 010; address = 100; RW = 0;#15;

EE 3120 Lab Report #2                                            Page 13
datain = 010; address = 101; RW = 0;#15;
end

endmodule

---------------------------------------------------------------------------------------
---------------------------------------------------------------------------------------
User Constraints File:
NET   in_sto3LOC = "P89";
NET   in_sto2LOC = "P88";
NET   in_sto1LOC = "P87";
NET   in_reg3LOC = "P86";
NET   in_reg2LOC = "P83";
NET   in_reg1LOC = "P84";
NET   en LOC = "P58";
NET   out1 LOC = "P44";
NET   out2 LOC = "P45";
NET   out3 LOC = "P46";

Note: When we tried to implement this code on the board it did not work in class. This is our final and
edited version. We know that code is fine and works well please contact me if there is any problem.

Waveforms/Results:
Problem 1:

---------------------------------------------------------------------------------------

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EE 3120 Lab Report #2                                                                             Page 14
Problem 2:

---------------------------------------------------------------------------------------

-----------------------------------------------------------------------------------

Problem 3:

---------------------------------------------------------------------------------------

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EE 3120 Lab Report #2                                                            Page 15
Conclusion:
This experiment was a good practice at introducing student to different type of
Flip-flops, understanding and designing flip-flops with synchronous and asynchronous
inputs, using D flip-flops to design and implement a universal shift register and use
address decoders and parallel in, parallel out registers to implement a register file
suitable for a small microprocessor. Overall the lab was a bit harder than previous labs.
The first part of the lab was somewhat straight forward and did not percent any major
obstacle however the only obstacle that was faced was with the second and third part of
the experiment, it required constant review of the work and optimization. Furthermore
after revising the design and backtracking we were able to run and achieve the desire
results. Overall, it was a great lab to learn and practice theory that was thought in class.

EE 3120 Lab Report #2                                                                Page 16

```
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