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Hot Carrier Effect in Deep Submicron CMOS

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Hot Carrier Effect in Deep Submicron CMOS Powered By Docstoc
					Hot Carrier Effects in Deep
Submicron CMOS

             By
                  Abhijit Sil
               Out Lines
   CMOS Scaling, different types ,Limiting factors .
   Hot carrier Effect & reason behind that.
   Different type of hot carrier injection
   Different type charge generation inside gate oxide
   Degradation in N-MOS & PMOS performance
   Hot Carrier Induced Punch through
   Effect of oxide field in hot carrier injection
   Hot Carrier Effect in Low temperature
   How we can suppress this effect
   Different Suppression Techniques
CMOS Scaling
   Defines as reduction of the dimension of different parameters of
    MOSFET .


   Why Scaling ??
•   Increase device packing density.
•   Improve speed or frequency response (1/L)
•   Improve current drive (Transconductance Gm )
•   Decrease Power consumption
Types of Scaling
    Constant field scaling – Requires to reduce power supply
    voltage with the reduction of feature size .


    Constant voltage scaling –
•   Provides voltage compatibility with older circuit technologies .
•   Increasing electric field leads to velocity saturation , mobility
    degradation , sub threshold leakage
Parameter Trends
Limiting Factors of CMOS
scaling
   Punch Through

   Drain Induced Barrier Lowering (DIBL)

   Gate Induced Barrier Lowering (GIBL)

   Hot Carrier Effect
Hot Carrier Effect
   As feature size decreases , Electric field in channel
    region increases which leads to gain high kinetic
    energy by holes & electron (Hot carrier) .

   High kinetic energy helps them to inject inside
    gate oxide and form interface states , which in
    turns causes degradation of circuit performance .
    This effect is called Hot Carrier Effect     .
Cause of Hot Carrier Effect
   In submicron device , channel doping is increased to reduce the
    channel depletion region (DLBL effect ) .

   High doping increases threshold voltage .

   Gate oxide thickness reduces to control the threshold voltage .

   Due to channeling doping concentration , decreased channel
    length & reduced gate oxide thickness , hot carrier generated &
    injected to gate oxide.
Different type of Hot carrier
Injection
   Drain Avalanche Hot carrier (DAHC) Injection

   Channel Hot Electron (CHE) Injection

   Substrate Hot Electron (SHE) Injection

   Secondary generated hot electron (SGHE) injection
    Substrate Hot Electron (SHE)
    Injection

   Occurs when the substrate
    back bias is very positive or
    very negative

   Carriers of one type in the
    substrate are driven by the
    substrate field toward the Si-
    SiO2 interface.

   Gain high kinetic energy from
    and injected to SiO2.
Channel Hot Electron (CHE)
Injection

   When both VG & VD
    very higher than source
    voltage , some
    electrons driven
    towards gate oxide .
Drain Avalanche Hot carrier
(DAHC) Injection
   When VD>VG , the
    acceleration of channel
    carrier causes Impact
    Ionization .

   The generated electron
    –holes pair gain energy
    to break the barrier in
    Si-SiO2 interface
Charge Generation inside SiO2
   Negative charge generation

   Interface State Generation

   Positive charge Generation
Negative Charge Generation
   Hot electron trapping
    results negative charge
    buildup in the oxide
    near the drain

   Forming an extension of
    the p+ drain region
Interface State Generation
   At SiO2 interface , some Si-H , Si—Si and Si-O bonds
    only need less energy to break.
         X:H + e** ---> Xo + He + e*
         Xo + e ----> X: -
   Any electron with energy > 2eV capable to release H2 and
    create interface states .

   The degradation is caused by electron trapping by acceptor
    type Interface traps at the Si- SiO2 interface
Positive Charge Generation
   Injection of holes into the
    oxide generates positive
    charge .

   The source of holes is
    impact ionization by
    electrons in the high field
    region near drain .
P-MOSFET Degradation
   Channel length
    Degradation

   Transconductance
    Degradation

   Threshold Shift
Continue..
   Interface state generation is
    most prominent threat for
    deep submicron P-MOSFET

   The max allowable voltages
    for 10% change in 10 yrs
    are 4.7v for +ve , 4.2 for –
    Ve & 3.3 v for interface state
    generation
N-MOS Degradation
   Trapped electrons in
    the oxides result in
    the increase of Vth
    & Leff.
Hot Carrier Induced Punch
through

Effect of Oxide Field
   As the oxide field increases ,
    initially VG shifts increases
    (electron charge trapping ).

   When field becomes 6MV/cm
    , VG shifts towards negative
    .(positive charge
    trapping)(considering n-mos)
Continue..
Hot Carrier Effect in Low
Temperature
   Low Temperature technology
    is required in Space
    Technology .

   Hot carrier effects
    significantly worst in low
    temp .

   Primary reason for the huge
    reduction of device
    performance is that a given
    amount of damage (induced
    at high or low temp )
    induces greater reduction on
    device performance in low
    temp .
N-MOS Hot Carrier Effect in Low
Temperature
Reason Behind Degradation

   Damaged increased due to Columbic scattering at low
    temp . Increase scattering leads to mobility degradation   .

   At low temp , inversion fermi level lies closer to
    conduction band .Hot carrier induced interface which
    located near the the conduction level will have great
    impact on device performance.
P-MOS Hot Carrier Effect in Low
Temperature
Suppression of Hot Carrier Effect
(Device structure aspect )

   Reductionof Hot-Carrier Generation
   Reduce the high drain field
   Separate main current path away from maximum
    field .
   Reduction of Hot-Carrier Injection
   Push impact ionization region deep into silicon.
   Position the injection inside the gate edge .
Suppression of Hot Carrier Effect
(Processing aspect )

   Reduction Hot Carrier Trapping
   Use High quality gate oxide

   Maintain good oxide during processing by reducing
    radiation damage

   Reduce bond breakage rate during hot carrier
    injection
Hot Carrier Reduction Technique
   Gate Oxide thickness reduction

   Lightly Doped MOSFET structure

   Double Diffused MOSFET structure

   Incorporating Si3N4 as the gate oxide

   Deuterium Post –Metal Annealing
Gate Oxide thickness reduction
Continue..
   As the oxide thickness
    is reduced , the point of
    peak of electron
    injection moves further
    into the drain region ,
    the damage region over
    the channel is reduced .
Lightly Doped MOSFET structure

   As the drain edge has
    less carrier
    concentration , reduces
    the drain induced
    depletion width &
    lateral electric field .
Different type of LDD structure

   P+poly gate buried channel N-LDD device -Broader
    conduction channel resulting deeper position of maximum
    avalanche generation .

   Buried LDD (B-LDD) – Retrograde LDD profile with
    peak concentration below the Si- surface which suppress
    hot carrier injection by driving current away from the
    surface .

   Inverse T-gate LDD – Improve current capability & hot
    carrier resistance .
Double Diffused MOSFET
structure
   Deeper n- phosphorous
    profile than N+As
    profile .

   The path of maximum
    current away from the
    position of the
    maximum field to
    reduce the impact
    ionization .
Continue..
Incorporating Si3N4 as the gate
oxide
   High die electric gate
    insulator can significantly
    reduce gate leakage
    because of the fact higher
    k has higher physical
    thickness for the same
    electrical oxide thickness .

   Compatible with silicon
    technology

   The Si-N bonds are harder
    to break than Si-H bonds
Deuterium Post –Metal
Annealing
   Low temperature post
    metalization anneals in
    hydrogen ambient are
    critical in reducing Si-
    Sio2 interface trap .

   Under Hot Carrier stress ,
    bond to deuterium are
    more difficult to break
    than bonds to protium
Conclusion
   Three types of hot carrier Injection (DAHC)
    Injection, (CHE) Injection, (SHE) Injection, (SGHE)
    injection

   Three types of charge generation inside gate
    oxide . Negative charge generation Interface State
    Generation Positive charge Generation

   Interface state generation is most prominent
    threat for P-MOSFET & Hot electron is for N-
    MOSFET
Continue ..
   In low temperature , same amount of
    damage (induced at high or low temp )
    induces greater reduction on device
    performance.

   Different reduction techniques
    proposed- Gate Oxide thickness reduction ,Lightly
    Doped MOSFET structure ,Double Diffused MOSFET
    structure , Si3N4 as the gate oxide ,Deuterium Post –
    Metal Annealing
References
    Hot-Electron and Hole-Emission Effects in Short n-Channel MOSFET‘s - KARL R.
     HOFMANN, MEMBER, IEEE, CHRISTOPH WERNER, WERNER WEBER, AND GERHARD DORDA , IEEE
     TRANSACTIONS ON ELECTRON DEVICES, VOL. ED-32, NO. 3 , MARCH 1985
    Effect of oxide field on hot carrier induced degradation in CMOS gate oxide-
    S.P. Zhao and S.Tayfor , 1995 IEEE 91 5th IPFA '95: Singapore
   Performance and Hot-Carrier Reliability of 100 nm Channel Length Jet Vapor
    Deposited Si3N4 MNSFETs –S. Mahapatra, Student Member, IEEE, V. Ramgopal
    Rao, Member, IEEE, B. Cheng, M. Khare, Chetan D. Parikh, J. C. S. Woo, and Juzer M.
    Vasi, Senior Member, IEEE , IEEE TRANSACTIONS ON ELECTRON DEVICES,
    VOL. 48, NO. 4, APRIL 2001
   Suppression of Hot-Carrier Effects in Submicrometer CMOS Technology
    MIN-LIANG CHEN, MEMBER, IEEE, CHUNG-WAI LEUNG, MEMBER, IEEE,
    W. T. COCHRAN, MEMBER, IEEE, WERNER JUNGLING, MEMBER, IEEE,
    CHARLES DZIUBA, AND TUNGSHENG YANG, IEEE TRANSACTIONS ON
    ELECTRON DEVICES, VOL. 35, NO. 12. DECEMBER 1988
References
   Comparison of NMOS and PMOS Hot Carrier Effects From 300 to 77 K -Miryeong
    Song, Kenneth P. MacWilliams, Member, IEEE, and Jason C. S. Woo, IEEE
    TRANSACTIONS ON ELECTRON DEVICES, VOL. 44, NO. 2, FEBRUARY,1997
   Deuterium Post-Metal Annealing of MOSFET’s for Improved Hot Carrier
    Reliability -I. C. Kizilyalli, J. W. Lyding, and K. Hess , IEEE ELECTRON DEVICE
    LETTERS, VOL. 18, NO. 3, MARCH 1997
   An As-P(n’-n-) Doublk Diffused Drain MOSFET for VLSI’S -EIJI TAKEDA,
    MEMBER, IEEE, HITOSHI KUME, YOSIII[NOBU NAKAGOME, TOHACHI MAKINO,
    AKIHIRO SHIMIZU, AND SHOJIR.0 ASAI, MEMBER, IEEE , IEEE TI. TRANSACTIONS ON
    ELECTRON DEVICES, VOL. ED-30, NO. 6 , JUNE 1983
   A New Mode of Hot Carrier Degradation in 0.18pm CMOS Technologies- C.T. Liu,
    E.J. Lloyd, C.P. Chang, K.P.Cheung, J.I. Colonell, W.Y.C. Lai, R. Liu, C.S. Pai, H.
    Vaidya, and J.T. Clemens Bell Laboratories, Lucent Technologies, 700 Mountain Ave.,
    Murray Hill, NJ 07974
References
   “Three hot-carrier degradation mechanisms in deep- Submicron
    PMOSFET's “, Woltjer, Paulzen, Pomp, Lifka, Woerlee, IEEE transactions on electron
    devices, Jan 1995.
   ,” Positive Oxide charge generation during .25µm PMOSFET hot carrier
    degradation Woltjer, Paulzen, Pomp, Lifka, Woerlee, , IEEE Electron Device Letters, Oct
    1994.
   ““Analysis of gate oxide thickness hot Carrier effects in surface channel
    P-MOSFET's “Doyle, B.S. Mistry, K.R. Cheng-Liang Huang, IEEE Transactions on
    Electron Devices, Jan 1995.


   “Hot-carrier degradation of submicrometer p-MOSFETs wit
    Thermal/LPCVD composite oxide “Lee, Yung-Huei , IEEE transactions on electron
    devices, Jan 1993
   http://www.semiconfareast.com/hotcarriers2.htm
Thank You For Your Time

				
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