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					              Final Presentation
Implementation of DSP Algorithm on SoC

Student : Einat Tevel
Supervisor : Isaschar Walter
Accompanying engineer : Emilia Burlak

The project is conducted with
cooperation of Rafael.

                                        winter 2003/2004
             Project Goals - Review
   Studying and investigating the architecture of System on
    Programmable Chip (SoC).
   Deciding on the Software/Hardware partition to be
    implemented.
   Implementing a signal processing algorithm on the chosen
    platform.
Second Semester:
  Implementing a signal processing algorithm based on a
  FIR/IIR Filter with Programmable parameters.
    •   Simulating and checking the code of the algorithm in
        hardware and software.
    •   Running the algorithm on the board.
          Project Schedule
          Second Semester


Defining the algorithm - CIC Filters.
Design - Block Scheme.
Hardware.
Software.
Verification.
                     CIC Filters
                     Overview
   Cascaded Integrator-Comb Filters.
   Multirate filters used for realizing large sample
    rate changes in digital systems.
   Multiplierless structures, consists only of:
    Adders, Subtractors and Registers.
   Decimation.
   Interpolation.
                    CIC Filters
                     Structure
   Cascade of Integrators.
   Resampling Switch (decimate/expansion).
   Cascade of Differentiators.
                     CIC Filters
                     Parameters
   Number of Stages (N).
   Rate Change Factor (R).
   Differential Delay (M).
                   CIC Filters
                Hardware/Software
   Hardware:
       Generic implementation of Decimator.
       Generic implementation of Interpolator.
   Software:
       Filter parameters : N, R, M.
       Filter Mux Select : Dec/Int.
       Data input for filtering.
   All wrapped into one in SoC.
                           Design
                     System Components
                                                     UART
                     PPC 405
                                                      send/receive files.
                     PLB
                                                     PPC405
                                plb2opb
                                                      Software.
                                 bridge

                                                     OPB CIC Filters
                                                      Hardware Core.
                     OPB




OPB CIC    UART             GPIO
                                          SDRAM
                                                     LEDs.
 Filters                   (LEDs)
                                                     SDRAM.
           Monitor
                                      Design
                                    System Flow
                                                  -   Receiving file from PC.
                     PPC 405
                                                  -   File read and analyzed.
                     PLB
                                                  -   Sending parameters and
                                                      data to filters.
                                plb2opb
                                 bridge
                                                  -   Receiving processed data
                     OPB                              from filters.
           UART
                                                  -   Sending data to PC.
OPB CIC                     GPIO
                                          SDRAM
 Filters                   (LEDs)



           Monitor
                             Design
                       Block Scheme - Top

                                   -   OPB SW-HW Intfc
      Data
                                       Generic SW-HW interface.
      Addr    OPB
                          CIC
             SW-HW
OPB




              Intfc.
                         Filters   -   CIC Filters
                                       Implementation of the CIC
                                         Filters modules.
                 Block Scheme
                OPB SW-HW Intfc

                              Using IPIF (IP Interface):
Data          Data              a portable, pre-designed
Addr          Addr
                                bus interface, that takes
       IPIF
                     SW-HW      care of the bus interface
               wr
               rd
                      Intfc     signals, bus protocol and
                                other interface issues.
                              Block Scheme
                              SW-HW Intfc
                                   sw_rst
                                                   fifo_in_dout

                 fifo_in_en          FIFO IN
                                                   fifo_in_rd_en
                                                                   Consists of:
                     Data
                                                                   •   Address Decoder.
                                                   fifo_out_din


Data
                                    FIFO OUT
                                                  fifo_out_wr_en
                                                                   •   FIFOs.
                              control_reg_valid
       Address
                                                                       Control/Status Regs.
addr
                                                     start
                                                                   •
       Decoder                     Control Reg.    mux_select
                                                                       Other signals:
 rd
 wr                                                                •
                                                                            sw_rst
                                   Status Reg.
                                                      finish            •
                                  finish_en
                               Stages_num
                                                                        •   params
                               Samples_rate
                                Diff_delay
                                                   Block Scheme
                                                    CIC Filters
     sw_rst
      start

      finish
                                                                      Consists of:
                               filter_Din_en                CIC_DEC
   fifo_in_dout                                                       • CIC Decimator.
                                 filter_Din

                                                                      • CIC Interpolator.
  fifo_in_rd_en       CIC
   mux_select        Filters                   mux_Select
                     Intfc.
 mux_select_en                                                        • CIC Filters Intfc.
                                  filter_Dout_en
   fifo_out_din                                             CIC_INT
                                 filter_Dout
 fifo_out_wr_en

filter_params (x3)
                         Hardware
   Code written in VHDL :
    •   Generic CIC Filters: Decimator, Interpolator.
    •   Interfaces: SW-HW intfc, Filters Intfc.
   Using “user core reference design” to instantiate the
    IPIF and attach it to the logic.
   FIFO - generated core from CoreGen.
   Simulation – Using Modelsim.
              Software
             Flow Chart
 Wait for      Receive
Input file     Params
from PC       from PC


             Send Params     Send
                to Core    START to
                             Core




Send Data                   Wait for
from Core                   FINISH
   to PC                   from Core
                         Software
                          Code
   Code written in C :
    •   Check_leds function : counting using LEDs.
    •   Check_sdram function : Memory read/write.
    •   CIC function: previous flow chart in a while loop.
   Frequently used commands:
    •   XUartLite_RecvByte(uart_base_addr);
    •   XIo_Out32(cic_base_addr, control_reg);
    •   XIo_In32(cic_base_addr+20);
                      Verification

   Simulation of the CIC Algorithm in MATLAB:
    •   data_out = dec_param(data_in, N ,R ,M)
    •   data_out = int_param(data_in, N ,R ,M)
   The system’s output was compared to the
    MATLAB’s output using various inputs and
    parameters.
   MATLAB GUI.
    GUI
 Filter
Params




  Files


          Results
                     GUI
                    Features
   Filter Type, N, M, R, chosen by user.
   Data input file specified by user.
   HW input filename specified by user.
   Creates HW input file to be run by user.
   HW output filename specified by user.
   Runs SW simulation.
   Compares and shows results using graph.
                Hardware Interface
   INPUT:
    Receives file via UART using Hyper-Terminal.
    •   The file contains the data in the right format for the
        HW. The file can be created using the GUI.
   OUTPUT:
    Sends the results via UART using Hyper-
    Terminal.
    •   The results are captured into file.
        The file can be read using the GUI.
Hyper Terminal
       Conclusions and Remarks.

   SoC is a powerful platform for integrating
    Hardware and Software.

   Still new and therefore encountered some
    problems.
Thank You

				
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