The Wire
• Scaling has seen wire delays • The parasitics affect circuit
become a major concern whereas performance by:
in previous technology nodes they – Increasing signal propagation
were not even a secondary design delay.
issue. – Contributing to energy
• Wire parasitic effects differ from dissipation and power
those of transistors. distribution.
– Introducing extra noise sources
• Wire materials could be
which affect circuit reliability.
polysilicon, aluminum, copper or
diffusion materials (n+/p+). • A comprehensive wire model is
very complex
• Wires of today’s processes form
complex geometries that introduce
capacitive, resistive and inductive
parasitics.
The Wire
• Inter wire parasitics create • With these conditions inter wire
coupling effects between the capacitance can be ignored and all
different bus signals. parasitic capacitances modeled as
• A simplified wire model has: a capacitor to ground :- the
– The inductive effects ignored lumped capacitance model.
since it is assumed that the Current
resistance of the wire is large. Flow
– The short wires must have large L
cross-sections or low resistivity.
– Separation between neighboring W
wires is assumed to be large or H
wires that are close to each other tdi dielectric
run together only for a short
substrate
distance.
The Wire Capacitance
• In the diagram shown, the width • With scaling and increasingly
of the wire (W) is substantially dense circuits, the wires are
larger than the thickness of the placed close to each other.
insulating material. • The proximity of the wires make
• The electric field lines are fringing capacitance to become
assumed to be perpendicular to more dominant.
the capacitor plates.
• The wire capacitance can be
modeled as a parallel plate W
capacitor. cfringe
H
di
C pp WL
tdi cpp
• The dielectric of choice is SiO2.
Wire Capacitance
• The fringing capacitance Cfringe
is modeled using cylindrical wire
parallel
with a dimension equal to the
interconnect thickness H.
• The approximation of the wire
capacitance is:
di 2 di
Cwire C pp C fringe WL • Not all of the capacitive
tdi t
log di
H components terminate at ground,
• The lumped C wire model is not many connect to other wires.
complete for today’s technologies
since the wire is not completely
isolated from its surrounding
structures and is thus not only
capacitively coupled to ground.
Wire Resistance
• The resistance of the wire is given • At high frequencies a
L L
by: R A HW phenomenon called skin effect
• A rectangular wire is assumed. comes into play and resistance
• ρ is the resistivity of the material becomes frequency dependent.
measured in Ω-m. • Skin effect is an issue in wider
• Rho is constant in a given wires. Current crowds at the wire
technology and leads to the edges.
modification of the equation as
follows: R = RsquareL/W
H
• Rsquare is ρ/H and is the sheet
resistance of a material having
units of ohms per square
(Ω/square)
Wire Indctance
• Consequences of on-chip inductance • An ideal wire assumes that a voltage
include: change at one end of the wire
– Signal ringing propagates immediately to the wire’s
– Over-shoot other end.
– Signal reflection due to impedance • The wire becomes equipotential.
mismatch • This ideal approach still holds for
– Inductive coupling between lines short wires, also designers interested
– Switching noise due to Ldi/dt voltage only in circuit behavior can use this
drops. ideal model.
• The inductance of a section of a • Circuit parasitics of a wire are
circuit can be evaluated as V = distributed along its length instead of
Ldi/dt being lumped at a single position.
• Inductance per unit length of wire and • With low to medium switching
capacitance C are related by the frequencies and small resistive
expression CL=ε. components we can consider only a
lumped capacitive component of wire.
Lumped C Wire Model
• We can lump the total wire
resistance into a single R and the
Vout
Cwire
global capacitance into a single C.
Driver
• The lumped RC model is
Vout inaccurate for long interconnects.
RDriver CLumpe • The RC network can enhance
Source d
understanding of a distributed RC
network.
• In order to evaluate the RC model
• This is a simple but yet effective we use the RC tree which has:
model and widely used in digital – Has a single input node S.
design. – Has all capacitors between a node
• There is a need to include the and ground.
resistive as well as the capacitive – Has no resistive loops
components.
The Lumped RC Model
• The resistive-capacitive • There is a unique resistive
R
(RC) model. 2 2
path between the source
C2
R4
node S and any node i on the
S 1 R3 4
R1
network
3 Ri C4
C1
i
• A shared path resistance
C3
R2
Ci from the root node to nodes
R1 C2
k and i is:
Rik R j R j pathS i paths k
R3
C1
C3 • The equation describes the
td 2 C1R1 C2 R1 R2 C3 R1
common resistance from
• R1 is the common resistance input to nodes i and k.
in the path. •
The Elmore Delay Model
• If we have a step input and if we • The segment’s capacitance
assume that all nodes are initially becomes c(L/N).
2
L
at logic 0 we have: DN rc 2 rc Nrc
N N
di C
k 1
k Rik
rcL2
N N 1 N 1
RC
2N
2
2N
• The Elmore Delay Model offers • The above equation calculates the
designers a quick estimate of the time constant of the wire using the
delay. Elmore Delay Model.
• To compute the time constant of a • For rL = R and cL = C we have
wire of length L, we partition the the Lumped R and C.
wire into N identical segments. • If there are numerous segments
• Each segment has a length of L/N. (N Large) the RC model
• The segment resistance becomes approaches that of a distributed 2
r(L/N). RC line with: RC rcL
2
DN
2
The Elmore Delay Model
Vin rL Vj-1 rL Vj rL Vj+1 rL Vout
• The delay of a wire is a quadratic
cL cL cL cL
function of its length i.e. doubling
the length of a wire quadruples its Ij-1 Ij Ij+1
delay.
• Find the voltage at node i?
• The lumped RC model
underestimates the delay by 0.5 • Find the response at node i with
times. respect to time?
dVi V V j V j V j 1
• The Elmore Delay model only C I j 1 I j j 1
dt R R
estimates the value of the
cL
V j
V j 1 V j V j 1 V j
dominant component. t rL
• We have discussed briefly that the • As the number of segments in the
Elmore Model can be used to network becomes large with
estimate the delay complex sections becoming smaller we 2
transistor netwworks. have: rc dV d V 2
dt dx
The Diffusion Equation
• The variable x in the previous • The solution for the propagation
equation is the distance from the of a voltage step along the wire
input to the point of interest. shows that the rise/fall delay tx
• The variable r is the resistance per along a wire of length x is: tx=kx2.
unit length. • k is a constant given by: k 2mEh 2
• c is the capacitance per unit • E is given by: E mc2
length. • The mass m and the velocity c2
• V is the voltage at the particular are the variables of this equation.
point on the wire. RCnn 1
• The equation t 0.7 2
n results
• The equation has no closed form from a discrete analysis of the
solution. circuit with n being the number of
for t RC
Voutt 2erfc RC
4t
sections.
• The 0.7 factor accounts for the
rise and/or fall delay to half rail.
The Diffusion Equation
• As n becomes very large i.e. • So far the inductance of the wire
individual sections become very has been negligible, but when the
2
small we have: tl 0.7 rcl circuits switch fact and the
2 interconnect wire is of high
• The discussed wire delays have
significant bearing on circuit quality the inductance of the wire
performance and when the starts to dominate delay behavior.
propagation delay of the wire is • At this point transmission line
greater than the propagation delay effects have to be considered.
of the gate (tpRC>tpgate) that’s • Inductance is distributed over the
cause for concern. wire just like resistance and
• The critical length of a wire is capacitance.
described by: • The distributed rlc model
describes the transmission line.
t pgate
Lcrit
0.38rc
The transmission Line
• The transmission line is the most • In simple terms energy is
accurate approximation of actual transferred between capacitive
interconnect behavior. (electric field) and inductive
• The signal now propagates over a (magnetic field) modes.
wire like a wave. • At point x at time t we have:
i
• This is different from the x
ri l ;
t
distributed rc model in which the i cv
g c
x t t
signal diffuses from source to • The leakage conductance is
destination. assumed to be 0.
• As a wave the signal propagates 2 2
rc lc 2
by alternatively transferring x 2 t t
energy from the electric field to
the magnetic field.
The Transmission Line
• First: assume that the resistance of • Line termination determines how
the line is negligible. much the wave is reflected upon
• The result is a lossless arrival at the end of the wire.
transmission line. • This would be capacitive
• No voltage drops just a termination since the line is lc.
capacitive-inductive (cl) model. • Chip interconnects are not wide
• The wave propagation equation enough to be treated as lossless
2 2
becomes: 2 lc 2 2 2 2 transmission lines.
x t t • The resistance of an interconnect
• A step input applied to a lossless
transmission line propagate along is an important factor.
1 1 c
the line with a speed: lc
o
r r
• The response of a lossy
• The behavior of the transmission transmission line to a unit step
line is influenced by the function combines wave
termination of the line. propagation with a diffusion
component.
The Lossy Transmission Line
• The diffusive component affects • The transmission line is
the amplitude of the signal. considered lossless when the total
• If the resistive component resistance is substantially smaller
becomes dominant then the line than the characteristic impedance
behaves like a distributed rc. or when R
• The transmission line effects are
used when tr and tf are smaller
than the time of flight.
• The wire’s total resistance must
be restricted to R<5Z0 for
transmission line effects to be
considered.
• If this is not the case then the
distributed RC model is sufficient.