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Sequential Circuit Synthesis - II Virendra Singh Indian Institute of Science Bangalore IEP on Digital System Synthesis, IIT Kanpur Incompletely Specified Machine The specified behaviour of a machine with partially specified transitions can be described by another machine whose state transitions are completely specified The transformation is accomplished by replacing all the dashes in the next state entries by T and adding a terminal state T whose output are unspecified PS NS, z PS NS, z X=0 X=1 X=0 X=1 A B, 1 T, -- A B, 1 --, -- B T, 0 C, 0 B --, 0 C, 0 C A, 1 B, 0 C A, 1 B, 0 T T, -- T, -- Dec 14,2007 Sequential@iitk 2 Compatible States State Si of M1 is said to cover, or contain, state Sj of M2 if and only if every input sequence applicable to Sj is also applicable to Si, and its application to both M1 and M2 when they are initially in Si and Sj, respectively, results in identical output sequences whenever the outputs of M2 are specified Machine M1 is said to cover machine M2 if and only if, for every state Sj in M2, there is a corresponding state Si in M1 s.t. Si covers Sj Dec 14,2007 Sequential@iitk 3 Compatible States Two states Si and Sj of machine M are compatible, if and only if, for every input sequence applicable to to both Si and Sj, the same output sequence will be produced whenever both outputs are specified and regardless of whether Si or Sj is the initial state Si and Sj are compatible, if and only if, their outputs are not conflicting (i.e., identical when specified) and their Ii-successor, for every Ii for which both are specified, are the same or also compatible. A set of states (Si, Sj, Sk, ….) is called compatible if all its members are compatible Dec 14,2007 Sequential@iitk 4 Compatible States A compatible Ci is said to be larger than, or to cover, another compatible Cj, if and only if, every state in Cj is also contained in Ci A compatible is maximal if it is not covered by any other compatible Dec 14,2007 Sequential@iitk 5 Compatible States PS NS, z PS NS, z X = 0 X=1 X = 0 X= 1 A C, 1 E, 1 A C, 1 E, -- C B, 0 A, 1 B C, -- E, 1 D D, 0 E, 1 C B, 0 A, 1 E D, 1 A, 0 D D, 0 E, 1 PS NS, z E D, 1 A, 0 X= 0 X=1 AE - α β, 1 α, 0 BCD - β β, 0 α, 1 Dec 14,2007 Sequential@iitk 6 Compatible States A set of states is compatible if and only if every pair of the states in that set is compatible PS NS, z PS NS, z X=0 X=1 X=0 X=1 A A, 0 C, 0 A A, 0 C, 0 B B, 0 B, -- B’ B’, 0 B’’, -- C B, 0 A, 1 B’’ B+, 0 B’, 1 C B+, 0 A, 1 Dec 14,2007 Sequential@iitk 7 Compatible States PS NS, z PS NS, z X= 0 X=1 X= 0 X=1 (AB’) – α α, 0 β, 0 (AB’) – α α, 0 β, 0 (B’’C) - β β, 0 α, 1 (B”C) – β α, 0 α, 1 B+ = B” B+ = B’ Dec 14,2007 Sequential@iitk 8 Merger Graph •Transforming into fully PS NS, z specified machine may I1 I2 I3 I4 not be optimal one A --- C, 1 E, 1 B, 1 • First generate the entire set of compatibles B E, 0 --- --- --- •Select an appropriate C F, 0 F, 1 --- --- subset, which will form D --- --- B, 1 --- the basis of state reduction leading to E --- F, 0 A, 0 D, 1 minimum machine F C, 0 --- B, 0 C, 1 Dec 14,2007 Sequential@iitk 9 Merger Graph • A set of states is compatible if and only if every pair of states in that set is compatible • It is sufficient to consider pair of states and use them to generate entire set • Compatible pair of states is referred as compatible pairs • Let the Ik-successors of Si and Sj be Sp and Sq, respectively; then (Sp Sq) said to be implied by (SiSj) • (SpSq) are referred as implied pair Dec 14,2007 Sequential@iitk 10 Merger Graph Merger graph is undirected graph 1. It consists of n-vertices, each of which corresponds to a state of M 2. For each pair of states (Si Sj) in M whose next state and output entries are not conflicting, an undirected arc is drawn between vertices Si and Sj 3. If for a pair of states (Si Sj) the corresponding outputs under all inputs are not conflicting, but successors are not the same, an interrupted arc is drawn between Si and Sj, and then implied pairs are entered in the space Dec 14,2007 Sequential@iitk 11 Merger Graph PS NS, z A I1 I2 I3 I4 (CF) A --- C, 1 E, 1 B, 1 F B B E, 0 --- --- --- (CF) C F, 0 F, 1 --- --- (AB) (EF) D --- --- B, 1 --- (CD) (BE) C E --- F, 0 A, 0 D, 1 E F C, 0 --- B, 0 C, 1 D Dec 14,2007 Sequential@iitk 12 Merger Graph Merger graph is undirected graph Nine compatible pairs (AB), (AC), (AD), (BC), (BD), (BE), (CD), (CF), (EF) (AB), (AC), (BC) are compatible => (ABC) compatible Find minimal set of compatible {(ABCD), (BC), (BE), (DE)} Dec 14,2007 Sequential@iitk 13 Merger Graph A set of compatible (for machine M) is said to be closed if, for every compatible contained in the set, all its implied also contained in the set. A closed set of compatibles which contains all the sates of M is called closed covering A set {(AD), (BE), (CD)} is a closed covering PS NS, z I1 I2 I3 I4 (AB) - α δ, 0 β, 1 δ, 1 α, 1 (CD) - β δ, 0 δ, 1 α, 1 --- (EF) - δ β, 0 δ, 0 α, 0 Β, 0 Dec 14,2007 Sequential@iitk 14 Compatible Graph The compatible graph is a directed graph whose vertices corresponding to all compatible pairs, and arc leads from vertex (Si Sj) to vertex (Sp Sq) if and only if (Si Sj) implies (Sp Sq) It is a tool which aids in the search for a minimal closed covering Compatible pairs are obtained from merger graph Dec 14,2007 Sequential@iitk 15 Compatibility Graph PS NS, z A (CF) I1 I2 I3 I4 (BE) (BC) A --- --- E, 1 --- E B B C, 0 A, 1 B, 0 --- (AE) C C, 0 D, 1 --- A, 0 (BC) D --- E, 1 B, -- --- (BC) (AD) E B, 0 --- C, -- B, 0 D (AB) (DE) C Merger Graph Dec 14,2007 Sequential@iitk 16 Compatibility Graph A (CF) AC (BE) (BC) B E AD (AE) (BC) BE (BC) (AD) BC D (AB) (DE) CD C DE Merger Graph Dec 14,2007 Sequential@iitk 17 Minimization using Network Model Behaviour of sequential circuit can be described by traces, i.e., sequence of inputs and outputs Various approaches to optimize Ignore registers and optimize the combinational logic Retiming – move position of registers only Dec 14,2007 Sequential@iitk 18 Retiming Minimize cycle time or the area of synchronous circuits by changing the position of the registers Cycle time is bounded from below by the critical path delay in the combinational circuit Retiming aims at placing the registers in the appropriate position, so that the critical paths they embrace are as short as possible Moving registers may increase or decrease the number of regsisters Dec 14,2007 Sequential@iitk 19 Retiming + + + Host δ δ δ Dec 14,2007 Sequential@iitk 20 Dec 14,2007 Sequential@iitk 21 Dec 14,2007 Sequential@iitk 22 Example Machine M2 PS NS, z P0 = (ABCDEFG) X=0 X=1 P1 = (ABCDFG) (E) A E, 0 C, 0 P2 = (AF) (BCDG) (E) B C, 0 A, 0 P3 = (AF) (BD) (CG) (E) C B, 0 G, 0 P4 = (A) (F) (BD) (CG) (E) D G, 0 A, 0 P5 = (A) (F) (BD) (CG) (E) E F, 1 B, 0 F E, 0 D, 0 G D, 0 G, 0 Dec 14,2007 Sequential@iitk 23

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