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CPRE 583
Reconfigurable Computing
Lecture 3: Wed 9/1/2010
(Reconfigurable Computing Hardware)
Instructor: Dr. Phillip Jones
(phjones@iastate.edu)
Reconfigurable Computing Laboratory
Iowa State University
Ames, Iowa, USA
http://class.ece.iastate.edu/cpre583/
1 - CPRE 583 (Reconfigurable Computing): Reconfigurable Computing Hardware Iowa State University (Ames)
Announcements/Reminders
• Send me top 3 choices for topic for mini literary survey
– PowerPoint tree due: Fri 9/17 by class, so try to have to
me by 9/16 night. My current plan is to summarize
some of the classes findings during class.
– Final 5-10 page write up on your tree due: Fri 9/24
midnight.
2 - CPRE 583 (Reconfigurable Computing): Reconfigurable Computing Hardware Iowa State University (Ames)
Overview
• Logic
• Interconnect/Routing
• Optimized resources
– Adders, Multipliers
– Memory
– System-on-chip building blocks
• Example Commercial FPGA structure
3 - CPRE 583 (Reconfigurable Computing): Reconfigurable Computing Hardware Iowa State University (Ames)
What you should learn
• Basic understanding of the major
components that make up an FPGA device.
4 - CPRE 583 (Reconfigurable Computing): Reconfigurable Computing Hardware Iowa State University (Ames)
Basic FPGA Architectural Components
• FPGA: Field Programmable Gate Array
• Sea of general purpose logic gates
CLB CLB CLB CLB
CLB CLB CLB CLB Configurable Logic Block
(CLB)
CLB CLB CLB CLB
CLB CLB CLB CLB
5 - CPRE 583 (Reconfigurable Computing): Reconfigurable Computing Hardware Iowa State University (Ames)
Computational Fabric - LUT
LUT = Look up Table
Z
A
B 4-LUT
C
D
ABCD Z
X000 0
ABCD Z ABCD Z ABCD Z X001 1
0000 0000 0 0000 0 X010 0
0001 0001 0 0001 1
X101 0
1110 1110 0 1110 1 X110 1
1111 1111 1 1111 1 X111 1
B
A A
B Z B Z Z
AND OR C 1 2:1
C C D 0Mux
D D
6 - CPRE 583 (Reconfigurable Computing): Reconfigurable Computing Hardware Iowa State University (Ames)
Computational Fabric - LUT
LUT = Look up Table
Z
A
B 4-LUT
C
D
How many 4-LUTs needed
to OR 32-bits
Draw
32
1
7 - CPRE 583 (Reconfigurable Computing): Reconfigurable Computing Hardware Iowa State University (Ames)
Computational Fabric - LUT
LUT = Look up Table
Z
A
B 4-LUT
C
D
How many 4-LUTs needed
to OR 32-bits
Draw
4 LUT
4 LUT 4
32 4 LUT LUT
4 LUT
4 1
LUT
4 LUT
4 LUT 4
4 LUT LUT
4 LUT
8 - CPRE 583 (Reconfigurable Computing): Reconfigurable Computing Hardware Iowa State University (Ames)
Computational Fabric - LUT
LUT = Look up Table
Z
A
B 4-LUT
C
D
How many 4-LUTs needed
to AND 2-bits with the 32-bit OR
Draw
4 LUT
4 LUT 4
32 4 LUT LUT
4 LUT
4 1
LUT
4 LUT
4 LUT 4
4 LUT LUT
4 LUT
9 - CPRE 583 (Reconfigurable Computing): Reconfigurable Computing Hardware Iowa State University (Ames)
Computational Fabric - LUT
LUT = Look up Table
Z
A
B 4-LUT
C
D
How many 4-LUTs needed
to AND 2-bits with the 32-bit OR
Draw
4 LUT
4 LUT 4
32 4 LUT LUT
4 LUT
4 1
LUT
4 LUT
4 LUT 4
4 LUT LUT
4 LUT
10 - CPRE 583 (Reconfigurable Computing): Reconfigurable Computing Hardware Iowa State University (Ames)
Computational Fabric - LUT
LUT = Look up Table
Z
A
B 4-LUT Write out the
C
D Truth table
ABCD Z
How many 4-LUTs needed 0000
to AND 2-bits with the 32-bit OR 0001
0010
Draw 0011
4 LUT 0100
0101
4 LUT 4
32 0110
4 LUT LUT 0111
4 LUT 1000
4 1 1001
LUT 1010
4 LUT
1011
4 LUT 4 1100
4 LUT LUT 1101
4 LUT 1110
1111
11 - CPRE 583 (Reconfigurable Computing): Reconfigurable Computing Hardware Iowa State University (Ames)
Computational Fabric - LUT
LUT = Look up Table
Z
A
B 4-LUT Write out the
C
D Truth table
ABCD Z
How many 4-LUTs needed 0000 0
to AND 2-bits with the 32-bit OR 0001 0
0010 0
Draw 0011 0
4 LUT 0100 0
0101 0
4 LUT 4
32 0110
4 LUT LUT 0111
4 LUT 1000 0
4 1 1001 0
LUT 1010 0
4 LUT
1011 0
4 LUT 4 1100 0
4 LUT LUT 1101 0
4 LUT 1110
1111
12 - CPRE 583 (Reconfigurable Computing): Reconfigurable Computing Hardware Iowa State University (Ames)
Computational Fabric - LUT
LUT = Look up Table
Z
A
B 4-LUT Write out the
C
D Truth table
ABCD Z
How many 4-LUTs needed 0000 0
to AND 2-bits with the 32-bit OR 0001 0
0010 0
Draw 0011 0
4 LUT 0100 0
0101 0
4 LUT 4
32 0110 0
4 LUT LUT 0111 1
4 LUT 1000 0
4 1 1001 0
LUT 1010 0
4 LUT
1011 0
4 LUT 4 1100 0
4 LUT LUT 1101 0
4 LUT 1110 1
1111 1
13 - CPRE 583 (Reconfigurable Computing): Reconfigurable Computing Hardware Iowa State University (Ames)
Computational Fabric - LUT
LUT = Look up Table
Z
A
B 4-LUT
C
D
How could one build a 4-LUT?
ABCD 4
1x16
Memory
0
0
0 16:1
Z
Mux
0
0
1
14 - CPRE 583 (Reconfigurable Computing): Reconfigurable Computing Hardware Iowa State University (Ames)
Computational Fabric - LUT
LUT = Look up Table
Z
A
B 4-LUT
C
D
How many different 4 input functions can a 4-LUT implement?
216 = 65536
ABCD 4
1x16
Memory
0
0
0 16:1
Z
Mux
0
0
1
15 - CPRE 583 (Reconfigurable Computing): Reconfigurable Computing Hardware Iowa State University (Ames)
Computational Fabric - LUT
LUT = Look up Table
Z
A
B 4-LUT
C
D
How many different N input functions can a N-LUT implement?
ABCD 4
1x16
Memory
0
0
0 16:1
Z
Mux
0
0
1
16 - CPRE 583 (Reconfigurable Computing): Reconfigurable Computing Hardware Iowa State University (Ames)
Computational Fabric - LUT
LUT = Look up Table
Z
A
B 4-LUT
C
D
How many different N input functions can a N-LUT implement?
ABCD N
1x16
Memory
0
0
0 16:1
Z
Mux
0
0
1
17 - CPRE 583 (Reconfigurable Computing): Reconfigurable Computing Hardware Iowa State University (Ames)
Computational Fabric - LUT
LUT = Look up Table
Z
A
B 4-LUT
C
D
How many different N input functions can a N-LUT implement?
= 22N
ABCD N
1x2N
Memory N=4
0 16 =224=65536
0
2
0 16:1
Z
Mux
0
0
1
18 - CPRE 583 (Reconfigurable Computing): Reconfigurable Computing Hardware Iowa State University (Ames)
Granularity of Computation
Trade-offs associated with LUT size
Example: 2-LUT (4=2x2 bits) vs. 10-LUT (1024=32x32 bits)
1024-bits
2-LUT
Microprocessor 10-LUT
1024-bits
19 - CPRE 583 (Reconfigurable Computing): Reconfigurable Computing Hardware Iowa State University (Ames)
Granularity of Computation
Trade-offs associated with LUT size
Example: 2-LUT (4=2x2 bits) vs. 10-LUT (1024=32x32 bits)
1024-bits
4
2-LUT
op
A 3 3
Microprocessor 3 10-LUT
B
1024-bits
20 - CPRE 583 (Reconfigurable Computing): Reconfigurable Computing Hardware Iowa State University (Ames)
Granularity of Computation
Trade-offs associated with LUT size
Example: 2-LUT (4=2x2 bits) vs. 10-LUT (1024=32x32 bits)
1024-bits
4
2-LUT
op
A 3 3
Microprocessor 3 10-LUT
B
4
op 1024-bits
A 3 3
B 3
4
op
3 3
A
B 3
21 - CPRE 583 (Reconfigurable Computing): Reconfigurable Computing Hardware Iowa State University (Ames)
Granularity of Computation
Trade-offs associated with LUT size
Example: 2-LUT (4=2x2 bits) vs. 10-LUT (1024=32x32 bits)
1024-bits
4
2-LUT
op
A 3
Microprocessor 3 3 10-LUT
B
1024-bits
op
A 3
3
B 3
4
op
A 3
3
B 3
22 - CPRE 583 (Reconfigurable Computing): Reconfigurable Computing Hardware Iowa State University (Ames)
Granularity of Computation
Trade-offs associated with LUT size
Example: 2-LUT (4=2x2 bits) vs. 10-LUT (1024=32x32 bits)
1024-bits
4
2-LUT
op
A 3
Microprocessor 3 3 10-LUT
B
4 1024-bits
op
A 3
3 3
B
4
op
A 3
3
3
B
23 - CPRE 583 (Reconfigurable Computing): Reconfigurable Computing Hardware Iowa State University (Ames)
Granularity of Computation
Trade-offs associated with LUT size
Example: 2-LUT (4=2x2 bits) vs. 10-LUT (1024=32x32 bits)
1024-bits
2-LUT
10-LUT
Bit logic and 1024-bits
constants
24 - CPRE 583 (Reconfigurable Computing): Reconfigurable Computing Hardware Iowa State University (Ames)
Granularity of Computation
Trade-offs associated with LUT size
Example: 2-LUT (4=2x2 bits) vs. 10-LUT (1024=32x32 bits)
1024-bits
2-LUT
10-LUT
Bit logic and 1024-bits
constants
(A and “1100”)
or (B or “1000”)
25 - CPRE 583 (Reconfigurable Computing): Reconfigurable Computing Hardware Iowa State University (Ames)
Granularity of Computation
Trade-offs associated with LUT size
Example: 2-LUT (4=2x2 bits) vs. 10-LUT (1024=32x32 bits)
1024-bits
2-LUT
A
10-LUT
B
Bit logic and 1024-bits
constants
(A and “1100”)
or (B or “1000”)
26 - CPRE 583 (Reconfigurable Computing): Reconfigurable Computing Hardware Iowa State University (Ames)
Granularity of Computation
Trade-offs associated with LUT size
Example: 2-LUT (4=2x2 bits) vs. 10-LUT (1024=32x32 bits)
1024-bits
2-LUT
4
A AND
10-LUT
Bit logic and 1 1024-bits
constants OR Area that was
(A and “1100”) required using
or (B or “1000”) 0 2-LUTS
4
B OR
It’s much worse,
each 10-LUT only has one output
27 - CPRE 583 (Reconfigurable Computing): Reconfigurable Computing Hardware Iowa State University (Ames)
Computational Fabric - DFF
Z
A
B 4-LUT
C
D
• LUTs are fine for implementing any arbitrary
combinational logic (output is ONLY a function of its
inputs) function. But what about sequential logic
(output is a function of input AND previous state
information)?
Need Memory!!
28 - CPRE 583 (Reconfigurable Computing): Reconfigurable Computing Hardware Iowa State University (Ames)
Computational Fabric - DFF
Z(t)
A
B 4-LUT Z(t+1)
C
D DFF
DFF = D Flip Flop
Detect the pattern “1101”
1/0 1/0 0/0
Input/output
1/1
0/0 1 11 110 1101
0/0 1/0
Start
29 - CPRE 583 (Reconfigurable Computing): Reconfigurable Computing Hardware Iowa State University (Ames)
Computational Fabric - DFF
Z(t)
A
B 4-LUT Z(t+1)
C
D DFF
DFF = D Flip Flop
Increase circuit performance (pipelining)
4 LUT delays
A
B per output
C 4-LUT 4-LUT 4-LUT 4-LUT
D DFF DFF DFF DFF
1 DFF delay
A
B per output
C 4-LUT 4-LUT 4-LUT 4-LUT
D DFF DFF DFF DFF
30 - CPRE 583 (Reconfigurable Computing): Reconfigurable Computing Hardware Iowa State University (Ames)
Communication: Interconnect & Routing
Need a mechanism to move results of computation around.
CLB CLB CLB CLB CLB CLB
CLB CLB CLB CLB CLB CLB
CLB CLB CLB CLB CLB CLB
CLB CLB CLB CLB CLB CLB
CLB CLB CLB CLB CLB CLB
CLB CLB CLB CLB CLB CLB
31 - CPRE 583 (Reconfigurable Computing): Reconfigurable Computing Hardware Iowa State University (Ames)
Communication: Interconnect & Routing
Need a mechanism to move results of computation around.
Nearest Neighbor:
CLB CLB CLB CLB CLB CLB
CLB CLB CLB CLB CLB CLB
CLB CLB CLB CLB CLB CLB
CLB CLB CLB CLB CLB CLB
CLB CLB CLB CLB CLB CLB
CLB CLB CLB CLB CLB CLB
32 - CPRE 583 (Reconfigurable Computing): Reconfigurable Computing Hardware Iowa State University (Ames)
Communication: Interconnect & Routing
Need a mechanism to move results of computation around.
Nearest Neighbor:
CLB CLB CLB CLB CLB CLB
CLB CLB CLB CLB CLB CLB
Segmented:
CLB CLB CLB CLB CLB CLB
CLB CLB CLB CLB CLB CLB
CLB CLB CLB CLB CLB CLB
CLB CLB CLB CLB CLB CLB
33 - CPRE 583 (Reconfigurable Computing): Reconfigurable Computing Hardware Iowa State University (Ames)
Communication: Interconnect & Routing
Need a mechanism to move results of computation around.
Nearest Neighbor:
CLB CLB CLB CLB CLB CLB
CLB CLB CLB CLB CLB CLB
Segmented:
CLB CLB CLB CLB CLB CLB
CLB CLB CLB CLB CLB CLB
Hierarchical:
CLB CLB CLB CLB CLB CLB
CLB CLB CLB CLB CLB CLB
34 - CPRE 583 (Reconfigurable Computing): Reconfigurable Computing Hardware Iowa State University (Ames)
Optimized Resources: Dedicated Logic
LUTs + DFFs can implement any arbitrary digital
logic. But not optimally (ASICs give make much
better use of silicon area for Power, Speed, routing
resources)
• Arithmetic
– Add, Multiply
• On chip memory
• System on chip building blocks
– Processor, PCI-express, Gigabit Ethernet, ADC,
etc.
35 - CPRE 583 (Reconfigurable Computing): Reconfigurable Computing Hardware Iowa State University (Ames)
Optimized Resources: Dedicated Logic
Fast Addition generate propagate
Carry out logic
Two output LUT
A3
c4 6-LUT
Carry Look Ahead B3 Sum 3
A2 B2
A1 A2
B1 P1
CLB P2 6-LUT Sum 2
Carry1 B2
A1
B1 G1 Carry
Carry1
G2
2
A1
A1 6-LUT
B1 Sum Sum Sum 1
CLB B1
Carry1 1 2
Dedicated routing
resources Carry in
36 - CPRE 583 (Reconfigurable Computing): Reconfigurable Computing Hardware Iowa State University (Ames)
Optimized Resources: Dedicated Logic
Embedded Memory 96 bits, 300 MHz
8
12
37 - CPRE 583 (Reconfigurable Computing): Reconfigurable Computing Hardware Iowa State University (Ames)
Optimized Resources: Dedicated Logic
Embedded Memory 18 Kbits, 550 MHz
8
Dedicated
12 memory
block
38 - CPRE 583 (Reconfigurable Computing): Reconfigurable Computing Hardware Iowa State University (Ames)
Optimized Resources: Dedicated Logic
Multiplication
18x18 multiply
Type # LUTs Latency Speed
LUT ~400 5 clks 380 MHz
Dedicated
0 3 clks 450 MHz
18x18 Multiplier
Virtex-5 (6-LUTs)
Very rough estimate of Silicon area comparison
(assuming SX95 andLX110 have about the same die size)
In other word you can replace
6-LUT 6-LUT one LUT based 18x18 multiplier
18x18 With 100 dedicated 18x18
Multiplier Multipliers!!!
6-LUT 6-LUT
39 - CPRE 583 (Reconfigurable Computing): Reconfigurable Computing Hardware Iowa State University (Ames)
Optimized Resources: Dedicated Logic
Processor
PowerPC hard-core MicroBlaze soft-core
• 500 MHz
•Super scalor • 250 MHz
•Highspeed 2x5 switch fabric • Simple scalar
40 - CPRE 583 (Reconfigurable Computing): Reconfigurable Computing Hardware Iowa State University (Ames)
Optimized Resources: Dedicated Logic
System on Chip Dedicated Logic
Reconfigurable Logic
Sensor
ADC
RAM Sensor
Matrix Multiplier
Coprocessor
PID Motor
Ethernet Data Controller
MAC Buffer
Also see Actel Fusion:http://www.actel.com/products/fusion/default.aspx
41 - CPRE 583 (Reconfigurable Computing): Reconfigurable Computing Hardware Iowa State University (Ames)
Xilinx CLB Architecture
• Virtex 5 FPGA User Guide
42 - CPRE 583 (Reconfigurable Computing): Reconfigurable Computing Hardware Iowa State University (Ames)
Questions/Comments/Concerns
43 - CPRE 583 (Reconfigurable Computing): Reconfigurable Computing Hardware Iowa State University (Ames)
Computational Fabric - LUT
• N-Lut, 3,4…6,…8-LUT
– AND, XOR, NOT
– Exercises
• How many 4-LUTs to OR 32 bits (draw)
• How many 4-LUTs to AND 2 bits with the OR of
these 32 bits (draw)
• Draw the truth table for the 4-LUT that gives the final
output
– How could one implement a LUT (Memory + MUX)
– How many ways can a 4-LUT be programmed
– How many ways can a N-LUT be programmed
• Granularity trade-off: Functionality vs. propagation
delay (2-LUT -> CPU), bit-level vs. datapath
44 - CPRE 583 (Reconfigurable Computing): Reconfigurable Computing Hardware Iowa State University (Ames)
Computational Fabric - DFF
• Enable building circuits that can store information
(sequential circuits, state machines)
• Enables pipelining to increase operating frequency/
throughput
45 - CPRE 583 (Reconfigurable Computing): Reconfigurable Computing Hardware Iowa State University (Ames)
Communication: Interconnect & Routing
• Need a mechanism to move the results of a LUT to
other LUTs.
• Island stale (Array of CB)
– Nearest neighbor (paper on reconfigure arch that uses
this)
• Not scalable (large delays, and uses logic elements for
routing?)
– Segmented (different length for latency trade-off)
• Multi hop scales < O(N)?
• Avoid using logic
– Hierarchical (good for apps with lots of local
communication and little remote communication)
• Typical an FPGA silicon area will be 10% logic and
90% interconnect!!
46 - CPRE 583 (Reconfigurable Computing): Reconfigurable Computing Hardware Iowa State University (Ames)
Optimized Resources: Hard Cores
• LUTs + DFFs can implement any arbitrary digital
logic. But not optimally (ASICs give make much
better use of silicon area for Power, Speed,
routing resources)
• Arithmetic
– Add, Mult
• On chip memory
• System on chip building blocks
– Processor, PCI-express, Gigbit Ethernet, A/D
47 - CPRE 583 (Reconfigurable Computing): Reconfigurable Computing Hardware Iowa State University (Ames)
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