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1:2demultiplexer
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library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity fd is
Port ( d : in STD_LOGIC;
s0 : in STD_LOGIC;
y0 : out STD_LOGIC;
y1 : out STD_LOGIC);
architecture Behavioral of fd is
begin
y0 <= (d and (not s0));
y1 <= (d and s0);
end Behavioral;
JK flip flop
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity fgf is
Port ( clk : in STD_LOGIC;
j : in STD_LOGIC;
k : in STD_LOGIC;
reset : in STD_LOGIC;
q : out STD_LOGIC;
qbar : out STD_LOGIC);
end fgf;
architecture Behavioral of fgf is
signal state : std_logic;
signal input : std_logic_vector(1 downto 0);
begin
input<=j&k;
p:process(clk,reset)is
begin
if(reset='1')then
state<='0';
else if(rising_edge(clk))then
case(input)is
when "11" =>
state<=not state;
when "10" =>
state <='1';
when "01" =>
state <='0';
when others =>
null;
end case;
end if;
end if;
end process;
q <= state;
qbar<=not state;
end Behavioral;
1:4 demultiplexer
ibrary IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity ferfgt is
Port ( d : in STD_LOGIC;
s0 : in STD_LOGIC;
s1 : in STD_LOGIC;
y0 : out STD_LOGIC;
y1 : out STD_LOGIC;
y2 : out STD_LOGIC;
y3 : out STD_LOGIC);
end ferfgt;
architecture Behavioral of ferfgt is
begin
y0 <= (d and (not s1)and (not s0));
y1 <= ( d and (not s1) and s0) ;
y2 <= (d and s1 and (not s0));
y3 <= (d and s1 and s0);
end Behavioral;
4bit counter
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity ery is
Port ( c : in STD_LOGIC;
clr : in STD_LOGIC;
up_down : in STD_LOGIC;
q : out STD_LOGIC_VECTOR (3 downto 0));
end ery;
architecture Behavioral of ery is
signal tmp:std_logic_vector(3 downto 0);
begin
process(c,clr)
begin
if(clr='1')then
tmp<="0000";
else if(c'event and c='1')then
if(up_down='1')then
tmp<=tmp+1;
else
tmp<=tmp-1;
end if;
end if;
end if;
end process;
q <= tmp;
end Behavioral;
D-flipflop
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity sfxg is
Port ( d : in STD_LOGIC;
clk : in STD_LOGIC;
reset : in STD_LOGIC;
q : out STD_LOGIC);
end sfxg;
architecture Behavioral of sfxg is
begin
process ( clk)
begin
if( clk' event and clk='1')then
if reset ='0'then
q<= '0';
else
q<=d;
end if;
end if;
end process;
end Behavioral;
4:1 multiplexer:
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity regqer is
Port ( i0 : in STD_LOGIC;
i1 : in STD_LOGIC;
i2 : in STD_LOGIC;
i3 : in STD_LOGIC;
s1 : in STD_LOGIC;
s2 : in STD_LOGIC;
y : out STD_LOGIC);
end regqer;
architecture Behavioral of regqer is
begin
y <= ((not s1) and (not s2) and i0) or (( not s1) and (s2 and i1)) or ( s1 and ( not s2) and i2) or( s1 and s2
and i3);
end Behavioral;
8:1 mux:
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity fdgdfgd is
Port ( d0 : in STD_LOGIC;
d1 : in STD_LOGIC;
d2 : in STD_LOGIC;
d3 : in STD_LOGIC;
d4 : in STD_LOGIC;
d5 : in STD_LOGIC;
d6 : in STD_LOGIC;
d7 : in STD_LOGIC;
s2 : in STD_LOGIC;
s1 : in STD_LOGIC;
s0 : in STD_LOGIC;
e : in STD_LOGIC;
y : inout STD_LOGIC;
y1 : out STD_LOGIC);
end fdgdfgd;
architecture Behavioral of fdgdfgd is
begin
y <= (d0 and (not s2) and (not s1) and (not s0) and (not e)) or (d1 and (not s2) and (not s1) and s0 and
(not e)) or (d2 and (not s2) and s1 and (not s0)and (not e)) or( d3 and(not s2) and s1 and s0 and (not e))
or (d4 and s2 and (not s1) and (not s0 ) and (not e)) or(d5 and s2 and (not s1) and s0 and( not e)) or (d6
and s2 and s1 and (not s0) and (not e)) or(d7 and s2 and s1 and s0 and (not e));
y1 <= (not y);
end Behavioral;
8 to 3 decoder:
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity tyt is
Port ( vecin : in STD_LOGIC_VECTOR (7 downto 0);
vecout : out STD_LOGIC_VECTOR (2 downto 0));
end tyt;
architecture Behavioral of tyt is
begin
with vecin select
vecout <= "001" when "00000010",
"010" when "00000100",
"011" when "00001000",
"100" when "00010000",
"101" when "00100000",
"110" when "01000000",
"111" when "10000000",
"000" when others;
end Behavioral;
T-FLIPFLOP
ibrary IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity t54q is
Port ( t : in STD_LOGIC;
clk : in STD_LOGIC;
reset : in STD_LOGIC;
q : inout STD_LOGIC;
nq : inout STD_LOGIC);
end t54q;
architecture Behavioral of t54q is
begin
process(clk,t)
begin
if(reset='1')then
q<='0';
nq<='1';
else if(clk='1' and clk' event)then
if(t='1')then
q<=nq;
nq<=q;
else
q<=q;
nq<=nq;
end if;
end if;
end if;
end process;
end Behavioral;
8-BIT shift register
ibrary IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity dthd is
Port ( c : in STD_LOGIC;
s1 : in STD_LOGIC;
ce : in STD_LOGIC;
s0 : out STD_LOGIC);
end dthd;
architecture Behavioral of dthd is
signal tmp:std_logic_vector(7 downto 0);
begin
process (c)
begin
if(c' event and c='0')then
if(ce='1')then
for i in 0 to 6 loop
tmp(i+1)<=tmp(i);
end loop;
tmp(0)<=s1;
end if;
end if;
end process;
s0<=tmp(7);
end Behavioral;
shift parallel
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity rtet is
Port ( c : in STD_LOGIC;
s1 : in STD_LOGIC;
left_right : in STD_LOGIC;
po : out STD_LOGIC_vector(7 downto 0));
end rtet;
architecture Behavioral of rtet is
signal tmp:std_logic_vector(7 downto 0);
begin
process(c)
begin
if(c' event and c='1')then
if(left_right='0')then
tmp<=tmp(6 downto 0) & s1;
else
tmp<=s1 & tmp(7 downto 1);
end if;
end if;
end process;
po<=tmp;
end Behavioral;
