Instruction Set Architectures (cont)
• History
• Addressing Modes
• --> Types of Instructions
• --> Encoding Instructions
• --> DLX Instruction Set
CIS429.S00: Lec7- 1
Types of instructions (by operation)
• arithmetic/logical
• data movement
• control
• floating point
• decimal
• string
• graphics
CIS429.S00: Lec7- 2
Top ten 80x86 instructions
Rank Instruction Frequency
1 Load 22%
2 Cond. Branch 20%
3 Compare 16%
4 Store 12%
5 Add 8%
6 And 6%
7 Sub 5%
8 Move R to R 4%
9 Call 1%
10 Return 1%
CIS429.S00: Lec7- 3
Control flow instructions
• conditional branches BEQZ HOME
• unconditional branches or jumps JMP ROPE
• procedure call
• procedure return
Target of the branch can be specified as
• explicit direct JMP ROPE
• explicit indirect JMP (R1)
• displacement JMP 100(R2)
• PC relative JMP 100(PC)
CIS429.S00: Lec7- 4
Use of branches in benchmarks
itle:
T (157-HEN2.12)
dobe
Creator: A Illustrator(T ) 5.0M
his as
Preview: T EPSpicture w not sav w a ed ith
iew IFF )
prev (T or PICT includedinit
his ill
Comment: T EPSpicture w print to apostscript
printer but not to other types of printers
CIS429.S00: Lec7- 5
Displacements used in branches
itle:
T (157-H 2.13)EN
C dobe M
reator: A Illustrator(T ) 5.0
: his as
Preview T EPSpicture w not sav w a ed ith
iew IFF )
prev (T or PICT includedinit
om ent: his ill
C m T EPSpicture w print to apostscript
printer but not to other types of printers
• x axis gives number of bits
• 5-6 bits captures most of the displacements
CIS429.S00: Lec7- 6
Instruction encoding issues
• total size(s) of instructions (halfword, word,
doubleword)
• number of fields, number of operands
• number of bits for each field
Dependent on:
number of registers
types of instructions (operations)
addressing modes
etc.
CIS429.S00: Lec7- 7
Basic varieties of instruction encoding:
variable, fixed, hybrid
itle:
T (157-H N E 2.17)
rea d e
C tor: A ob Illustra M
tor(T ) 5.0
iew his PS re as ot ed ith
Prev : T E pictu w n sav w a
rev IF T clud
p iew(T For PIC ) in edinit
om en his PS re ill rint
C m t: T E pictu w p to ap ostscript
rin t ot pes rinters
p ter bu n to other ty of p
CIS429.S00: Lec7- 8
DLX Architecture
Registers
• 32 32-bit general purpose registers
R0, R1, R2 ….. R31
• 32 32-bit floating points registers
single precision F0, F1, … F31
double precision F0, F2, … F30
(even-odd pairs)
CIS429.S00: Lec7- 9
DLX Architecture (cont)
Data types
• Integer data types
byte (8 bits), halfword (16 bits),
word (32 bits)
• Floating point data types (IEEE 754)
single precision (32 bits)
double precision (64 bits)
CIS429.S00: Lec7- 10
DLX Architecture (cont)
Addressing modes (looks like four, only two)
• Immediate - 16 bits
ADD R1, R2,#3
• Displacement - 16 bits
LW R1,30(R2)
• Registered deferred/indirect - use 0 displacement
LW R1,0(R2)
• Absolute - use R0 as the base, R0 = 0
LW R1,508(R0)
CIS429.S00: Lec7- 11
DLX Instruction Format
T E
itle: (157-H N2.21)
rea d e tra M
C tor: A ob Illus tor(T ) 5.5
iew h PS re as
Prev : T is E pictu w not s edw aav ith
rev IF C ) clu ed
p iew(TF or PI T in d init
om en his PS
C m t: T E pictu w p re ill rint to ap ostscript
rin t ot pes rin
p ter bu n to other ty of p ters
CIS429.S00: Lec7- 12
Deciphering DLX notation
LW R1,30(R2) Regs[R1] <--32 Mem[30 + Regs[R2]]
LH R1,40(R3) Regs[R1] <--32
16
(Mem[40 + Regs[R3]0) ##
Mem[40 + Regs[R3]] ##
Mem[41 + Regs[R3]]
Load halfword Duplicate the sign bit, concatenate
with the byte at Mem[40 + Regs[R3]] and
concatenate with the byte at
Mem[41 + Regs[R3]]. This makes a total of 32 bits.
CIS429.S00: Lec7- 13
Deciphering DLX notation
JAL NAME R31 <-- PC + 4 save return addr
PC <-- NAME
25
((PC + 4) - 2 <= NAME <
25
((PC + 4) + 2 )
Check bounds on value of NAME
since this uses PC relative addressing
Used for subroutine calls:
CIS429.S00: Lec7- 14