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					HSD 2010 21st Annual Workshop on Interconnections within High Speed Digital Systems

                                                   Final Program
                                                   Monday, 03 May 2010
  8:30 AM - 9:00 AM             Opening Remarks
  Workshop Co-Chair             David Bisant, University of Maryland, College Park, MD, USA
                                Jeffrey Kash, IBM Research, Yorktown Heights, NY, USA
                                Z. Rena Huang, Rensselaer Polytechnic Institute, Troy, NY, USA

  8:45 AM - 9:00 AM             Memorial for Samantha Blodgett

  9:00 AM - 11:00 AM
  Session Chair: Valencia Joyner, Tufts University, Medford, MA, USA

TUT1    9:00 AM - 10:00 AM (Tutorial)
Safe, Secure and Sustainable Body Area Networks for Pervasive Healthcare, S. K. S. Gupta, Arizona State University, Tempe, AZ, USA

TUT2    10:00 AM - 11:00 AM (Tutorial)
I/O Requirements and Possibilities for Bio Implantable Computing Interfaces New Interconnect Technologies, K. Mai, Carnegie Mellon
University, Pittsburgh, PA, USA

11:00 AM - 11:15 PM                                          COFFEE BREAK

  11:15 AM - 12:45 PM
  Session Chair: David Bisant, University of Maryland, College Park, MD, USA

MA1    11:15 AM - 11:45 AM (Invited)
Carbon Nanotube Global Interconnects for Emerging Chip Multiprocessors, S. Pasricha, Colorado State University, Fort Collins, CO,
In ultra-deep submicron (UDSM) technologies, the current paradigm of using copper (Cu) interconnects for on-chip global communication is
rapidly becoming a serious performance bottleneck. Carbon nanotubes (CNTs) have recently been proposed as alternative interconnect
fabrics in UDSM technologies. Depending on the direction in which they are rolled, CNTs can behave either as semiconductors or metallic
conductors. Conducting CNTs possess extraordinary properties that make them promising candidates for interconnects in future technologies.
Due to their covalently bonded structure, they are highly resistant to electromigration and other sources of physical breakdown. They can also
support very high thermal conductivity and current densities with very little performance degradation. In this talk, we investigate the
performance of four CNT alternatives that may replace conventional copper (Cu) interconnects at the global interconnect level - (i) single
walled CNTs (SWCNTs), (ii) SWCNT bundles, (iii) multi-walled CNTs (MWCNTs) and (iv) bundles of mixed SWCNTs/MWCNTs. RLC
equivalent circuit models for conventional CNT interconnects will be discussed. These models will then be used as a foundation to explore the
system-level impact of using CNT global interconnects on the overall performance of several multi-core chip multiprocessor (CMP)

MA2    11:45 AM - 12:15 PM (Invited)
Challenges of Wireless Ultra-High Speed Communications, R. Kraemer, IHP Microelectronics, Frankfurt, Germany
In the recent past very fast wireless short range communication systems are in the discussion in different standardization organization such as
IEEE802.15.3c and IEEE802.11ad. These systems should allow speed of more than 1Gb/s. In research systems are being discussed that
should reach 10Gb/s or even slightly more.

With this background the talk will discuss first research in this field of ultra high speed wireless communication. The approaches and
achievements in the 60GHz band will especially be highlighted. Based on our results in 60 GHz the talk will address the question of how to
reach even much higher speed like e.g. 100Gb/s. Several problem areas will be discussed such as frequency band, baseband performance,
coding schemas and MAC protocols. An unconventional approach of moving signal processing tasks from the digital domain into the analog
domain will shortly be discussed.
HSD 2010 21st Annual Workshop on Interconnections within High Speed Digital Systems

MA3     12:15 PM - 12:45 PM (Invited)
Dispersion and Nonlinearity Tailoring using Slotted Waveguides, A. E. Willner, University of Southern California, Los Angeles, CA, USA
On-chip optical waveguides have the potential to play a significant role in high-capacity optical interconnections. Such optical waveguides will
alter the data signals traversing the structure. For example, chromatic dispersion and nonlinearity will affact the data signals. There are
several wideband-data scenarios in which one may want to tailor the specific values and spectral profiles of dispersion and nonlinearity for a
given waveguide, including transmission, signal processing, wavelength conversion, phase and polarization manipulation, and sensing.

We will discuss the recent use of slots in waveguiding structures in order to achieve tailoring of chromatic dispersion and nonlinearity over a
wide spectral range. Slots are constructed of a very thin, lower-refractive-index region and provide interesting waveguiding properties for
entire structure. Slots help to adjust the optical modal overlap with different types of materials. High or low dispersion and nonlinearity values,
coupled with a desired spectral shape over a wide profile, will be presented. Such advances have the potential to enable high data rates for
on-chip tranmission and processing of optical information.

12:45 PM - 1:00 PM              Organization of Teams for Problem Sessions

1:00 PM - 5:00 PM               Lunch & Problem Session I

5:00 PM - 6:30 PM               Welcome Reception – Barranca A

  6:30 PM - 7:15 PM
  Session Chair: Tulin Mangir, TM Associates, Santa Monica, CA, USA

PLE1     6:30 PM - 7:15 PM
The Future of Optical Interconnects, M. W. Haney, Defense Advanced Research Projects Agency, Arlington, VA, USA
As Silicon microprocessor technology continues to scale exponentially in computational performance, chip-level metal interconnect technology
will not be able to keep pace. Consequently, there is a looming communications bottleneck that will prevent high-performance computing
systems from scaling in computational efficiency much beyond the 5 GFLOPS/W level. Optical interconnect technology continues to advance
to higher levels of integration, density, and power efficiency, and may provide the solution to the chip-level communications constraints.
Projections show that integrated optical interconnects will enable computational efficiencies beyond 50 GFLOPS/W in future high-performance
computing systems. In this talk I review the DARPA-sponsored research efforts in integrated photonic interconnects, examine the potential
system impact of optical interconnects in high performance computing systems, and highlight the key technological challenges to be

                              BIO: Dr. Haney is a Program Manager in the Microsystems Technology Office at DARPA, where he is on
                              leave from the Department of Electrical and Computer Engineering at the University of Delaware.             His
                              interests span the application of integrated photonics and optics technologies to computing, signal processing,
                              bio-sensing, and solar power conversion. Before joining the University of Delaware (in 2001), Dr. Haney was
                              with Department of Electrical and Computer Engineering at George Mason University. In 1998 he co-founded
                              Applied Photonics, Inc., an optical engineering company that developed and demonstrated novel concepts in
                              high-density optical interconnects. Previous to joining GMU, he held positions as Director of Photonics
                              Programs at BDM Corporation and Group Leader for Electro-optic Systems at General Dynamics.

Dr. Haney received his BS from the University of Massachusetts in Physics, MS from the University of Illinois in Electrical Engineering, and
Ph.D. from the California Institute of Technology in Electrical Engineering. He is a fellow of the Optical Society of America.
HSD 2010 21st Annual Workshop on Interconnections within High Speed Digital Systems

                                                    Tuesday, 04 May 2010
  8:00 AM - 9:30 AM
  Session Chair: Thomas Koch, Lehigh University, Bethlehem, PA, USA

TuA1     8:00 AM - 8:30 AM (Invited)
High Speed Interfaces in 25Gbps Systems, J. Goergen, Cisco Systems, San Jose, CA, USA
This presentation will discuss the complications designers face for 1) 25Gbps module to chip interface through one connector, and 2) 25Gbps
back plane interface through two connectors. Solutions will be discussed, as well as effectiveness to the system problem set. Included is a
brief overview of the presenter’s view of a telecommunications network system.

TuA3    8:30 AM - 9:00 AM (Invited)
Optical Versus Electrical Interconnects, M. Ritter, IBM Research, Yorktown Heights, NY, USA
System-level switching and computing performance improvements continue to drive exponential growth of interconnect bandwidths. Memory
bus bandwidths are fast approaching 1 Tb/s per bus, and multi-core, multi-chip servers require staggering aggregate chip-to-chip bandwidths
for HPC applications. Simultaneously, internet traffic is accelerating with key switch providers complaining that they needed 100 Gb/s Ethernet
solutions a year ago. In this context of exploding bandwidth needs, the perennial question has been how to partition system communication
among electrical and optical interconnects to achieve competitive system cost-performance metrics. This question can only be addressed by
understanding performance limits of the two technologies. These limitations can be grouped in four broad categories for facility of comparing
optical and electrical interconnect solutions: bandwidth escape, power, reliability, and cost metrics. Having compared these metrics and
undergirding physical limitations for the two technologies, we will show applications where optical interconnects offer superior performance
today. We will close with a discussion of the most probable future insertion points for optical technologies and the issues which must be
tackled in practical implementations.

  9:00 AM - 11:15 AM
  Session Chair: Z. Rena Huang, Rensselaer Polytechnic Institute, Troy, NY, USA

TuB1     9:00 AM - 9:30 AM (Invited)
Communication Technology Road Map II, J. Michel and L.C. Kimerling, Massachusetts Institute of Technology, Cambridge, MA, USA
In 2005, the Communication Technology Roadmap (CTR) I Report correctly noted a shift in technology from classic telephonic
communications infrastructure to data-centric packet-switched communications. The report also forecast the impending integration of photonic
circuit elements within standard electronics circuits and noted the inability of any single commercial entity to resolve these issues
independently. We will present the findings from the most recent report, CTR II. In this report, an even greater change in direction is observed
as Information Technology is reaching limits in its ability to scale to greater capacity and functionality. The emerging barriers to the scaling of
information technology are power efficiency, bandwidth density, and icost. By 2018, the energy utilized by Internet Protocol (IP) traffic is
predicted to exceed 10% of total electrical power generation in developed countries. Parallelism in computational architecture is the accepted
solution to power efficiency of information processing, but bandwidth density bottlenecks are occurring throughout the interconnection
hierarchy from cloud networks to chip-to-chip interconnects. We will discuss the opportunities for optical data transmission in
telecommunication, computation, imaging and learning.

TuB2     9:30 AM - 10:00 AM (Invited)
Optical Interconnection Developments from Campus Networks to the PCB Level, J.D. Ingham, N. Bamiedakis, R. V. Penty and
I. H. White, University of Cambridge, Cambridge, Cambridgeshire, UK
The continuing rise in traffic in local-area networks is motivating the development of new standards for optical datacommunication links. For
example, IEEE 802.3 is currently finalizing the standardization of the initial forms of 40 Gigabit Ethernet and 100 Gigabit Ethernet. In contrast
to previous standards, operation at 40 Gb/s and beyond necessitates multiplexing of several lower-rate channels to achieve high aggregate
line rates at a commercially acceptable cost. However, it would be preferable to employ multiple electrical channels on a single optical
wavelength, thereby avoiding the cost of multiple lasers, photodetectors and the associated optical multiplexing components. This talk will
therefore consider the application of high-spectral-efficiency microwave modulation formats to short-reach links and their implementation by
low-cost and low-power-consumption transversal filters.

Furthermore, optical techniques are increasingly attractive for not only in-building links but also links within computer systems. Polymer-based
components have been developed that can be formed directly on conventional printed circuit board substrates using processes that are
compatible with standard circuit board technology. Therefore, this talk will also consider cost effective optical technologies for these
applications, including siloxane materials developed at Dow Corning. A high-capacity backplane for blade servers with a total aggregate
bandwidth of 1 Tb/s will be described.
HSD 2010 21st Annual Workshop on Interconnections within High Speed Digital Systems

TuB3    10:00 AM - 10:30 AM (Invited)
Board-Level Optical Interconnects for Computing Applications, R. F. Dangel, IBM Research, Rueschlikon, Switzerland
In the near future, electrical interconnect bottlenecks will appear for intra-system links of computing systems, namely for the processor
package IO bandwidth to the board and at the card-to-backplane interface. In consequence, new intra-system interconnect technologies will
be required to continue the performance scaling of computing systems. Generally, optical interconnects as a possible successor technology
offer several advantages compared to established electrical links, such as a higher bandwidth density and power efficiency. However, optics
has merely been applied at the rack to rack-to-rack level, so far. Therefore, the current development of a reliable and mature integrated
technology for board-level optical interconnects is of great importance. This new optical link technology does require the integration of
additional optical and electro-optical components such as lasers, detectors, and optical waveguides. This imposes a cost challenge that can
only be solved by a higher state of integration between electrical and optical technology in terms of the components, subsystem technology
and assembly methods. The prospects and challenges of several optical link technology concepts will be discussed in relation to the massive
interconnect bandwidth requirements that will be required in future computing systems.

10:30 AM - 10:45 AM                                          COFFEE BREAK

TuB4    10:45 AM - 11:15 AM (Invited)
Advanced Card-to-Backplane Optical Interconnects, M. R. Wang, University of Miami, Coral Gables, FL, USA
The CPU speeds of computing systems including personal computers are drastically increasing with on-chip local clock speeds expected to
approach 10 GHz in coming years. Conversely, chip-to-board clock speeds are expected to only gradually increase over the same time frame.
With the interconnection speed of copper lines on a printed circuit board limited to a few gigahertz, alternative techniques for high-speed
backplane design are being extensively researched. Optical Interconnects offer several advantages over conventional copper lines, including
the ability to achieve high data rate signal transmission, large fanout densities, low power consumption, and immunity to radiation and external
electromagnetic interference. Improved packaging, signal tapping, and low-cost solutions are needed for its practical implementation. We
report our experimental results of a flexible ribbon optical interconnect technology for card-to-backplane applications. The interconnection
scheme is based on the exposed core evanescent coupling between a backplane waveguide and a flexible waveguide connected to the card.
It is capable of tapping optical signal power from the backplane waveguide to the card waveguide when the card is plugged into the
backplane. The approach results in the elimination of the 45° waveguide mirror and local waveguide termination obstacles present in other
reported optical interconnect schemes.

  11:15 AM - 1:15 PM
  Session Chair: Peter Van Daele, Ghent University, Ghent, Belgium

TuC1    11:15 AM - 11:45 AM (Invited)
The Future of Silicon Photonics, T. L. Koch, Lehigh University, Bethlehem, PA, USA
Silicon photonics has already demonstrated high performance components and photonic integrated circuits (PICs) incorporating a variety of
filtering, modulation and detection functions. This talk reviews some key advances in worldwide research and examines the potential of silicon
photonics to provide a pathway to deliver the high-functionality, ultra-high density, lower power solutions that will be required in next-
generations communications.

Recent trends suggest that photonic integration may be evolving from a primary role of cost, size and power reduction of existing photonic
solutions and link architectures to one of enabling the continued scaling of electronic functionality. These same trends suggest that the
importance of photonic integration will scale inversely with distance, and also that a key focus of research in the next decade must be the
realization of major improvements in manufacturing platforms providing dramatic improvements in the intimacy of electronics and photonics.

This talk will also illustrate how much headroom still exists relative to fundamental limits of power consumption, suggesting strong
opportunities for innovation in quantum and nanophotonic solutions to deliver improved optical modulation, detection, and possibly generation.
The conclusions point to the unique position that silicon photonics can play in approaching optoelectronics performance limits, and also for
providing an unprecedented intimacy between integrated photonics and electronics in a practical, low-cost manufacturing platform.

TuC2    11:45 AM - 12:15 PM (Invited)
Deeply Scaled Silicon Photonic Devices, S. Assefa, IBM Research, Yorktown Heights, NY, USA
As the number of cores in a microprocessor increases, the communication bandwidth provided by electrical interconnects becomes the
bottleneck which reduces processor performance. Optical interconnects are attractive solutions for achieving communication bandwidth well
beyond terabit-per-second for high-performance multi-core microprocessors. Specifically, deeply scaled silicon nanophotonic devices have
shown great promise as components for on-chip optical links. Silicon provides the opportunity for integrating optical devices at the vicinity of
CMOS circuitry utilizing standard processes. This talk will discuss how leveraging CMOS integration technology has enabled large progress in
demonstration of passive and active silicon nanophotonic devices such as wavelength division multiplexing, modulators, switches and
photodetectors. Specifically, most of the talk will focus on the challenges of integrating Germanium photodetectors and new developments on
avalanche photodetectors.
HSD 2010 21st Annual Workshop on Interconnections within High Speed Digital Systems

TuC3     12:15 PM - 12:45 PM (Invited)
Silicon Photonics to Bring Optics Closer to the Processor, X. Zheng, J. E. Cunningham, Sun Microsystems, San Diego, CA, USA, R. Ho,
J. Lexau, Sun Microsystems, Menlo Park, CA, USA, G. Li, I. Shubin, Y. Luo, H. Thacker, J. Yao, Sun Microsystems, San Diego, CA, F. Liu,
D. Patil, P. Amberg, N. Pinckney, Sun Microsystems, Menlo Park, CA, USA, P. Dong, D. Feng, M. Asghary, Kotura, Inc. Monterey Park, CA,
USA, A. Mekis, T. Pinguet, Luxtera, Inc. Carlsbad, CA, USA, K. Raj and A. Krishnamoorthy, Sun Microsystems, San Diego, CA, USA
Scaling of high performance, many-core, computing systems calls for disruptive solutions to provide ultra energy efficient and high bandwidth
density interconnects with very low cost. Silicon photonics is viewed as a promising solution. For silicon photonics to prevail and penetrate
deeper into computing system interconnection hierarchy, it demands for innovative optical devices, novel circuits, as well as advanced
integration. We report our recent progress in devices and technologies toward sub pJ/bit optical links for inter/intra-chip applications, including
low loss silicon waveguides, optical proximity coupler, and tuneable WDM MUX/DeMUXes. In particular, we present compact reverse biased
silicon ring modulator with high modulation bandwidth of 12GHz, very small capacitance of ~15fF, low voltage swing of 2V, high extinction
ratio (>7dB) and low optical loss (~2dB at on-state). Integrated with low power CMOS driver using low parasitic microsolder bump technique,
we achieved record low power consumption of 320fJ/bit at 5Gbps operation. Using the same integration technique, we further demonstrated
the first hybrid integrated silicon photonic receiver based on Ge waveguide photo detector, with which we accomplished high energy efficiency
of 690fJ/bit, and sensitivity of -18.9dBm at 5Gbps data rate for bit-error-rate of 10 .

TuC4     12:45 PM - 1:15 PM (Invited)
Scaled CMOS Photonics, J. Orcutt, Massachusetts Institute of Technology, Cambridge, MA, USA
A critical feature of silicon photonics has been the ability to monolithically integrate photonics with high-performance electronics. However,
silicon photonics has traditionally relied on a thick Silicon-on-Insulator substrate that dramatically reduces the performance of individual
transistors as well as limits the allowed power density for circuits. Here we present photonic devices fabricated in a scaled CMOS
environment with zero-changes to the process flow. We demonstrate compact wavelength division multiplexing photonics monolithically
integrated with over 1 million transistors per die. This device architecture enables seamless integration of photonics within state-of-the art
electronic foundry processes. Large scale integration of photonics with high-performance electronics enables applications such as massively
parallel processing on individual chips and opens the door to energy efficient communications at the terabit scale.

1:15 PM - 5:00 PM              Lunch & Problem Session II

7:00 PM - 9:00 PM              Student Poster Session & Problem Solutions
HSD 2010 21st Annual Workshop on Interconnections within High Speed Digital Systems

                                                Wednesday, 05 May 2010
  7:00 AM - 8:00 AM              HSD Committee Business Meeting

  8:15 AM - 8:45 AM
  Session Chair: Jeffrey Kash, IBM Research, Yorktown Heights, NY, USA

WA1     8:15 AM - 8:45 AM (Invited)
Zeno-based Optoelectronics, M. S. Goodman, Defense Advanced Research Projects Agency, Arlington, VA, USA
We present an overview of the Zeno-based Optoelectronics (ZOE) program, and discuss the potentially revolutionary impacts to
optoelectronics and optical communications. In the past, all-optical switches have been based on materials with real nonlinear index of
refraction (Kerr effect, etc.). Inspired by the quantum Zeno effect, DARPA is developing a new family of materials leading to optoelectronic
devices with large imaginary nonlinear refractive index in order to implement fast, all-optical switching with ultra-low energy dissipation. The
materials under consideration range from designer organic molecules, to quantum dots, to atomic rubidium. The broad goal of the program is
to overturn the fundamental assumption that high optical loss is contradictory to low energy dissipation in optoelectronics. If successful, the
program will usher in a new era of all-optical devices, based on optically induced loss, that will perform switching, wavelength multiplexing,
memory, and other useful functions at speeds in the 10s of GHz with energy dissipation per operation at the attojoule level.

  8:45 AM - 10:15 AM
  Session Chair: Jeffrey Kash, IBM Research, Yorktown Heights, NY, USA

PLE2    8:45 AM - 9:30 AM
Light Peak Optical Interconnects, J. R. Bautista, Intel Corporation, Santa Clara, CA, USA

PLE3    9:30 AM - 10:15 AM
Interconnects for the Financial Industry, A. Bach, New York Stock Exchange Euronext, New York, NY, USA

10:15 AM - 10:30 AM                                          COFFEE BREAK

  10:30 AM - 1:45 PM
  Session Chair:      Davis Hartman, General Dynamics, Scottsdale, AZ, USA

WB1     10:30 AM - 11:00 AM (Invited)
Large Scale Deployment of Optical Interconnects for High Energy Physics Experiments at CERN, F. Vasey, CERN - European
Organisation for Nuclear Research, Geneve, Switzerland
Radiation tolerant, high speed optoelectronic data transmission links are fundamental building blocks in today’s large
scale high energy physics detectors, as exemplified by the four experiments currently in operation at CERN's Large Hadron Collider (LHC).
This talk will illustrate how exceptionally stringent operational and environmental requirements were met to build one of the world's densest
short distance optical network, now serving science at its high energy frontier.

WB2     11:00 AM - 11:30 AM (Invited)
Communication Networks for Datacenters, M. McLaren, HP Laboratories, Bristol, UK
Datacenter networks of many thousand nodes have become commonplace in the enterprise, cloud computing, and high-performance markets.
For future exascale system, networks capable of connecting over 100,000 nodes will be required. Significant challenges remain to be solved in
building networks of this size with acceptable cost, power, and reliability. Short range optical interconnect technologies targeting backplane
and chip level applications can help reduce interconnect power. At the same time the high bandwidth density of optical interconnects will
enable new switch architectures and topologies. Emerging technologies such as integrated CMOS photonics offer the potential of much more
richly connected data center networks enabling new classes of application.
HSD 2010 21st Annual Workshop on Interconnections within High Speed Digital Systems

WB3     11:30 AM - 12:00 PM (Invited)
Network Interconnects Issues in Large Supercomputing Systems, K. S. Hemmert, Sandia National Laboratories, Albuquerque, NM, USA
As HPC passes petascale and drives toward exascale, the system-wide interconnect will continue to be a critical area of innovation.
Maintaining good system balance (interconnect performance versus node performance) is vital to providing high parallel efficiency. In turn,
high parallel efficiency is required to minimize energy to solution for the largest HPC systems. System power is looming as the single biggest
challenge in reaching the exascale. This talk will focus on the major challenges facing interconnect design as we strive toward exascale and
discuss where photonics can help get us there.

12:00 PM - 1:30 PM            Panel Discussion
Moderator:                    Davis Hartman, General Dynamics, Scottsdate, AZ, USA
Panel Members:                Andrew Bach, New York Stock Exchange Euronext, New York, NY, USA
                              Jerry Bautista, Intel Corporation, Santa Clara, CA, USA

1:30 PM - 1:45 PM             Concluding Remarks