A Radiation Hardened by Design Approach to Solve Single Event Upsets
David W. Jensen, Steven E. Koenck, and Alan C. Tribble
Rockwell Collins, Advanced Technology Center
The occurrence of single event upsets (SEUs) in electronic devices used in critical
space and aviation applications has been recognized over the past 10 years to be a
serious problem that can jeopardize the mission completion. As semiconductor process
geometries continue to shrink, the susceptibility to radiation induced SEUs increases.
Special radiation-hardened semiconductor processes have been developed and shown
to be effective in mitigating radiation effects in electronic devices; however, these
processes are costly and difficult to keep current with state-of-the-art process density.
The Rockwell Collins Advanced Technology Center has developed concepts for a set of
comprehensive SEU mitigation technologies that are suitable for implementation in
standard sub-micron semiconductor processes. These concepts are based on a
combination of SEU prevention and SEU tolerance that make it possible to implement
complex semiconductor devices such as microprocessors that are essentially SEU
immune. A key Rockwell Collins innovation is a novel multiple interconnected
redundant transistor (MIRT) microelectronic logic structure. In this paper we introduce
the MIRT concept and its application to several key microprocessor subsystems.