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```					Chapter 3 Logic Synthesis with Verilog HDL

Fig. 1 Synthesis terminology
Fig. 1 Logic synthesis flow from RTL to gates

Design Constraint
1. Timing constraint—The circuit must meet
certain timing requirements.

2. Area constraint—The area of the final layout
must not exceed a limit.

3. Power—The power dissipation in the circuit
must not exceed a threshold.
6.5 Basic Design Example
Let us discuss synthesis of two examples to understand each step in the synthesis flow.

6.5.1 4-Bit Magnitude Comparator
A magnitude comparator checks if one number is greater than, equal to, or less than another number.
Design a 4_bit magnitude comparator that has the following specifications :
﹡Output A_gt_B is true if A is greater than B
﹡Output A_eq_B is true if A is equal than B
﹡Output A_lt_B is true if A is less than B
Verilog Code

//Module magnitude comparator
module magnitude_comparator(A_gt_B, A_lt_B, A_eq_B,A,B);

//Comparison output
output A_gt_B,A_lt_B,A_eq_B;

//4-bits numbers input
input [3:0] A,B;

assign A_gt_B=(A>B);
assign A_eq_B=(A==B);
assign A_ls_B=(A<B);

endmodule

Technology library
Synthesis Result
The logic synthesis tool produces a final, gate-level description. The schematic for the
gate-level circuit is shown below.

Symbol View

Schematic View
The Synthesized Circuit         Test Stimulus Code

module stimulus;
reg [3:0] A,B;
wire A_gt_B,A_eq_B,A_lt_B;
magnitude_comparator m1(A_gt_B, A_lt_B,
A_eq_B,A,B);
initial
begin
\$monitor("A=%b,B=%b,A_gt_B=%b,A_eq_B=%b,A_lt_B=%b",
A,B,A_gt_B,A_eq_B,A_lt_B);
end

initial
begin
A=4'b1111 ; B=4'b1100;
#10 A=4'b1100 ; B=4'b1100;
#10 A=4'b1000 ; B=4'b1100;
#10 A=4'b0111 ; B=4'b0001;

end
endmodule

Simulation Result
6.5.2 Newspaper Vending Machine
A simple digital circuit is to be designed for the coin acceptor of an electronic newspaper
vending machine.

*Assume that the newspaper cost 15 cents.
*The coin acceptor takes only nickels and dimes.
*Valid combinations including order of coins are one nickel and one dime, three nickels,
or one dime and one nickel. Two dimes are valid, but the acceptor does not return money.

Verilog Code
The Verilog RTL description for finite state machine is shown below.

module vend(coin,clock,reset,newspaper);
input [1:0] coin;
input clock;
input reset;
output newspaper;
wire newspaper;

wire [1:0] NEXT_STATE;
State encoding
reg [1:0] PRES_STATE;

parameter s0=2'b00;
parameter s5=2'b01;
parameter s10=2'b10;
parameter s15=2'b11;

function [2:0] fsm;
input [1:0] fsm_coin;
input [1:0] fsm_PRES_STATE;

reg fsm_newspaper;
reg [1:0] fsm_NEXT_STATE;
begin
case (fsm_PRES_STATE)
Initial state       s0:
begin
if(fsm_coin==2'b10)
Give one dime            begin
fsm_NEXT_STATE=s10;
end
else if(fsm_coin==2'b01)
begin
Give one nickel             fsm_newspaper=1'b0;
end
else
begin
Give no                     fsm_newspaper=1'b0;     money
end
end
s5:
begin
if(fsm_coin==2'b10)
Give one dime            begin
fsm_NEXT_STATE=s15;
end
else if(fsm_coin==2'b01)
Give one nickel          begin
fsm_NEXT_STATE=s10;
end
Give no                  else                       money
fsm_newspaper=1'b0;
fsm_NEXT_STATE=s5;
end
end
s10:
begin
Give one dime            if(fsm_coin==2'b10)
fsm_newspaper=1'b0;
fsm_NEXT_STATE=s15;
end
Give one nickel          else if(fsm_coin==2'b01)
fsm_newspaper=1'b0;
fsm_NEXT_STATE=s15;
end
Give no money            else
begin
fsm_newspaper=1'b0;
end
end
s15:
begin
Give newspaper              fsm_newspaper=1'b1;
fsm_NEXT_STATE=s0;
endcase
fsm={fsm_newspaper,fsm_NEXT_STATE};
end
endfunction
assign
{newspaper,NEXT_STATE}=fsm(coin,PRES_STATE);
always @(posedge clock)
Posedge edge      begin
trigger             if (reset==1'b1)
PRES_STATE=s0;
else
PRES_STATE=NEXT_STATE;
end
endmodule
Synthesis Result

The logic synthesis tool produces gate-level description. The symbol and schematic for
the gate-level circuit are shown below.

Symbol View

Schematic View
Test Stimulus Code

Stimulus is applied to the original RTL description to test all possible combination of
coins. The same stimulus is applied to test the optimized gate-level netlist. Stimulus
applied to both the RTL and gate level netlist is shown below.

module stimulus;
reg clock;
reg [1:0] coin;
reg reset;
wire newspaper;

vend vendy(coin, clock, reset, newspaper);
initial
begin
\$display("\t\tTIME    RESET NEWSPAPER\n");
\$monitor("%d %d %d",\$time,reset,newspaper);
end
initial
begin
clock=0; coin=0;reset=1;
#50 reset=0;
@(negedge clock);
#80 coin=1; #40 coin=0;
Test all       #80 coin=1; #40 coin=0;                                   possible
combination    #80 coin=1; #40 coin=0;
#80 coin=1; #40 coin=0;
#80 coin=2; #40 coin=0;
#80 coin=2; #40 coin=0;
#80 coin=2; #40 coin=0;
#180 coin=2; #40 coin=0;
#180 coin=1; #40 coin=0;
#80 \$finish;
end

Generate       always
periodic       begin                                                     clock
#20 clock=~clock;
end
endmodule
Simulation result
Stimulation result is shown below. Thus, the gate level netlist is verified.
 Basic Coding Guidelines
1. Use simple constructs, basic types, and simple clocking schemes;
2. Use a consistent coding style, consistent naming conventions, and state machines and
processes;
3. Use a regular partitioning scheme, with all module outputs registered and with
modules roughly of the same size;
4. Make the RTL code easy to understand, bu using comments, meaningful names, and
constants or parameters instead of hard-coded number.

 General Naming Conventions
Rule 1: Use lowercase letters for all signal names, variable names, and port names.
Rule 2: Use uppercase letters for names of constants and user-defined types.
Rule 3: Use meaningful names for signals, ports, functions, and parameters
Ex. Do not use ‘ra’ for a RAM address bus. Instead, use ‘ram_addr’.
Rule 4: If your design uses several parameters, use short but descriptive names.
Lengthy parameter names can cause excessively long design unit names, when you
elaborate the design with Design Compiler.
Rule 5: For active low signals, end the signal name with an underscore followed by a
lowercase character (for example, _b or _n).
Signal naming conventions
Convention        Use
*_r               Output of a register (for example, count_r)
*_a               Asynchronous signal (for example, addr_strobe_a)
*_pn              Signal used in the nth phase (for example, enable_p2)
*_nxt             Data before being registered into a register with the same name
*_z               Three-state internal

Rule 6: Using named association rather than positional association
.a (in1), .b (in2), .ci (carry_in), .sum (sum), .co (carry_out) );
 Coding for Synthesis
1. Avoid Latches

Multiplexor
model

Set-latch
model
Ex. Poor coding style: latches inferred because of missing assignments and missing
condition
always @ (d)
begin
case (d)
2’b00: z <= 1’b1;
2’b01: z <= 1’b0;
2’b10: z <= 1’b1; s <= 1’b1;
endcase
end
2. Specify Complete Sensitivity Lists
Poor code (latch inferred)              Good code (3-input AND gate)
always @ (a or b)                       always @ (a or b or c)
y=a&b&c                                 y=a&b&c

3. sequential

```
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