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					Index   WBS        Task Description
1       1          Digital Gammasphere - Phase I



18       1.2       Hardware Development
19         1.2.1   Design interface board between GS and DGS
20         1.2.2   Develop new digitizer firmware to report all discriminators
21         1.2.3   Develop new trigger firmware to handle new digitizer data format
22         1.2.4   Implement multiplicity trigger with new format
23         1.2.5   Integrate GS signals into trigger firmware
26         1.2.8   Design pickoff boards
                     Development
                       draw up initial circuit
                       order parts
                       parts procurement delay
                       verify interconnections with signal conditioner (sanity check)
                       lay out pc board
                       pc board manufacture
                       stuff boards
                       test pc board on bench
27        1.2.9    Design signal conditioning boxes
                     Prototype Development
                       draw up initial circuit
                       order parts
                       parts procurement delay
                       verify interconnections with pickoff board (sanity check)
                       lay out pc board
                       pc board manufacture
                       stuff boards
                       test pc board on bench
                     Chassis Development
                       design box itself- connectors/power supply/mechanics
                       order power supplies
                       external manufacture of chassis
                       mount pc board in box
                   Combined pickoff/conditioner testing
                     Lab Bench Testing
                       Test pickoff/conditioner with pulser/detector in PHY lab using MCA
                       Develop LabWindows software to allow testing of pickoff/conditioner with digitizer
84                     Develop DAQ that allows for slow rate acquisition with a PC
                       Make measurements of energy resolution as a function of flat-top, rise
85                     time with actual GS signals (or other Ge detectors)
                       Verify triggering using multiplicity of 2+ within one digitizer and multiplicity
86                     of 2+ across multiple digitizers
                       Test pickoff/conditioner with pulser/detector in HEP lab using digitizer &
                       LabWindows
                     Testing at Gammasphere
                       Test pickoff/conditioner in GS environment connected to MCA
                       Test pickoff/conditioner in GS environment using DGS DAQ
                   Production cycle of pickoffs and conditioners
                     rework schematic based on prototype testing
                   order parts in production quantities
                   relayout of PC board
                   stuff/assemble production quantities
                   test multiple boxes




31




                  changes in firmware of digitizer/trigger will of necessity create new registers in trigger specific to DGS
                  will need registers in router to mask unconnected channels of digitizers as digitizers now report many
                  changes in firmware will then cause changes to EPICS records and need new GUI interfaces
                  so ANL will have to develop expertise to do this to LBL software once we progress past first steps.


                  Agreed that 20 channels per conditioner is optimal
                  PC boards within conditioners will block vertical airflow; may require plenums in VXI racks




32   1.3          Software Development: run parasitically and stand-alone at GS (no interface card)
                   coerce LBL to give/sell us the vxWorks kernel and their control software
33   1.3.1         install vxWorks kernel from LBL onto MVME5500 processors
                   flash bootroms on MVME5500
                   install and learn to use LBL control software without changes
                   verify stand-alone operation of single digitizer without trigger at GS
32   1.3          Software Development: run parasitically with multiple digitizers & trigger modules but still asynchrono
                   this cannot start until firmware changes in trig/dig allow for multiplicity in DGS
                   verify operation of multiple digitizer DGS multiplicity trigger
                   take and analyze data; verify rates; check spectra….
                  Software Development: run synchronously with multiple digitizers & trigger modules
                   Develop multi-crate monitoring and data logging merged with GS data
42   1.3.10        Develop time-stamp correlation and testing
29       1.2.11    Measure effective energy resolution of DGS relative to GS
30       1.2.12    Measure pileup sensitivity
83   1.5   Test Stand Tasks
87


           Schedule for Digital Gammasphere Phase 1:

           (1) Splitter and Conditioner boards: (PW)
           (a) Design and Construct proto-type boards 9/15/09 - 11/31/09
           (b) Test boards in conjunction with analog GS and digitizer. 12/1/09 - 12/31/09
              - plug splitter board into VXI
           - make connections between spltter board, conditioning box and digitizers
           - check analog GS energy resolution.
           - check energy resolution from digitizer.
           - NOTE: Will need either PC based or VME base daq working for digitizer tests.
           (c) Finalize design of splitter and conditioner boards.
           (d) Construct splitter boards and conditioner boxes for Phase I implentation.
(2) PC basesd acquisition system:
(a) Put together PC base VME system at HEP to interact with digitizer (DONE)
(b) Clone PC based system for Physics
- order MXI-2 VME to PCI card (MPC)
- order PC running windows. (TL)
- assemble and test system. (MPC,JTA)

(3) DAQ Computers

(4) VME based test station:
(a) Order VME crates (HEP) 9/1/09
(b) Obtain MVME5500 9/1/09 (15)
(c) Mount Rack in shack and install processor and digitizer boards.

(5) front end software tasks:
(a) install vxWorks kernel from LBL onto MVME5500 processors
(b) flash bootroms on MVME5500
    (c) evaulate LBL control software and determine what needs to be changed for DGS.
(d) Readout data with one crate system.
(e) Modify software to meet needs of DGS (certainly event builing in MVME5500).
(f) Perform multi-crate readout.

(6) Trigger boards:
(a) Order parts for assembly (HEP) 9/1/09
(b) Assemble boards (HEP).
   (c) Test boards.

(7) Digitizers
   (a) Place order for 16 boards.

(8) GS to DGS VXI board
   (a) Design board
(b) Build board
(c) Test board

(9) Firmware modifications:
(a) Modify firmare for digitizers to treat each channel identically
(b) Modify trigger firmware to treat each channel identically.

(10) DAQ software

(11) Shack Infastructure
              Duration   Start                End         Prior Task Resource List
                                   9/2/2009     3/31/2010




                                               12/31/2009            JTA             actually should be done by about 12/1 if we're lucky; c
                                               12/31/2009                            must be done by this time to allow for tests at GS
                                               12/31/2009




                                  9/17/2009     10/1/2009            PW
                                  9/17/2009     9/30/2009            PW
                                  10/1/2009     11/1/2009
                                  10/1/2009     10/1/2009
                                  10/1/2009    10/20/2009            PW
                                 10/20/2009    11/10/2009            PW
                                 11/10/2009     12/1/2009            PW
                                  12/1/2009     12/5/2009            PW


                                  9/17/2009     10/1/2009            PW
                                  9/17/2009     9/30/2009            PW
                                  10/1/2009     11/1/2009
                                  10/1/2009     10/1/2009
                                  10/1/2009    10/20/2009            PW
                                 10/20/2009    11/10/2009            PW
                                 11/10/2009     12/1/2009            PW
                                  12/1/2009     12/5/2009            PW
                                  9/17/2009    11/30/2009            BN




                               12/5/2009        12/7/2009
tioner with digitizer    Anytime..              12/7/2009            HEP?
                               9/17/2009       11/30/2009            HEP (AK?)

                                  12/7/2009    12/31/2009

                                  12/7/2009    12/31/2009

                                   1/1/2010     1/31/2010            MC/JTA

                                   2/1/2010     2/15/2010                            dependent on GS schedule
                                  2/15/2010     3/15/2010

                                  2/15/2010     2/28/2010
                                2/20/2010       4/1/2010
                                 3/1/2010      3/15/2010
                                3/15/2010      4/30/2010
                                 5/1/2010




  registers in trigger specific to DGS
 izers as digitizers now report many discriminator bits
 d need new GUI interfaces
nce we progress past first steps.



e plenums in VXI racks




o interface card)                                          single digitizer, no trigger, not synchronized to GS in a
                          now                11/15/2009    Essentially same as MSU setup
                                11/15/2009    12/1/2009
                                 12/1/2009   12/10/2009
                                11/15/2009   12/15/2009
                                12/15/2009    1/15/2009    remember, there's the shutdown
 igger modules but still asynchronous to GS                single digitizer, no trigger, not synchronized to GS in a
 licity in DGS
                          depends…           +1 month
                          follows….          +1 month      remember, there's the shutdown
& trigger modules
                          follows async.. +1 month
                          follows….          +1 month      if development of GS-DGs synchronizer card starts ea
                          this will be a few months…..
                          this will be a few months…..
                   1d   3/31/2010   3/31/2010




digitizer tests.
be changed for DGS.

n MVME5500).
ne by about 12/1 if we're lucky; could slip to Mar 2010 without causing trouble.
time to allow for tests at GS
gger, not synchronized to GS in any way.




gger, not synchronized to GS in any way.




-DGs synchronizer card starts early 2010, this could be fall 2010…
50   1.4       Infrastructure                                                     1d
               Re-wire the shack
                 Purchase new Ethernet cables for shack
                   Specify cables that must be replaced
                   Place order
                   Procurement delay
                 Purchase new switches for shack
                 Rip out old cabling in shack
                 Install new cabling
                 Test DG operation with new network cabling
               Rack Modifications
                 Procure new rack
                   Determine whether buy or borrow
                   Procurement delay
                   Make room within the shack
                   Move new rack into shack
                 Procure infrastructure for new rack
                   Purchase fan trays
                   purchase power distribution
                   Obtain rails
               Installation of support equipment into rack
51   1.4.1       Set up rack to hold DG equipment
52   1.4.1.1       Install fans
53   1.4.1.2       mount rails to hold DG subracks
54   1.4.1.3       Install crates into rack
55   1.4.1.4       install power distribution box within rack
56   1.4.1.5   Build computing infrastructure for experiment
                 Identify Linux computers used for DAQ.
                 Purchase 4 identical PC's with keyboards and monitors
                 Install Linux (FEDORA CORE 11)
                 Attach computers to network
                 Setup one system as boot node for MVME5500 processors
                 install LBL software package
                 install VxWorks and EPICS onto desiginated Linux boot node (licence?)

58   1.4.2     Installation of pickoff boards
59   1.4.2.1   Install signal pickoff boards at inputs of VXI cards
60   1.4.2.2   Run cables from pickoff boards to signal conditioner boxes
61   1.4.2.3   Unplug Gammasphere cables and re-plug into pickoff boards
62   1.4.2.4   Verify operation of Gammasphere afterwards, insure no broken cables
63   1.4.2.5   Re-run gain scans to insure no deleterious effects on Gammashpere by pickoff cards
64   1.4.3     Install signal conditioning boxes into racks
65   1.4.3.1   Move VXI crates around in racks to make room for signal conditioning boxes
66   1.4.3.2   Run cables from back of signal conditioners to digitizers
67   1.4.4     Install AC power runs
68   1.4.4.1   Run AC power to DG rack
69   1.4.4.2   Run AC power to router/hub
70   1.4.4.3   Install AC power for test PC/monitor
71   1.4.5     Install Ethernet runs for VME processors
72   1.4.5.1   Procure routers for DG
73   1.4.5.2   Install cables from DG router/hub to main network
74   1.4.5.3   Assign IP addresses
75   1.4.5.4   Run cables from new DG hubs to VME processor boards
76   1.4.6     Install GS-to-DGS interface
77   1.4.6.1   Install interface card into GS master trigger crate
78   1.4.6.2   Verify that presence of card does not mess up Gammasphere operation
79   1.4.6.3   Install cabling from interface card to Master trigger of DGS
80   1.4.6.4   Verify that Digital Gammasphere links onto clock of Gammasphere and that Master Trigger has base fun
81   1.4.6.5   Transfer test data over link from GS to DGS and vice versa (verify link)
82   1.4.6.6   Take test run with Gammasphere and read out counts of triggers from DGS; verify these match.

               measurement of rack space taken up by conditioner boxes?
               how many digitizers does each conditioner service?
               how are conditioner boxes cooled? Does this eat up more rack space?\
               looks like 20 channels (2 digitizers) per conditioner box is optimal
               What about noise between the two digitizers? Grounding?
                3/31/2010    3/31/2010


                             10/1/2009   TL/PHY
                             10/5/2009   TL/PHY
                            10/20/2009
                10/1/2009   10/20/2009   TL/PHY
               10/20/2009   10/31/2009   TL/PHY
                11/1/2009   11/15/2009   TL/PHY
               11/15/2009   11/30/2009   TL/PHY


                             9/30/2009   DS
                10/1/2009   10/15/2009   DS
                10/1/2009   10/15/2009   DS
               10/15/2009   10/15/2009   DS

                10/1/2009   10/15/2009   PW
                10/1/2009   10/15/2009   PW
                10/1/2009   10/15/2009   PW

                                         DS       expect new VME crates between 10/1 and 10/15
               10/15/2009   10/25/2009   DS
               10/15/2009   10/25/2009   DS
               10/15/2009   10/25/2009   DS
               10/15/2009   10/25/2009   DS
                                         DS
                9/10/2009    9/25/2009   TL/MC
                9/25/2009   10/15/2009   MC
               10/15/2009   10/20/2009   TL/SZ
               10/15/2009   10/20/2009   TL/SZ
               10/20/2009   11/15/2009   TL
               10/20/2009   11/15/2009   TL
               10/20/2009   11/15/2009   TL




e by pickoff cards
and that Master Trigger has base functionality

om DGS; verify these match.
2    1.1           Procurement151d           9/2/2009 3/31/2010
3      1.1.1                  2d              VME crates
                   Purchase/test powered9/2/2009 9/3/2009          HEP
4      1.1.2                  151d           9/2/2009
                   Build required trigger modules 3/31/2010        HEP
5        1.1.2.1   Order parts3d             9/2/2009 9/4/2009     HEP
6        1.1.2.2              22d
                   Procurement delay         2/9/2010 ######## 5   HEP
7        1.1.2.3              2w            BEST
                   External assembly @ 11/1/2009 ######## 6        HEP
8        1.1.2.4   Test boards2w           ######## 12/1/2009 7    HEP
9      1.1.3       Purchase1d              3/31/2010 3/31/2010
                               sufficient digitizers
         1.1.3.1      Negotiate price with LBL        9/20/2009    CJL
         1.1.3.2      Place order                     10/1/2009    CJL
         1.1.3.3      Production delay                12/1/2009    LBL
         1.1.3.4      Testing at LBL                   1/1/2010    LBL
10     1.1.4       Buy cabling1d           3/31/2010 3/31/2010
11       1.1.4.1              1d
                   triggers to digitizers 3/31/2010 3/31/2010
12       1.1.4.2              1d           3/31/2010
                   digitizers to signal conditioners 3/31/2010
13       1.1.4.3              1d           experiment
                   signal conditioners to 3/31/2010 3/31/2010
14       1.1.4.4              1d
                   other interface cabling 3/31/2010 3/31/2010
15     1.1.5                  1d           3/31/2010 3/31/2010
                   Procure processor modules
16       1.1.5.1              1d           3/31/2010 3/31/2010
                   procure OS for processor modules
17       1.1.5.2              1d           3/31/2010 3/31/2010
                   procure license for vxWorks on processors

				
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