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					                        Firmware Design Project

1. Create your account at
2. Read various introductory materials on this
   web site. Focus on Virtex-5 family with embedded
   GTP/GTX serializers/deserializers. You can start
   from this book
3. Go to
   and install ISE development system ver 10.1 + SP3 on your PC
4. Use the 25-digit ID key (ask for it) to activate it
4.1. Version 10.1.03 is quite old, but works well. You can try
    later version, but then you will need to get your
    ID directly from Xilinx.
5. Install ModelSim simulation tools, also from Xilinx website
6. Create your own project. Experiment with the RocketIO GTP
    Wizard. Run the full implementation cycle.
    Confirm by simulation.

Here is a specific project for you, as long as you
are familiar with the steps 1-6 above.

We need to build a new optical link for the LHC upgrade.
On a transmitter end there will be 12 Texas Instruments
TLK2501 serializers and one SNAP12 12-channel optical
transmitter. On a receiver end there will be one SNAP12
receiver module and one FPGA (Virtex-5 or -6 or -7)
with embedded deserialzers. They should perform the
basic set of TLK2501 receiver functions. So your goal
would be to build a deserializer core that emulates
the TLK2501 receiver part. The operating frequencies
are 80MHz and 120MHz.

Xilinx discusses this approach, for example, here
but I am not aware of any existing implementations.
So you may actually start with the internet search.
You will need to know how the TLK2501 works in
every detail, see

The other interesting source is this article
This is very technically specific publication.
The first part discusses the problem of high-speed
fixed-latency (this is exactly what we need)
serial links and their implementation in the FPGA.
The second part focuses on a specific implementation
of the HP-1032/34 chips. These devices are, however,
very different from TLK2501.

Testing and debugging in real hardware is the last
important step, after simulation (to be discussed later).

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