PMC PMC BTeV Registers

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					                             PMC BTeV Registers

This document details the PMC XILINX firmware registers implemented for the BTeV
initialization sequence.

   1. PMC Register 0x0200
      The table below lists the offsets used in PMC register 0x0200. This register is
      used to generate the initialization signals for plane B.

            Offset #                                   Signal
             200                                    DIN, CCLK
             204                          DACS signals (CS, SCLK, CDATA)
             208                             Plane B Reset signal (RS)
             210                                       PROG
             218                           ASIC1 signals (SCLK, CDATA)
             220                           ASIC1 signals (SCLK, CDATA)
             21C                           ASIC2 signals (SCLK, CDATA)
             224                           ASIC2 signals (SCLK, CDATA)

   2. PMC Register 0x0300
      The table below lists the offsets used in PMC register 0x0300. This register is
      used to generate the initialization signals for plane A.

            Offset #                                   Signal
             300                                    DIN, CCLK
             304                          DACS signals (CS, SCLK, CDATA)
             308                             Plane B Reset signal (RS)
             310                                       PROG
             318                           ASIC1 signals (SCLK, CDATA)
             320                           ASIC1 signals (SCLK, CDATA)
             31C                           ASIC2 signals (SCLK, CDATA)
             324                           ASIC2 signals (SCLK, CDATA)

   3. Offset Independent Signals
      In this section, I list the signals that are independent from the offset but are
      generated in the firmware. These signals are valid for both planes; however, they
      are plane dependent.

      3.1. Plane A signals

              Signal                                 Source
             DCLK_A             BTeV Data Clock. Generated by the FPIX firmware
                                from FPIX_Readoutclock_A. Clock freq. 16 MHz.
              ACQ_A             BTeV Read Clock. Generated by the FPIX firmware
                                from BCOCLK_A. Clock freq. 8 MHz.
     DRESET_A          Digital reset signal. Generated in the BTeV firmware by
                       implementing a delay element on the Trigger signal
                       from the NIM input.
   FEA_A (0…3)         Front-end address bits. They are generated in the BTeV
                       firmware independently.


3.2. Plane B Signals

       Signal                                    Source
      DCLK_B           BTeV Data Clock. Generated by the FPIX firmware
                       from FPIX_Readoutclock_B. Clock freq. 16 MHz.
       ACQ_B           BTeV Read Clock. Generated by the FPIX firmware
                       from BCOCLK_B. Clock freq. 8 MHz.
     DRESET_B          Digital reset signal. Generated in the BTeV firmware by
                       implementing a delay element on the Trigger signal
                       from the NIM input.
   FEA_B (0…3)         Front-end address bits. They are generated in the BTeV
                       firmware independently.

				
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posted:12/31/2011
language:English
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