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					Principles of Computer Operating Systems

        Course number: CS433
        Who?    Tarun Soni ( tsoni@csusm.edu )

        Where? ACD408

        When? Tuesday and Thursday evenings 4:00-5:15 pm
                Office Hours: Tue:5:15-6:15pm, Sci2-229
                Also, generally available just before and just after class.

        Textbook: Silberschatz, “Modern Operating Systems”

        Web-page: http://public.csusm.edu/tsoni/
                (slides, homework questions, other pointers and information)




CS433-W-1-1                                                               Tarun Soni
                                Grading

• Grade breakdown
     – 5 Surprise Quizzes     (20-30 mins, only 4 high scores count) 40%
     – Mid-term quiz                                        20%
     – Mid-term project submission                          0%
     – Final project submission                             40%

• Homeworks do not need to be turned in. Homeworks will be programming assignments
  and it is your responsibility to make sure you do them and understand what you did.
  Pop-quizzes will be based on hw and can include code-fragments.
• What is cheating?
     – Studying together in groups is encouraged
     – Work must be your own
     – Common examples of cheating: copying an exam question from other material or
        other person...
     – Better off to skip question (small fraction of grade.)
• Written/email request for changes to grades within 1 week
     – average grade will be in the B- or B range; set expectations accordingly


  CS433-W-1-2                                                         Tarun Soni
Course structure


       •Computer system overview.
       •Operating system overview.
       •Process description and control.
       •Threads.
       •Concurrency: mutual exclusion and synchronization.
       •Concurrency: deadlock and starvation.
       •Memory management.
       •Virtual memory.
       •Uniprocessor scheduling.
       •I/O management and disk scheduling.
       •File management.
       •Time permitting: Real time issues, security


CS433-W-1-3                                           Tarun Soni
Approximate Plan


      Dates             Topic Covered                      Suggested
                                                           Reading
      Jan 21,23         Introduction, Overview of OS       Ch. 1-3
      Jan 28, 30. Feb Multi-tasking: Processes, threads,   Ch. 4,5
      4,5             scheduling
      Feb 11, 13, 18,   IPCs, Concurrency                  Ch. 6,7
      20
      Feb 20, 27        Deadlocks, Starvation              Ch. 8
      Mar 4,6,11,13     Memory Management                  Ch. 9, 10
      Mar 13            Mid-Term
      Mar 18,20         File Systems                       Ch. 11
      Mar 25, 27        IO Systems                         Ch. 12, 13
      Apr 8,10,15,17    Networking                         Ch. 14
      Apr 22,24,29      Security, and Protection           Ch. 18
      May 1,5,7         Advanced Topics, Review            Ch. 15,16,17
                        Finals? Surprise quizzes?
CS433-W-1-4                                                             Tarun Soni
The place of an operating system




     • An Operating System makes the
       computing power available to users by
       controlling the hardware




CS433-W-1-5                          Tarun Soni
What hardware are we talking about?


   •    Processor (CPU)
   •    Main Memory (aka real memory, aka primary memory)
          – holds data in code
   •    I/O modules (I/O controllers, I/O channels, I/O processors...)
          – hardware (with registers called I/O ports) that moves data
            between cpu and peripherals like:
             • secondary memory devices (eg: hard disks)
             • keyboard, display...
             • communications equipment
   •    System interconnection (ie: Buses)
          – communication among processors, memory, and I/O modules




CS433-W-1-6                                               Tarun Soni
A typical system




                   Processor/Memory
                   Bus




                   PCI Bus




                   I/O Busses



CS433-W-1-7                  Tarun Soni
Computer Architecture: Execution of instructions


       Instruction
              Fetch


       Instruction
          Decode

                                                     operation
         Operand
              Fetch
                                            a
         Execute                                32   ALU
                                                                        result
                                                                 32
              Result                        b
              Store                             32


              Next
       Instruction
CS433-W-1-8                                                Tarun Soni
  Architecture: Typical Single Cycle Datapath



                                                          Control
                       Ideal
                    Instruction                       Control Signals Conditions
                                        Instruction
                      Memory
                                   Rd Rs        Rt
                                    5  5         5
     Instruction
       Address
                                                      A                          Data
     Next Address




                                        Rw Ra Rb                           32                             Data
                             32                                                 Address
                                                      32                                      Ideal       Out




                                                                     ALU
                                         32 32-bit
                      PC




                                                                                              Data
                                         Registers                              Data         Memory
                                                      B
                                                                                In
                                  Clk                                                  Clk
                                                            32
                    Clk




                                                          Datapath


• Logical vs. Physical Structure
   CS433-W-1-9                                                                               Tarun Soni
  Architecture: Pipelined Datapath

Instruction Fetch   Instruction Decode/         Execute/         Memory Access        Write Back
                      Register Fetch       Address Calculation

                              registers!




   CS433-W-1-10                                                          Tarun Soni
Registers on the CPU


  • Control & Status Registers
     – Generally not available to user programs
     – some used by CPU to control its operation
     – some used by OS to control program execution
  • User-visible Registers
     – available to system (OS) and user programs
     – holds data, addresses, and some condition codes




CS433-W-1-11                                      Tarun Soni
System Registers on the CPU


• Program Counter (PC)
   – Contains the address of the next instruction to be
     fetched
• Instruction Register (IR)
   – Contains the instruction most recently fetched
• Program Status Word (PSW)
   – A register or group of registers containing:
       • condition codes and status info bits
       • Interrupt enable/disable bit
       • Supervisor(OS)/user mode bit




 CS433-W-1-12                                        Tarun Soni
User Registers on the CPU



• Data Registers
   – can be assigned by the user program to perform
     operations on data
• Address Registers
   – contain memory address of data and instructions
   – may contain a portion of an address that is used to
     calculate the complete address
   – Eg: Index, Segment, Stack pointers

• How would you implement address traps ?
       – Check during instruction fetch ?
       – Address limit registers Hi/Lo
       – Who guards the limit registers?


CS433-W-1-13                                        Tarun Soni
I/O Modules




   •     Data to/from system bus are buffered in data register(s)
   •     Status/Control register(s) holds
           – current status information
           – current control information from
   •     I/O logic interact with CPU via control bus



CS433-W-1-14                                                   Tarun Soni
I/O Modules


    I/O is usually much slower than CPU




      •    WRITE transfer control to the
           printer driver (I/O pgm)
      •    I/O pgm prepare I/O module for
           printing (4)
      •    CPU has to WAIT for I/O command
           to complete
      •    Long wait for a printer
      •    I/O pgm finishes in (5) and report
           status of operation




CS433-W-1-15                                    Tarun Soni
Interrupts


•    Computers now permit I/O modules to INTERRUPT the CPU.
•    For this the I/O module just assert an interrupt request line on
     the control bus
•    Then CPU transfers control to an Interrupt Handler Routine
     (normally part of the OS)




CS433-W-1-16                                                  Tarun Soni
Interrupts: Control Flow


•    CPU checks for interrupts after each instruction
•    If no interrupts, then fetch the next instruction for the current
     program
•    If an interrupt is pending, then suspend execution of the current
     program, and execute the interrupt handler


What about pipelined processors ? And superscalar CPUs?
 •    Synchronous interrupts:
        – On receiving an interrupt, finish all instructions in the pipe before
          jumping to the ISR.
        – Less State to save
 •    Asynchronous interrupts:
        – Drop instructions in the pipe and jump immediately to ISR
        – Could mark them undone, or save state of pipe
        – Faster Interrupt switch time, more wasted work ?



CS433-W-1-17                                                           Tarun Soni
Interrupts: Control Flow




                           •   ISRs need to
                                – return control
                                – not block
                                – small and fast




                           •   I/O Devices:
                                – Prioritize ISRs
                                – Mask out
                                  interrupts of
                                  lower priority




CS433-W-1-18                          Tarun Soni
Interrupts: Improve CPU usage




  • I/O pgm prepares the I/O module and
    issues the I/O command (eg: to printer)
  • I/O pgm branches to user pgm
  • User code gets executed during I/O
    operation (eg: printing): no waiting
  • User pgm gets interrupted (x) when I/O
    operation is done and branches to
    interrupt handler to examine status of
    I/O module
  • Execution of user code resumes




CS433-W-1-19                                  Tarun Soni
Classes of Interrupts




•   I/O
      – signals normal completion of operation or error
•   Program Exception
      – overflows
      – try to execute illegal instruction
      – reference outside user’s memory space
•   Timer
      – preempts a pgm to perform another task
•   Hardware failure (eg: memory parity error)




CS433-W-1-20                                              Tarun Soni
Interrupt Handling


                                                Sequential Approach
                                       •   Disable interrupts during an
                                           interrupt
                                       •   Interrupts remain pending until
                                           the processor enables interrupts
                                       •   After interrupt handler routine
                                           completes, the processor checks
                                           for additional interrupts


           Priority Based
•    Higher priority interrupts
     cause lower-priority interrupts
     to wait
•    Causes a lower-priority
     interrupt handler to be
     interrupted

CS433-W-1-21                                                   Tarun Soni
CPU I/O Approaches

•   When a program reads a value on a I/O device it will need to wait
    for the I/O operation to complete
•   Interrupts are mostly effective when a single CPU is shared among
    several concurrently active processes.
•   The CPU can then switch to execute another program when a
    program waits for the result of the read operation.

•   3 techniques are possible for I/O operation
     – Programmed I/O
         • Does not use interrupts: CPU has to wait for completion of
           each I/O operation
     – Interrupt-driven I/O
         • CPU can execute code during I/O operation: it gets
           interrupted when I/O operation is done.
     – Direct Memory Access
         • A block of data is transferred directly from/to memory
           without going through CPU

CS433-W-1-22                                               Tarun Soni
               Polled vs. Interrupt




CS433-W-1-23                          Tarun Soni
DMA


  •    CPU issues request to a DMA module
       (separate module or incorporated into
       I/O module)
  •    DMA module transfers a block of data
       directly to or from memory (without
       going through CPU)
  •    An interrupt is sent when the task is
       complete
  •    The CPU is only involved at the
       beginning and end of the transfer
  •    The CPU is free to perform other tasks
       during data transfer


                Need to worry about Bus accesses and control



 CS433-W-1-24                                                  Tarun Soni
Memory Hierarchy and Caches

• By taking advantage of
  the principle of locality:
  both Spatial and
  Temporal
     – Present the user
       with as much
       memory as is
       available in the
       cheapest
       technology.
     – Provide access at
       the speed offered
       by the fastest
       technology.




   CS433-W-1-25                Tarun Soni
Cache Design


•     Cache size
       – small caches have a significant impact on performance
•     Block size
       – the unit of data exchanged between cache and main memory
       – hit means the information was found in the cache

•    Mapping function
      – determines which cache location the block will occupy
      – Direct Map, Set associative etc.
•    Replacement algorithm
      – determines which block to replace
      – Least-Recently-Used (LRU) algorithm
•    Write policy
      – write a block of cache back to main memory
      – main memory must be current for direct memory access by I/O
        modules and multiple processors
    CS433-W-1-26                                            Tarun Soni
          Virtual Memory

•       is just cacheing, but uses different terminology
         cache                 VM
         block                 page
         cache miss            page fault
         address               virtual address
         index                 physical address (sort of)

•     What happens:
       • if another program in the processor uses the same addresses
          that yours does?
       • If your program uses addresses that don’t exist in the machine?
       • to “holes” in the address space your program uses?
•     Virtual memory provides
       – performance (through the cacheing effect)
       – protection
       – ease of programming/compilation
       – efficient use of memory
    CS433-W-1-27                                             Tarun Soni
              Performance trends



  1000                                                               µProc
                                                                       CPU

                                                                     60%/yr.
                                              “Moore’s Law”
Performance



                                                                     (2X/1.5yr)
          100                                               Processor-Memory
                                                            Performance Gap:
                                                            (grows 50% / year)
                10
                                                                     DRAM
                                                                DRAM
                                                                     9%/yr.
                    1                                                (2X/10 yrs)
                         1980
                         1981
                         1982
                         1983
                         1984
                         1985
                         1986
                         1987
                         1988
                         1989
                         1990
                         1991
                         1992
                         1993
                         1994
                         1995
                         1996
                         1997
                         1998
                         1999
                         2000
                                            Time
                     Note the discrepancy between memory and processor speeds
              CS433-W-1-28                                                Tarun Soni
Architecture: The real thing




CS433-W-1-29                   Tarun Soni
Bios/Boot Loaders


 •    BIOS: The very first “program” that the computer executes
       • Basic Input Output System
 •    Typically resides in “non-volatile” memory
 •    First instruction comes in at “reset-address” of processor
 •    Initial instructions
             • Configure Processor
             • Configure basic memory and at least one I/O path
             • Configure at least one display device (Monitor?)
             • (Sometimes) present user interface for modification of
                boot parameters
             • Jump to “boot device – bootloader”
 •    Generally developed and supplied by the hardware manufacturer,
      since the BOIS needs a large amount of detailed hardware
      information.



CS433-W-1-30                                               Tarun Soni
Bios/Boot Loaders


 •    Bootloader: Initial program that typically comes from the disk.
 •    Typically the second stage of booting a machine.
 •    Usually larger than a BIOS and generally not in Flash.
 •    Could include significant hardware setup and a number of device
      drivers to permit multiple boot-devices or OS images to be
      booted.
 •    Typically resides at “address 0” or equivalent for access from
      BIOS.
 •    Permits configuration by user to define the OS boot parameters
 •    Generally supplied by the OS manufacturer, since the bootloader
      needs to leave the machine in a state expected by the OS.
       • E.g., Caches being turned on or off
       • Memory mapping in specific state
       • Network I/O on or off.
 •    Needs to know about filesystems and executable formats to be
      able to boot OS image.

CS433-W-1-31                                               Tarun Soni
Bios/Boot Loaders


 •    Example BIOS:
       • Open Firmware is an attempt at standardizing BIOS/Firmware
       • Standard PC BIOS- E.g., Phoenix Technologies
       • Linux BIOS

 •    Example Bootloaders:
       • GNU/Grub
       • Linux/LILO
       • Windows/Built-in
       • Redhat/Redboot
       • PowerPC/PPCBug
       • BSD/PMon
       • Almost all have a command line interface

 •    Continuing trade-offs between the need for bootloaders, BIOSes
      and functionality to be stuffed into various layers.
CS433-W-1-32                                               Tarun Soni
Bios/Boot Loaders


 •    Architecture or Redboot




•    BIOS/Bootloaders and OS images usually want to be loaded at
     specific memory locations, which may sometimes lead to clashes.


CS433-W-1-33                                              Tarun Soni
               Operating Systems
                   Overview




CS433-W-1-34                       Tarun Soni
Operating System




• Is a program that controls the execution of application
  programs
   – OS must relinquish control to user programs and regain
      it safely and efficiently
   – Tells the CPU when to execute other pgms
• Is an interface between the user and hardware
• Masks the details of the hardware to application programs
   – Hence OS must deal with hardware details




CS433-W-1-35                                      Tarun Soni
End User view




CS433-W-1-36    Tarun Soni
Services needed in a functional system




    • Facilities for Program creation
       – editors, compilers, linkers, and debuggers
    • Program execution
           – loading in memory, I/O and file initialization
    • Access to I/O and files
       – deals with the specifics of I/O and file formats
    • System access
       – Protection in access to resources and data
       – Resolves conflicts for resource contention




CS433-W-1-37                                                  Tarun Soni
Services needed in a functional system


• Error Detection
                                    • Error Response
   – internal and external
                                       – simply report error to
     hardware errors
                                         the application
       • memory error
                                       – Retry the operation
       • device failure
                                       – Abort the application
   – software errors
       • arithmetic overflow
       • access forbidden           • Fault recovery
         memory locations              – Graceful removal of
   – Inability of OS to grant            service
     request of application            – Replacement with
                                         standby services




CS433-W-1-38                                           Tarun Soni
 Services needed in a functional system

 • Accounting
    – collect statistics on resource usage
    – monitor performance (eg: response time)
    – used for system parameter tuning to improve
      performance
    – useful for anticipating future enhancements
    – used for billing users (on multiuser systems)

Continuous Evolution of Operating Systems

 • Must adapt to hardware upgrades and new types of
   hardware.
 • Must offer new services, eg: internet support
 • The need to change the OS on regular basis place
   requirements on it’s design
    – modular construction with clean interfaces
    – object oriented methodology
 CS433-W-1-39                                         Tarun Soni
History: Earliest Operating Systems: Batch systems

     •     first operating systems (mid-50s)
     •     Components:
               –   End user = programmer
               –   Job submission: tape or punched cards !
               –   Monitor: RAM resident batch control program
               –   Monitor utilities: loaded as needed into RAM
               –   Job Control Language: directives to the monitor
               –   Output: on tape/punched cards/printout


     •     The user submit a job (written on card or tape) to a computer
           operator
     •     The computer operator place a batch of several jobs on a input
           device
     •     A special program, the monitor, manages the execution of each
           program in the batch
     •     Resident monitor is in main memory and available for execution
     •     Monitor utilities are loaded when needed

CS433-W-1-40                                                         Tarun Soni
Batch Processing


    • Monitor reads jobs one at a time
      from the input device
    • Monitor places a job in the user
      program area
    • A monitor instruction branches to
      the start of the user program
    • Execution of user pgm continues
      until:
       – end-of-pgm occurs
       – error occurs
    • Causes the CPU to fetch its next
      instruction from Monitor




CS433-W-1-41                              Tarun Soni
Batch Processing


    • Problems
        1. How does the monitor know about the nature of
           the job (e.g., Fortran versus Assembly) or which
           program to execute?
        2. How does the monitor distinguish
           (a) job from job?
           (b) data from program?
    • Solution
        – Introduce control cards

     • Special cards that tell the resident monitor which
       programs to run
     • Special characters distinguish control cards from
       data or program cards
     • Use “Job Control Language”

CS433-W-1-42                                          Tarun Soni
Job Control Language



     • Is the language to provide
       instructions to the monitor               $JOB
                                                 $FTN
        – what compiler to use
                                                 ...
        – what data to use                       FORTRAN
     • Example of job format: -------------->>   program
     • $FTN loads the compiler and               ...
       transfers control to it                   $LOAD
     • $LOAD loads the object code (in           $RUN
       place of compiler)                        ...
                                                 Data
     • $RUN transfers control to user
                                                 ...
       program
                                                 $END




CS433-W-1-43                                       Tarun Soni
Batch Processing




   • Parts of resident monitor
      – Control card interpreter – responsible for reading
        and carrying out instructions on the cards.
      – Loader – loads systems programs and
        applications programs into memory.
      – Device drivers – know special characteristics and
        properties for each of the system’s I/O devices.
   • Problem: Slow Performance – I/O and CPU could not
     overlap ; card reader very slow.
   • Solution: Off-line operation – speed up computation
     by loading jobs into memory from tapes and card
     reading and line printing done off-line.



CS433-W-1-44                                         Tarun Soni
Spooling




   • Overlap I/O of one job with computation of another
     job. While executing one job, the OS.

      – Reads next job from card reader into a storage
         area on the disk (job queue).
      – Outputs printout of previous job from disk to
         printer.
   • Job pool – data structure that allows the OS to select
     which job to run next in order to increase CPU
     utilization.

   SPOOL: Simultaneous Peripheral Operations On Line



CS433-W-1-45                                          Tarun Soni
Batch OS

• Relies on available hardware to effectively alternate
  execution from various parts of memory
Need some things from the hardware
• Memory protection
   – do not allow the memory area containing the monitor to
     be altered by user programs
• Timer
   – prevents a job from monopolizing the system
   – an interrupt occurs when time expires
•    Privileged instructions
      – can be executed only by the monitor
      – an interrupt occurs if a program tries these instructions
•    Interrupts
      – provides flexibility for relinquishing control to and regaining
         control from user programs
 CS433-W-1-46                                                  Tarun Soni
Batch OS




•    Permits only one user program at a time
•    Wasted CPU cycles during I/O
•    Cumbersome job input and output process for development
•    Today: end user is not really the programmer



• However, first “multi-context” OS with the monitor and user
  contexts
• Simple step to include saving state and running more than
  one jobs at a time as hardware became faster and more
  amenable



CS433-W-1-47                                       Tarun Soni
Multi-programmed batch OS
                  Multiprogrammed Batch Systems
    • If memory can hold several programs, then CPU can switch
      to another one whenever a program is awaiting for an I/O to
      complete
    • This is multitasking (multiprogramming)




CS433-W-1-48                                         Tarun Soni
Time Shared Systems


• Batch multiprogramming does not support interaction with
  users
• TSS extends multiprogramming to handle multiple
  interactive jobs
• Processor’s time is shared among multiple users
• Multiple users simultaneously access the system through
  terminals

• Because of slow human reaction time, a typical user needs 2
  sec of processing time per minute
• Then (about) 30 users should be able to share the same
  system without noticeable delay in the computer reaction
  time
• The file system must be protected (multiple users…)


CS433-W-1-49                                       Tarun Soni
Multi-programmed batch OS




• Hardware support:
   – I/O interrupts and (possibly) DMA
       • in order to execute instructions while I/O device is
         busy
   – Memory management
       • several ready-to-run jobs must be kept in memory
   – Memory protection (data and programs)
• Software support from the OS:
   – Scheduling (which program is to be run next)
   – To manage resource contention




CS433-W-1-50                                          Tarun Soni
Hardware Support



    • Sharing system resources requires operating system
      to ensure that an incorrect program cannot cause
      other programs to execute incorrectly.
    • Provide hardware support to differentiate between at
      least two modes of operations.
       1. User mode – execution done on behalf of a user.
       2. Monitor mode (also supervisor mode or system
          mode) – execution done on behalf of operating
          system.




CS433-W-1-51                                        Tarun Soni
Hardware Support: Dual Mode operation



    • Mode bit added to computer hardware to indicate the
      current mode: monitor (0) or user (1).
    • When an interrupt or fault occurs hardware switches
      to monitor mode.
                     Interrupt/fault


               monitor                   user
                         set user mode




    • Privileged instructions can be issued only in monitor
      mode.

CS433-W-1-52                                         Tarun Soni
Protection


   I/O
   • All I/O instructions are privileged instructions.
   • Must ensure that a user program could never gain
       control of the computer in monitor mode (I.e., a user
       program that, as part of its execution, stores a new
       address in the interrupt vector).
   Memory
   • Must provide memory protection at least for the
       interrupt vector and the interrupt service routines.
   • In order to have memory protection, add two
       registers that determine the range of legal addresses
       a program may access:
        – base register – holds the smallest legal physical
           memory address.
        – Limit register – contains the size of the range
   • Memory outside the defined range is protected.
CS433-W-1-53                                           Tarun Soni
Hardware for addressing traps




  • When executing in monitor mode, the operating
    system has unrestricted access to both monitor and
    user’s memory.
  • The load instructions for the base and limit registers
    are privileged instructions.
CS433-W-1-54                                          Tarun Soni
Hardware for CPU protection


    So how do you prevent infinite loops ?

    • Timer – interrupts computer after specified period to
      ensure operating system maintains control.
       – Timer is decremented every clock tick.
       – When timer reaches the value 0, an interrupt
         occurs.
    • Timer commonly used to implement time sharing.
    • Time also used to compute the current time.
    • Load-timer is a privileged instruction.




CS433-W-1-55                                          Tarun Soni
System archiecture


   how does the user program perform I/O?



   • System call – the method used by a process to
     request action by the operating system.
      – Usually takes the form of a trap to a specific
        location in the interrupt vector.
      – Control passes through the interrupt vector to a
        service routine in the OS, and the mode bit is set
        to monitor mode.
      – The monitor verifies that the parameters are
        correct and legal, executes the request, and
        returns control to the instruction following the
        system call.


CS433-W-1-56                                          Tarun Soni
Evolution of major concepts




CS433-W-1-57                  Tarun Soni
Parallel Systems



     • Multiprocessor systems with more than one CPU in
       close communication.
     • Tightly coupled system – processors share memory
       and a clock; communication usually takes place
       through the shared memory.
     • Advantages of parallel system:
        – Increased throughput
        – Economical
        – Increased reliability
            • graceful degradation
            • fail-soft systems




CS433-W-1-58                                      Tarun Soni
Parallel Systems




     • Symmetric multiprocessing (SMP)
        – Each processor runs an identical copy of the
          operating system.
        – Many processes can run at once without
          performance deterioration.
        – Most modern operating systems support SMP
     • Asymmetric multiprocessing
        – Each processor is assigned a specific task; master
          processor schedules and allocates work to slave
          processors.
        – More common in extremely large systems



CS433-W-1-59                                         Tarun Soni
Real-time systems



     • Often used as a control device in a dedicated
       application such as controlling scientific
       experiments, medical imaging systems, industrial
       control systems, and some display systems.
     • Well-defined fixed-time constraints.
     • Hard real-time system.
        – Secondary storage limited or absent, data stored
          in short-term memory, or read-only memory (ROM)
        – Conflicts with time-sharing systems, not
          supported by general-purpose operating systems.
     • Soft real-time system
        – Limited utility in industrial control or robotics
        – Useful in applications (multimedia, virtual reality)
          requiring advanced operating-system features.

CS433-W-1-60                                           Tarun Soni
Distributed systems




     • Distribute the computation among several physical
       processors.
     • Loosely coupled system – each processor has its
       own local memory; processors communicate with
       one another through various communications lines,
       such as high-speed buses or telephone lines.
     • Advantages of distributed systems.
        – Resources Sharing
        – Computation speed up – load sharing
        – Reliability
        – Communications



CS433-W-1-61                                       Tarun Soni
Distributed systems




     • Network Operating System
        – provides file sharing
        – provides communication scheme
        – runs independently from other computers on the
          network
     • Distributed Operating System
        – less autonomy between computers
        – gives the impression there is a single operating
          system controlling the network.




CS433-W-1-62                                         Tarun Soni

				
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