FPGA signal processing for radarsonar applications

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					DefenseElectronics

FPGA signal processing
for radar/sonar applications
FPGAs have been used in radar and sonar systems for some time—mostly
in support functions. However, as FPGAs get more sophisticated, performing
and integrating more DSP functions in FPGAs is becoming the standard. As
a result, radar- and sonar-system designers can rely on logic providers for
optimized processing solutions, rather than on proprietary math functions.
By Ryan Kenny

R     adar and sonar applications are signal-
      processing intensive and heavily rely on
the efficient implementation of such digital
                                                          Changing requirements in radar
                                                          applications
                                                             Modern military radar systems have
                                                                                                           lows designers to make early decisions on
                                                                                                           actionable intelligence and to meta-tag sensor
                                                                                                           data earlier for more efficient analysis. These
signal-processing (DSP) algorithms as fil-                 evolving requirements, both in how the           and other emerging techniques will allow for
tering, transforms and modulation. In past                systems are designed and how the end user        the creation of better radar or sonar systems,
systems, conventional digital signal proces-              uses the data. This results in some of the       but each requires additional signal-process-
sors were used to perform many of these al-               same design changes in electronic systems        ing resources.
gorithms. However, field-programmable gate                 affecting both the military and commer-             One of these resources is the emerging
arrays (FPGAs) deliver an order of magnitude              cial design communities. That is, the need       class of high-performance FPGAs. One of
higher performance than traditional DSPs.                 for smaller, energy-efficient systems with        the primary differences in the past between
A key reason is that an FPGA can side step the            high processing-power requirements. This         FPGAs and application-specific integrated
classic Von Neumann architecture’s instruc-               makes low power consumption a key driver         circuits (ASICs) has been greater complexity
tion—fetch, load/store bottleneck—found                   in most designs.                                 in the latter class of devices. However, with
in most DSPs. Another reason is the FPGA’s                   With warfare having become more urban,        the 65 nm generation of FPGAs, and 45 nm
lower power consumption.                                  ground clutter and background noise take         devices on the horizon, FPGAs in sensor
   When approaching the problem of imple-                 on additional significance for the radar opera-   systems have become nearly as complex as
menting signal-processing functions within an             tor, thus demanding more processing power        ASICs. This complexity comes from rapidly
FPGA, designers have developed the mindset                and better algorithms. Overlaying data from      increasing logic density, as well as from the
that these functions must be optimally coded              multiple sensors and known terrain features      integration of the many different processing
from the ground up for their application or               is one approach to increasing resolution, but    functions now integrated into one device.
significantly modified. However, silicon-                 this too has impacts on system-processing
optimized, high-precision math functions                  requirements and user-decision models.           Modern approaches to radar DSP
are being developed for specific applications                 High-speed digital systems make new              As FPGAs increase in density and per-
as part of the programmable logic product                 digital beam-forming technologies pos-           formance capability, more signal-processing
offering of many vendors, including Altera,               sible, increasing the number of beams and        functions can be incorporated and migrated to
making complex systems easier to manage                   nulls available for warfighting and surveil-      the front end containing the exciter/receiver
and lower risk.                                           lance missions. More digital logic also al-      of the radar (or sonar) system. This may in-
                                                                                                           clude waveform generation, filtering, matrix-
                                                                                                           inverse operations, and signal correlation.
                                                                          ���������������                     A representative multi-element radar ele-
            ���                 ����
                            ������������������������
                                 ������                                                                    ment is shown in Figure 1, with multiple sig-
                                                       ���������                                           nal-processing and beam-forming elements
                                ����                                          ��������                     represented in a single logic element. The
                                                                              ��������       ��������
          ��������              ����                                                         ����
                                                                                                           design of this single FPGA quickly becomes
                                                                              �������
                                                                              ���������      ������        complex, particularly if the beam-forming
                                                                                                           algorithms allow for multiple beams and nulls
                                                            ����                                           in the active array.
                      ��������                              ����
                      ��������                              �������
                                                                                                           An all-FPGA design
                                                                              ��������
                                                                              ��������                     for signal processing
                                                                              �������                         Fitting multiple DSP functions into a sin-
            ���                 ������                 ���������              ���������                    gle FPGA has many integration challenges,
                                                                                                           but also offers significant advantages to the
                                ����                                                                       designer in performance and flexibility.
          ��������              ����                                          ����������                      The primary reasons for integrating DSP
                                                                                                           functions into a single FPGA are system-
                                                                                                           level reductions in size, weight and power.
Figure 1. Block diagram of a typical prototype radar system.                                               For example, eliminating the transfer path-


Supplement to Penton Media                                              www.rfdesign.com                                                                    9
     ways between separate FPGAs and DSPs                                                            ����




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     significantly reduces power consumption
     and, therefore, heat. This, in turn, reduces         ���                                                                                                                                                                      ��
     the system-cooling burden of the design.                                                                                       �����    �       �
     Recent releases of design and place-and-
     route software, such as Altera’s Quartus II
     design suite, have advanced power-awareness                                                     ����
     features that significantly reduce dynamic
     power use of the FPGA. These options can




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     be important to the designer; the benchmark
     of device logic density among competitive          ������������������������������������������
     FPGA providers is beginning to give way
                                                       Figure 2. The DSP math block in a Stratix III FPGA can be divided into 9 x 9 bits, or combined into
     to functionality-per-watt metrics, due to the     36 x 36 bits.
     sensitivity of power and cooling requirements
     in emerging systems.
        Performance is also a key driver as FPGA-
     pipelined signal processing has become more                                                             ���
     reliable and faster than traditional processing
     technologies. In applications where perfor-                                             ����������
     mance is the driving parameter, efficiency can
     be sacrificed for application speed, where a                                                            ���������
     memory-intensive, massively parallel float-
     ing-point math operation is desired. Alter-                 ��������                                   ���������                        ����
     natively, highly iterative DSP calculations                                                                                            ����������                           ���
                                                                 ����������                                                                                                                                          ���������
     can be implemented for applications where                                                                                                                                                                       ��������
     moderate performance is allowable, but                                                                                                                                                                          ����




                                                                                                                                                         ����
     where logic-element usage is limited.                                                                  ���������
        This logically leads to the advantage of
     flexibility. The designer has the flexibility to
     decide between high-speed performance and
     the number of logic elements in every DSP
                                                       Figure 3. Block diagram of a typical architechture for integrated polyphase filtering and
     operation, whereas calculation bandwidths         downconversion.
     and iterations would be more difficult and
     costly to modify in a dedicated DSP device.       ing-point arithmetic, FPGAs have significant                                     nificant advantages to the system in signal
     In addition, consolidating DSP functions          flexibility advantages if the design team takes                                  accuracy and speed.
     within an FPGA allows for post-design             advantage of a strong architecture-based                                           The closer to the RF front end (or the
     system changes in the signal-processing           design approach. Large floating-point math                                       acoustical transceiver front end in sonar
     architecture, whereas using separate DSPs         operations can be performed in standard logic                                   systems) that signals can be digitized, the
     locks the designer into a fixed set of chip        cells (the least efficient option), in dedicated                                 fewer the analog-signal vulnerabilities that
     interfaces once the board is designed. FPGA       reduced-instruction-set-computer (RISC)                                         are introduced to the system. This includes
     designers can alternately switch between          embedded processors (the most flexible                                          high-order mixing products, error-vector-
     9-bit, 18-bit or 36-bit or 18-bit complex         option), or in dedicated floating-point multi-                                   magnitude (EVM) impairments due to phase/
     math functions without changing the system        plier logic (the most efficient option).                                         magnitude imbalance, carrier feed-through,
     hardware.                                            FPGA providers and third-party develop-                                      harmonics, and sideband noise.
        Additional flexibility can be designed into     ers offer efficient and accurate floating-point                                      More important than signal integrity,
     the system when the designer uses fast-embed-     operators, Fourier-transform tools and filter                                    however, is the design flexibility that the
     ded processors for the execution or routing       compilers to FPGA designers as intellectual                                     digital domain allows the radar-system
     of complex floating-point operations. These        property (IP). Engineers should conduct their                                   designer. Dynamic filtering and conditional
     functions are useful for radar applications.      own research on the current availability of                                     signal-processing algorithms significantly
                                                       advanced DSP functions, but a great deal                                        improve performance, as well as reduce
     FPGA DSP functions in radar/                      of preliminary information can be obtained                                      implementation losses and the time required
     sonar applications                                through the technical representatives of pro-                                   for the design cycle. While these advantages
        Several DSP functions are needed for radar     grammable logic device (PLD) vendors.                                           involve trade offs between power consump-
     or sonar processing near the receiver element.                                                                                    tion and digital bandwidth, modern FPGAs
     Each function should be closely examined          Digital up/digital down signal                                                  provide designers much greater flexibility
     to determine whether the application will         conversion                                                                      in mitigating power consumption, including
     show substantial speed and performance               The upconversion and downconversion                                          the support of selectable core voltages, or
     improvements through implementation in            of high-frequency signals are experiencing                                      critical-path power analyses.
     an FPGA. In some cases, these operations          a dual migration, both into the digital do-                                        The greater the numbers of on-chip
     can be efficiently implemented using an            main, and into the same monolithic device                                       resources available in FPGAs, the more de-
     FPGA embedded processor, even for highly          (either the ASIC or FPGA) that performs                                         signers are enabled to incorporate polyphase
     complex and adaptive operations.                  the baseband processing. This push to-                                          filtering and downconversion in the digital
        When a radar or sonar application calls for    ward more digital, software-radio-style                                         domain, as reflected in Figure 3. Multiple
     these operations to be performed with float-       signal-processing techniques provides sig-                                      onboard or external numerically controlled


10                                                                      www.rfdesign.com                                                                                                                   December 2007
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                                       �             ������                                                     automatically generate numerical coefficients
                       ������        ��
                                                 �
                                                                                ������                          having floating-point accuracy.
     ���                              ��
                                                                                         ����      ���             Because radar, sonar and digital-com-
                                                     ������
                       ������
                                                ��                                                              munication system designers must focus on
                                      ��                                                                        the complications of multi-element beam-
                                                     ������
                       ������        ��
                                           ��
                                                                                                                forming and waveform generation—not FFT
                                                                                                                design—programmable logic vendors such as
                                                                                                                Altera have internal tools and generators for
                                                                             ���                                conducting large, difficult element transfor-
                                                                                                                mations. This includes reference designs and
                                                                                                                core IP wizards for standard and non-standard
Figure 4. Block diagram for an FPGA-based FFT implementation.
                                                                                                                designs, as well as FFT co-processors, which
oscillators (NCOs) can allow very high                        cations required by the system. Therefore, in     are important design aids in the program-
phase discrimination with high-capacity                       larger arrays, there are more trade-off options   mable logic offering.
FPGA devices. This application is useful                      between the speed of the system and the num-
for prototyping, research and development,                    ber of logic elements required by the system      Design flow
where designers can incorporate and test                      (both of which increase as the parallelization       DSP logic designs are commonly executed
multiple phase resolutions without significant                 of the architecture increases).                   from an initial model in simulation languages,
hardware investments by using hardware-in-                       Implementing this function using a com-        such as Matlab or Simulink. These models are
the-loop test methodologies.                                  bination of a DSP and a group of internal         the most common, but not the only sources
                                                              memory blocks is the most likely design path      for designers to access optimized DSP IP
Algorithmic functions                                         for radar-system designers. As these opera-       offered through FPGA providers. The link-
   Examples of algorithmic math functions in                  tions are often tailored to the adaptive-array    age between modeling and hardware imple-
radar systems include recursive least-square                  algorithms of the radar system, they are likely   mentation is important, not only for design
and square-root operations. Many designers                    to be custom designed in VHDL. However,           simplicity, but for simulation and verification
have implemented these functions in C-based                   reference designs that are optimized for the      against the model.
processors (in fixed-decimal and floating-                      place-and-route capabilities of an FPGA              As the design density for FPGA-based
point operations), or with proprietary FPGA                   device can be offered or designed-to-order        sensor systems increase, full system model-
VHDL operations. The current generation of                    from the FPGA manufacturer, if required for       ing and simulation will become more time
FPGA devices include embedded processor                       the radar or sonar system.                        consuming. Compile, simulation, and place-
and logic-cell resources to efficiently imple-                                                                   and-route times will increasingly become
ment these processes; future generations will                 Fast-Fourier transforms                           discriminators when selecting FPGA and
also have these capabilities. Additionally,                      The bandwidths of many systems, includ-        design-software vendors. Furthermore, multi-
IP cores and reference designs are becom-                     ing radar/sonar and test/measurement sys-         processor and distributed processing options
ing available to transition anywhere from                     tems, are beginning to exceed the capabilities    for design software will be necessary to keep
dozens to hundreds of these operations into                   of dedicated DSPs. Implementing fast-Fourier      up with design complexity.
a single FPGA.                                                transforms (FFTs) and their inverses in FPGA         To cope with these trends, and to achieve
   Tools are available to translate processor-                logic has advantages in prototyping and scal-     the greatest signal-processing performance
based algorithms from C code to hardware                      ability, and offers design flexibility between     in their sonar or radar systems, designers
languages, such as very high-level descriptive                a system’s speed and the number of required       are encouraged to consider options beyond
language (VHDL). These tools can be used                      logic elements. For example, massively            their own VHDL modules or other inter-
to optimize certain logic functions from a                    parallel implementations can be designed          nally developed IP. Specifically, they should
standard main processor into an FPGA co-                      and distributed among the logic elements of       consider working with programmable logic
processor operating in parallel with the main                 a single or multiple FPGAs. However, while        manufacturers to develop tailored DSP cores,
processor, or to move entire operations from                  these implementations can significantly           or find ways to improve and optimize their
the main processor to the FPGA hardware.                      reduce latency, they impose the penalty of a      designs through advanced place-and-route
This provides an additional dimension of                      greater number of logic elements.                 methods available for FPGA design tools.
flexibility to the radar- or sonar-architecture                   In fact, the primary flexibility advantage      This is because the advanced capabilities of
designer’s toolkit.                                           of an FPGA for FFTs is the ability to select      integrated circuits enabled by increasingly
                                                              the optimal balance between these two pa-         sophisticated fabrication technologies can-
Complex matrix inversion                                      rameters in the initial design. This is fortu-    not be fully harnessed without flexible and
   Matrix inversion is an important element                   nate, because the implementation of large or      effective design techniques.
of adaptive-array designs and standard spa-                   complex FFTs should be the primary factor
tial-transceiver-array processing (STAP).                     in any design, and the advantages of an FFT               ABOUT THE AUTHOR
These operations are commonly performed in                    implementation in an FPGA (Figure 4) are
fixed hardware elements, though efficiently                     apparent. However, creating code or modify-       Ryan Kenny is the technical marketing man-
implemented embedded processing has been                      ing existing code from previous designs can       ager for military and aerospace products at
demonstrated in some radar/sonar develop-                     be cumbersome when testing and verifying          Altera. He is responsible for creating FPGA-
ment programs.                                                code units. Therefore, what is needed is a        based technical solutions for military-data
   The logic-element size and potential paral-                comprehensive suite of FFT design tools           and signal-processing applications. He joined
lelism of a matrix inversion engine depends                   that allows a nearly infinitely scalable FFT       Altera in 2007, and has more than 10 years of
on the size of the array used in the radar                    design. These tools are available and they        experience in space and defense electronics in
system. As the size of the array is increased,                allow scripted logic distribution among mul-      the U.S. Air Force and at Lockheed Martin.
so does the number of floating-point multipli-                 tiple FPGAs where necessary. They can also


Supplement to Penton Media                                                  www.rfdesign.com                                                                     11
12   www.rfdesign.com   December 2007

				
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