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					                                                        SVT




      The CDF Silicon Vertex Trigger
                  Beauty 2005
                    Mauro Dell’Orso
             Istituto Nazionale di Fisica Nucleare
                           Pisa – Italy




June 2005               Mauro Dell'Orso - Beauty 2005   1
                          Outline                        SVT


• CDF and the Silicon Vertex Trigger (SVT)

• Motivations

• Design

• Performance

• Upgrade

• Conclusions




June 2005                Mauro Dell'Orso - Beauty 2005   2
                                CDF r-z view                       SVT




                        COT
                        TRACKING
                        CHAMBER




LAYER 00



               SVX II                          INTERMEDIATE
               SILICON VERTEX                  SILICON LAYERS
               5 LAYERS
   June 2005                       Mauro Dell'Orso - Beauty 2005   3
                   SVX II                                         SVT


                                               10.6 cm



            f-sector



                                                         2.5 cm
    90 cm




June 2005      Mauro Dell'Orso - Beauty 2005                      4
                            Why and how?                                                   SVT

• Trigger on B hadronic decays
        – B physics studies, eg. CP violation in B decays, Bs mixing
        – new particle searches, eg. Higgs, Supersymmetry


• A b-trigger is particularly important at hadron colliders
        – large B production cross section for B physics
        – high energy available to produce new particles decaying to b quarks
        – overwhelming QCD background O(103)
            • need to improve S/B at trigger level

• Detect large impact parameter tracks from B decays using the
  fact that (B)1.5 ps


                  Technical challenge!
                                                                                  secondary vertex
                                                                 primary vertex
June 2005                        Mauro Dell'Orso - Beauty 2005                             5
             Exploit lifetime to select b,c                                 SVT




             Proton-antiproton                             B decay vertex
             collision point

                                     Impact parameter (d)


Transverse view                                            ~ 1 mm

 June 2005                 Mauro Dell'Orso - Beauty 2005                    6
            SVT: Input & Output                                           SVT


                                                 Inputs:
                                                 –  L1 tracks from XFT (f, pT)
                                                 –  digitized pulse heights
                                                    from SVX II

                                                 Functionalities:
                                                 –  hit cluster finding
                                                 –  pattern recognition
                                                 –  track fitting

                                                 Outputs:
                                                 –  reconstructed tracks
                                                          (d, f, pT)




June 2005        Mauro Dell'Orso - Beauty 2005                            7
                                        SVT Design Constraints                                    SVT
            Detector
            Raw Data

                          7.6 MHz Crossing rate



Level 1
pipeline:
                       Level 1
                       Trigger
                                                                           •45 kHz input rate
                                  Level 1
42 clock
cycles
                                  •7.6 MHz Synchromous Pipeline
                                  •5.5 s Latency
                                                                           •O(103) SVX strips/event
                                  •45 kHz accept rate

                                 SVX read out after L1
                                                                           •2-D low-res COT tracks
                  L1
                 Accept
Level 2
buffer: 4
                       Level 2
                       Trigger             SVT here                        •Latency O(10) sec
events

                                                                           •No Dead Time
                                  Level 2
                  L2              • Asynchromous 2 Stage Pipeline
                 Accept           •20 s Latency
 DAQ
 buffers
                                  •300 Hz accept rate
                                                                           •Resolution offline
                             At L3 it is too late
           L3 Farm



Mass Storage (50~100 Hz)

     June 2005                                             Mauro Dell'Orso - Beauty 2005          8
                   Tracking in 2 steps                                    SVT


1. Find low resolution
   track candidates                                       Roads
   called “roads”.
   Solve most of the
   pattern recognition
                                                         Super Bin (SB)


2. Then fit tracks
   inside roads.
   Thanks to 1st step
   it is much easier


   June 2005             Mauro Dell'Orso - Beauty 2005                    9
                     Pattern matching                      SVT




        The Event

                    The Pattern
                       Bank


                      ...

June 2005                 Mauro Dell'Orso - Beauty 2005   10
                   AM: Associative Memory                                                                    SVT


                            AM = BINGO PLAYERS
                                                                                                PATTERN 5
                                                                                    PATTERN 4
                                        PATTERN 2
                            PATTERN 1                 PATTERN 3         PATTERN N

               HIT # 1447




                                                                                      Bingo scorecard




•Dedicated device: maximum parallelism
•Each pattern with private comparator
•Track search during detector readout

   June 2005                            Mauro Dell'Orso - Beauty 2005                                       11
                  AM chip & system                       SVT


                • Undoable with standard electronics (90’s)
                 Full custom VLSI chip - 0.7m (INFN-Pisa)
                • 128 patterns, 6x12bit words each
                • Working up to 40 MHz



•   Limit to 2-D
•   6 layers: 5 SVX + 1 COT
•   ~250 micron bins  32k roads / 300 j sector
•   >95% coverage for Pt > 2 GeV

    June 2005           Mauro Dell'Orso - Beauty 2005   12
                                                         AM chip internal structure                                                                SVT

                                                                                                          AB<6:0> ( R/W MODE)
           SELP<2:0>
                                                                                            ADDRESS DECODER
    SELECT PLANE
      DECODER
                                                  pattern 0                           pattern 1                                 pattern 127
                                                       12 bits word     HIT                                   HIT                                 HIT
            DATA BUS MULTIPLEXER




                                   layer0                                               12 bits word                             12 bits word
                                                      12 bits compar.   BIT            12 bits compar.        BIT               12 bits compar.   BIT
                                   layer1

DB<11:0>                           layer2

                                   layer3

                                   layer4

                                   layer5



                                                           COUNT
      OPC<3:0>                                                                   HIT COUNTER
                                                            SHIFT
                                            CONTROL




           ENP*
           SEL*                                                                    MATCH BIT
           CLKB
                                                                                                    ADDRESS ENCODER
        CLKA
         OR*                                                                                                        AB<6:0> (OUTPUT MODE)



      June 2005                                                               Mauro Dell'Orso - Beauty 2005                                       13
                AM chip working principle                                                      SVT


                     Layer 1           Layer 2                  Layer 3        Layer 4
ONE PATTERN

                                                                                word
                Patt 0   word   FF        word             FF    word     FF             FF




                                FF                         FF             FF             FF
                Patt 1




                                                                                                   Output Bus
                                                                          FF
                Patt 2          FF                         FF                            FF




                Patt 3          FF                        FF              FF             FF




                         HIT               HIT                   HIT            HIT

    June 2005                   Mauro Dell'Orso - Beauty 2005                                 14
                                Track Fitting                         SVT

• Track confined to a road: fitting becomes easy

• Linear expansion in the hit positions xi:
        – Chi2 = Sumk ( (cik xi)^2 )
        – d = d0+ai xi ; phi = phi0+ bi xi ; Pt = ...


• Fit reduces to a few scalar products: fast evaluation
        – (DSP, FPGA …)


• Constants from detector geometry
        – Calculate in advance
        – Correction of mechanical alignments via linear algorithm
            • fast and stable
            • A tough problem made easy !


June 2005                           Mauro Dell'Orso - Beauty 2005    15
            From non-linear to linear constraints                           SVT



       Non-linear geometrical constraint for a circle:
                F(x1 , x2 , x3 , …) = 0




                                                                    D xi


  But for sufficiently small displacements:

     F(x1 , x2 , x3 , …) ~ a0 + a1Dx1 + a2Dx2 + a3Dx3 + … = 0
            with constant ai             (first order expansion of F)

June 2005                           Mauro Dell'Orso - Beauty 2005          16
            Constraint surface                    SVT




June 2005        Mauro Dell'Orso - Beauty 2005   17
            SVT crates in CDF counting room             SVT




June 2005              Mauro Dell'Orso - Beauty 2005   18
                                  The Device                                                   SVT
                                                 AM Sequencer              Super
                                                                                      AM Board
                                                                           Strip



                   Hit Finder
                                Hits

Detector                                                                   Matching
Data                                                               Roads
                                                                           Patterns

                                                                                         Roads +
                                                                                      Corresponding
                                                                                          Hits




                                                      Hit Buffer
                      L2 CPU
                                                               Tracks +
                                                          Corresponding Hits

       June 2005                   Mauro Dell'Orso - Beauty 2005
                                                                                   Track Fitter
                                                                                            19
                 AM Board                               SVT




            x8




                                                 x16         VME




                                                            AMbus

June 2005        Mauro Dell'Orso - Beauty 2005         20
                          Hadronic B decays with SVT                                                           SVT

                                            Two paths
@3x   1031 cm-2     s-1

           • L1:                                                     • L1:
                  •Two XFT tracks                                           •Two XFT tracks
                  •Pt > 2 GeV; Pt1 + Pt2 > 5.5 GeV                          •Pt > 2 GeV; Pt1 + Pt2 > 5.5 GeV
                  •Df < 135°                                                •Df < 135°

           • L2:                                                     • L2:
                  •d0>100 m for both tracks                                •d0>120 m for both tracks
                  •Validation of L1 cuts with Df>20°                        •Validation of L1 cuts with Df>2°
                  •Lxy > 200 m                                             •Lxy > 200 m
                  •d0(B)<140 m                                             •d0(B)<140 m

                                   Two body                                                 Many body
                                    decays                                                   decays

      June 2005                             Mauro Dell'Orso - Beauty 2005                                  21
B0  had + had Trigger



                         The SVT advantage:
   SVT                   3 orders of magnitude
                                                       Performance @ 5x1031                                         SVT



                                                                            35m  33m
                    24 s                                                   resol  beam
                                                                              s = 48m                   SVT
                                                                                                          Impact parameter

             0        10        20 30 40              50
                             Latency (s)

                                                           0.8
Efficiency




                     Given a fiducial offline track                           -500          -250    0        250        500
                     with SVX hits in 4/4 layers                                                   (m)
                     used by SVT


             0.00             0.05        0.10              0.15
                 June 2005                                  Mauro Dell'Orso - Beauty 2005                          23
                     Impact parameter (cm)
                                 SVX only                                                 SVT

                                                         impact parameter distribution

 Good tracks from just 4                                Silicon only
 closely spaced silicon layers                              no XFT

 I.p. as expected due to the
 lack of curvature                                       s ~ 87 m
 information




June 2005                        Mauro Dell'Orso - Beauty 2005                           24
                Online beamline fit & correction                                              SVT

                                                                         y
                                                                                f

                                                                     d              x
d
                            Raw                                <d> = Ybeamcosf – Xbeamsinf



d
                       Subtracted


                 phi


    June 2005                       Mauro Dell'Orso - Beauty 2005                            25
                 Hadron-hadron mass distribution                    SVT


            Ks

                      D0



                      Mhh (GeV)
                                                            Bh h
                                                               L~180 pb-1




June 2005                   Mauro Dell'Orso - Beauty 2005         26
                                      Upgrading SVT                                                                  SVT


       raw data from         Hit Finders                   Sequencer
       SVX front end
                                                                                  Associative Memory
                                      COT tracks
                                      fromXTRP
                                                                                           x 12 phi sectors
                                                                                   roads

                                                                                               Road Warrior
                 12 fibers

                                           hits
                                                                                                 Track Fitter

                                                    Merger                  hits

                                                                                                       to Level 2
                                                                            Hit Buffer

Reduce SVT processing time: c1+c2*N(Hit) +c3*N(Comb.)
                                                                                              RW:
1.   More patterns  thinner roads                                                           Remove
2.   Move Road Warrior before the HB                                                         ghosts

3.   New TF++, HB++, AMS++, AM++ @ > 40MHz

     June 2005                                    Mauro Dell'Orso - Beauty 2005                                     27
            Dead Time vs. L1 Accept Rate                                  SVT




                                                      SVT @ 3 x 1032


                                                      SVT @ 0.5 x 1032

                                                      UPGRADE @ 3 x 1032




June 2005             Mauro Dell'Orso - Beauty 2005                      28
                  New AM chip                              SVT

• Standard Cell UMC 0.18 m
  10x10 mm die - 5000 patterns
  6 input hit buses
  tested up to 40 MHz, simulated up to 50 MHz

• 116 prototype chips on September 2004
  MPW run – low yield 37%

• 3000 production chips on April 2005
  good yield 70%
  private masks         better process parameter tuning
                          for dense memory
   June 2005            Mauro Dell'Orso - Beauty 2005   29
                 LAMB++                      SVT




June 2005   Mauro Dell'Orso - Beauty 2005   30
                    What next ?                             SVT



                             Next challenge is silicon tracking
                                at both Level 1 & Level 2



            SVT

                                     Fast Track (FTK)

             LHC, Super B
             factory, ILC


June 2005             Mauro Dell'Orso - Beauty 2005        31
                                SUMMARY                                   SVT


            • The design and construction of SVT was a significant
              step forward in the technology of fast track finding

            • We use a massively parallel/pipelined architecture
              combined with some innovative techniques such as
              the associative memory and linearized track fitting

            • Performance of SVT is as expected

            • CDF is triggering on impact parameter and collecting
              data leading to significant physics results

            • B-physics, and not only, at hadron colliders
              substantially benefits of on-line tracking with off-line
              quality


June 2005                         Mauro Dell'Orso - Beauty 2005          32
                                                 SVT




            BACKUP SLIDES




June 2005       Mauro Dell'Orso - Beauty 2005   33
                                   Level 1 drift chamber trigger (XFT)                             SVT

                                                                                 Finds pT>1.5 GeV
                                                                                 tracks in 1.9 s

                                                                                 For every bunch
                                                                                 crossing (132 ns)!

                                                                                 s(1/pT) = 1.7%/GeV

                                                                                 s(f0) = 5 mrad
XFT efficiency




                                                                                 96% efficiency


                 1           1.5      2      2.5      3     3.5    4
                                    offline transverse momentum (GeV)
                 June 2005                       Mauro Dell'Orso - Beauty 2005                    34
                          CDF Run II trigger architecture                                                               SVT

                      detector elements

    CAL        COT
                            DØ resultsCES
                           MUON
                                 SVX



                            MUON
                                                                          •      Tracking system
               XFT                               XCES
                            PRIM.
                                                                                   – central outer tracking (COT)
                                                                                   – silicon tracking (SVX II & ISL)
              XTRP
                                                                          •      three-level trigger
   L1           L1            L1                                                   – L1: 5.5 s pipeline
  CAL         TRACK          MUON
                                                                                           • XFT: L1 2D COT track
                                                                                   – L2: 20 s processing time
             GLOBAL                                                                        • two stages of 10 s
               L1
                                                                          •      SVT at stage 1 of L2
  L2
 CAL
                                          SVT
                                                                                   –      SVX II readout
                                                                                   –      hit cluster finding
            GLOBAL
            LEVEL 2
                                                TSI/CLK                            –      pattern recognition
                                                                                   –      track fitting



June 2005                                                 Mauro Dell'Orso - Beauty 2005                                35
            2005 Trigger Performance & Limitations                                                            SVT

Level           Input rate   Output   Potential limitations                    Future upgrades              2006
                              rate    Current limitation                                                   Output
                                                                                                            rate
   1             ~1MHz       25kHz    •Silicon readout                         •XFT upgrade                 25kHz
                              (spec   •SVT processing time                     •SVT upgrade               (higher at
                             45kHz)   •L2 processing time                      •L2 Pulsar DONE             low lum)



   2             25kHz       400Hz    •Readout (non Si)                        •TDC modification            1kHz
                              (spec   •Event builder                           •Event builder
                             300Hz)   •L3 processing                           •Faster L3 nodes




   3             380Hz       85Hz     •CSL/data logging                        •Parallel logger 45 MB/s    100Hz
                             (spec                                             •CSL upgrade >60MB/s
                             75Hz)




Rates are “peak rates that we can achieve with good livetime.”
    June 2005                                  Mauro Dell'Orso - Beauty 2005                                 36
                       Building the “Pattern Bank”                                 SVT

    Instead of looking for hit combinations such that f(x1,x2,x3,…) = 0

1.        Build a database with all patterns corresponding to “good” tracks
2.        Compare hits in each event with all patterns to find track candidates


5

4

3

2

1




In this example:
Straight lines, 5 layers, 12 bins/layer

                   Total number of patterns ~ (12)2*(5-1) = 576

      June 2005                           Mauro Dell'Orso - Beauty 2005           37
                      SVT basic architecture                                                  SVT

• Pattern recognition and track fitting done separately and pipelined

            Pattern recognition with Associative Memory (AM)
                highly parallel algorithm
                using coarser resolution to reduce memory size
                                                                        Hits
                        Hits                                                   Associative
                                     Hit Buffer                                 Memory

                                                                      Roads

                                                                     Track
                      Roads + hits                                   Fitter    Tracks
                                                                               (d, pT, f)



            Fast track fitting with linear approximation
               using full resolution of the silicon vertex detector

June 2005                            Mauro Dell'Orso - Beauty 2005                           38
            SVT Wedges                        SVT




June 2005    Mauro Dell'Orso - Beauty 2005   39
            An SVT Slice                       SVT




June 2005     Mauro Dell'Orso - Beauty 2005   40
                          SVT system architecture                                                                        SVT




 raw data from          Hit Finders
                                                           Sequencer
 SVX front end                                                                      Associative Memory
                                      COT tracks
                                      fromXTRP

                                                                                      roads



            12 fibers

                                          hits                                                           Track Fitter


                                                     Merger                  hits
                                                                                                           to Level 2

                                                                                      Hit Buffer
     x 12 phi sectors




June 2005                                        Mauro Dell'Orso - Beauty 2005                                          41
                            SVT: board count                                          SVT

•           Hit Finders       42
•           Mergers           16
•           Sequencers        12                                   INFN
•           AMboards          24
•           Hit Buffers       12                                   INFN & Geneva
•           Track Fitters     12                                   University of Chicago
•           Spy Controls       8
•           XTFA               1
•           XTFB               2
•           XTFC               6
•           Ghostbuster        1

            TOTAL            136        + spares


June 2005                          Mauro Dell'Orso - Beauty 2005                     42
                          SVT: board and crate layout                                             SVT


            CPU               Hit Finder                                Merger         XTFA

            Tracer            Sequencer                                 Hit Buffer     XTFB

            Spy Control       Associative Memory                        Track Fitter   XTFC




            b0svt00               b0svt07                             b0svt06          b0svt05




            b0svt01               b0svt02                             b0svt03          b0svt04


June 2005                                   Mauro Dell'Orso - Beauty 2005                        43
              SVT data volume requires parallelism                   SVT




                  0,1   fan-out             fan-in          10,11


                 2,3
                          4,5
                                              6,7           8,9


            Reduces gigabytes/second to megabytes/second
June 2005   Peak (avg): 20 (0.5) GB/s      100 (1.5) MB/s
                            Mauro Dell'Orso - Beauty 2005           44
                     Expectations for runII                      SVT

Rates within bandwidth @ 0.7 1032
- Level 1: 20 kHz (bw 50 kHz)
- Level 2: 39 Hz (bw 300 Hz)
- Level 3: negligible

Expected yields in run II (2 fb-1)
 Mode              Events
 Bd  p+ p-         15,200 angle  at few degrees level
 Bs  Ds p         10,600 
 Bs  Ds ppp       12,800  5s sensitivity up to xs ~ 40
 Bs  D*s p          9,400 
 D* p             300,000
 Z  b-bbar         32,000

              N.B. : yields without SVT  O(1) event !

  June 2005                     Mauro Dell'Orso - Beauty 2005   45
              Promise is promise                                                   SVT




            s ~ 45 m
                                           What we promised…. From SVT
                                           TDR (’96) using offline silicon hits
                                           and offline CTC tracks




June 2005               Mauro Dell'Orso - Beauty 2005                             46
                       SVT performance                                                 SVT
                   Not just impact parameter
            Loop on all SVT-COT track pairs and compare parameters



    j: SVT – COT                                               Curvature: SVT - COT




June 2005                      Mauro Dell'Orso - Beauty 2005                          47
                                  Level 1 @Lum=40x1030 cm-2 sec-1                            SVT

•   Two Major Components
     – Calorimeter Triggers: Jets, electrons, photons, etc.                    ~4-5 kHz
       In SVT: L1_JET10_&_SET90 (Higgs multijet)
                           L1_TWO_TRK2_&_TWO_CJET5 (Zbb)
                           L1_MET15_&_TWO_TRK2 (Higgs Z  nn)                  ~2 kHz
                           L1_TWO_TRK10_DPHI20 (Di TAU exotic)
                           L1_EM8              (Gamma + bjet)
                           L1_CEM4_PT4         (B electron)
                           L1_CMUP6_PT4        (B muon)

     – Hadronic B Decays: Two XFT tracks                                       ~11-12 kHz
•   Using three classes of B triggers
     – Scenario A
                • pT>2, pT,1+pT,2>5.5, opp. charge, Df<135; DPS
     – Scenario C
                • pT>2.5, pT,1+pT,2>6.5, opp. charge, Df<135; PS by 2
     – Low PT
                • pT>2, Df<90; Heavy DPS, saturate bandwidth
                • Not considered for long-term




    June 2005                                  Mauro Dell'Orso - Beauty 2005                48
         Physics Prospects: All-Hadronic B decay SVT
                        Trigger
 Impact parameter from the SVT                       Trigger on secondary vertices (B hadrons)

                                                       B0d           pp    ( CP Violation)
        Trigger Strategy                               B0s           Ds np ( Bs mixing )
                                                        Z0            bb     (b-jet calibration
Level 1: 2D COT tracks (XFT)                                                 / top mass)
 • Two stiff tracks (Pt > 2.0 GeV/c)                    H              bb
 • Remove back-to-back pairs ( d f < 135 )
                                      o

 • Opposite charge

Level 2: SVT tracks
 • Two tracks with large impact parameter
 • Vertex tracks - require positive decay length
Level 3: full event reconstruction


    June 2005                        Mauro Dell'Orso - Beauty 2005                           49
            WHY 4/5?   Signal Yields with 4/5              SVT



                                                          1430
                                                  D0

                                                         4/5
                 J/psi


                                                          970
                                                  D0
                                                         4/4

June 2005                Mauro Dell'Orso - Beauty 2005    50
Accurate deadtime model (ModSim) to                 SVT
                              1. Two SRCs in parallel
 understand DAQ upgrades      2. L2 processor upgrade
                                                            3.   87 bit SVX digit.
              4/4                                           4.   - 3 sec in SVT proc.time
                                                            5.   cut SVT tails above 27
   DeadTime



                                                                 sec




                                                          BUT the recent
                                                          use of 4/5 in SVT
                    L1A rate (kHz)                        changes the conditions!
4/4 – 4/5                                            4/4 – 4/5




      June 2005           Mauro Dell'Orso - Beauty 2005                            51
7.6 MHz Crossing rate
                                                      CDF DAQ & Trigger                        SVT
                                  Detector
                                  Raw Data            Design goals
                                           Level 1
 Level 1
                           Level 1         •7.6 MHz Synchromous Pipeline
 pipeline:
                           Trigger         •5544 ns Latency
 42 clock
  cycles                           L1
                                  Accept
                                           •50 KHz accept rate
                                           •50 kHz                                  ~20 kHz actual
                                           Level 2
                                                                              SVT here
Level 2                   Level 2          • Asynchronous 3 Stage Pipeline
buffer:                   Trigger
   4                                       • 20 s average Latency
                                                    Latency
events                                     • 300 Hz accept rate            ~35 s actual
                          L2
                         Accept
 DAQ
buffers

             L3 Farm              To Mass Storage (50~100 Hz)

                                                                                 Tails are important
             June 2005                           Mauro Dell'Orso - Beauty 2005                52
                                             SVT




June 2005   Mauro Dell'Orso - Beauty 2005   53
            Upgrading SVT                                           SVT



            1st pulsar:
             AMS+RW                      AM++
                                       512k patt.




                                                     3rd pulsar:
                                                         TF


              2nd pulsar:
                  HB




June 2005            Mauro Dell'Orso - Beauty 2005                 54
                          512 Kpattern / phi sector                                          SVT

             LAMB GLUE

                     AM



                                                                  VME
                                                                INTERFAC
                                                                    E

             INDI

                                TOP
                                                                Input
                                                                                Clock
                                GLUE
                    PIPELINE                                    Control         Distrib.
  LAMB              REGISTERs




                                                                           CONNECTO
                                                                           HIT/ROAD
CONNECTORs
                                                                                      To
                                                                                      AMS




                                                                           R
 June 2005                      Mauro Dell'Orso - Beauty 2005                               55
                    Pulsar in SVT++                                 SVT
Large memory cannot be handled by old SVT boards.
The new ones are developed using Pulsar
•Fast enough to handle the new amount of data
•SVT interface built in
•Developers can concentrate on firmware (= board functionalities)
                             Sequencer + RW
                             RW remove redundant roads as soon
                             as they are returned by AM
                             sensitively reducing the amount of
                             data handled by the Hit Buffer
                                  Hit Buffer and Track Fitter
                                  •They need to handle larger amount
                                  of roads and hits
                                  •Fully exploit the fast logic of the
                                  Pulsar



June 2005                Mauro Dell'Orso - Beauty 2005             56
                    Upgrade is on schedule                                 SVT


                                                                 AM++
Real data




 AMS/RW




•AM++ and RW with 32k patterns have been already used in test runs for
data tacking
•Plan to install AM++ with 32k pattern in July
•Studies of 128k patterns coverage and efficiency are underway
•Plan to install TF++ as soon as it will be ready (August) then move to 128k
•HB++ expected to be installed during fall with 512k pattern memory

  June 2005                    Mauro Dell'Orso - Beauty 2005              57
             Circular buffers monitor every data link:                    SVT
                   like a built-in logic analyzer

                                                              EE   TAG




               SVT board 1   IN                               EE   TAG



                                  FIFO

                                                              EE   TAG



                                                              EE   TAG




 System wide uniform         OUT
     inter-board
                             IN
communication protocol
                                  FIFO




                             OUT
             SVT board 2




 June 2005                    Mauro Dell'Orso - Beauty 2005              58
                    On-crate monitoring of circular buffers                                      SVT

               monitor resolution                                           monitor acceptance
                         107 tracks
                          per hour!




  -1000 -500    0 500 1000                                              0   1   2 3 4 5 6
          impact parameter (m)
                                                                                azimuth (radians)

             monitor noisy channels                                Sample hits, roads,
                                                                   tracks at high rate
occupancy




                                                                   Check boards against
                                                                   emulation software

                     detector channel
        June 2005
                                                                   Fit for beam position …
                                        Mauro Dell'Orso - Beauty 2005                           59
                                 Why SVT succeeded                               SVT
 – Performance:
            • Parallel/pipelined architecture
            • Custom VLSI pattern recognition
            • Linear track fit in fast FPGAs

 – Reliability:
            •   Easy to sink/source test data (many boards can self-test)
            •   Modular design; universal, well-tested data link & fan-in/out
            •   Extensive on-crate monitoring during beam running
            •   Detailed CAD simulation before prototyping
                  – See poster by Mircea Bogdan

 – Flexibility:
            • System can operate with some (or all) inputs disabled
            • Building-block design: can add/replace processing steps
            • Modern FPGAs permit unforeseen algorithm changes

 – Key: design system for easy testing/commissioning




June 2005                                 Mauro Dell'Orso - Beauty 2005         60
                   Doing silicon tracking quickly                   SVT


• Three key features of SVT allow us to do in tens of microseconds what
  typically takes software hundreds of milliseconds:

    – Parallel/pipelined architecture

    – Custom VLSI pattern recognition

    – Linear track fit in fast FPGAs




   June 2005                      Mauro Dell'Orso - Beauty 2005    61

				
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