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					                                                      project005 read/writeprintf
                                                        prac4
                                                           prac63b overflow_interrupt
                                                             six-three
                                                   project006 timer0 prescalerproject004
WDR : Watchdog Reset                                0 0 0 0 0 0 0 0 0 0                   0   1
SLEEP : Sleep                                       0 0 0 0 0 0 0 0 0 0                   0   1
NOP : No Operation                                  0 0 0 0 0 6 3 19 0 0                 28
CLH : Clear Half Carry Flag in SREG                 0 0 0 0 0 0 0 0 0 0                   0   1
SEH : Set Half Carry Flag in SREG                   0 0 0 0 0 0 0 0 0 0                   0   1
CLT : Clear T in SREG                               1 0 0 0 0 0 0 0 0 0                   1
SET : Set T in SREG                                 1 0 0 0 0 0 0 0 0 0                   1
CLV : Clear Twos Complement Overflow                0 0 0 0 0 0 0 0 0 0                   0   1
SEV : Set Twos Complement Overflow.                 0 0 0 0 0 0 0 0 0 0                   0   1
CLS : Clear Signed Test Flag                        0 0 0 0 0 0 0 0 0 0                   0   1
SES : Set Signed Test Flag                          0 0 0 0 0 0 0 0 0 0                   0   1
CLI : Global Interrupt Disable                     # # 0 0 1 0 2 0 0 0                   35
CLZ : Clear Zero Flag                               0 0 0 0 0 0 0 0 0 0                   0   1
SEZ : Set Zero Flag                                 0 0 0 0 0 0 0 0 0 0                   0   1
CLN : Clear Negative Flag                           0 0 0 0 0 0 0 0 0 0                   0   1
SEN : Set Negative Flag                             0 0 0 0 0 0 0 0 0 0                   0   1
CLC : Clear Carry                                   0 0 0 0 0 0 0 0 0 0                   0   1
SEC : Set Carry                                     2 0 0 0 0 0 0 0 0 0                   2
BLD Rd, b : Bit load from T to Register             0 0 0 0 0 0 0 0 0 0                   0   1
BST Rd, b : Bit Store from Register to T            2 # 0 0 0 0 0 0 0 2                  27
BCLR s : Flag Clear                                 0 0 0 0 0 0 0 0 0 0                   0   1
BSET s : Flag Set                                   0 0 0 0 0 0 3 0 0 0                   3
SWAP Rd : Swap Nibbles                              0 0 0 0 0 0 0 0 0 0                   0   1
ASR Rd : Arithmetic Shift Right                     0 0 0 0 0 0 0 0 0 0                   0   1
ROR Rd : Rotate Right Through Carry                # # 0 0 0 0 0 0 0 0                 636
LSR Rd : Logical Shift Right                       # # 0 0 0 0 0 0 0 0                 206
CBI P,b : Clear Bit in I/O Register                 0 0 0 0 0 0 0 0 0 0                   0   1
SBI P,b : Set Bit in I/O Register                   9 0 0 0 0 0 0 0 0 0                   9
POP Rd : Pop Register from Stack                   # 0 0 3 6 0 8 1 0 0                   74
PUSH Rr : Push Register on Stack                   # # 0 5 2 0 8 2 4 2                 199
OUT P, Rr : Out Port                               # # 7 3 3 2 4 3 3 3                 111
IN Rd, P : In Port                                 # # 3 4 2 1 5 2 4 0                 104
STS k, Rr : Store Direct to SRAM                   # 6 0 0 0 0 1 0 0 6                   39
STD_z Z+,q,Rr : Store Indirect with Displacement   # 0 0 4 3 0 6 2 2 0                   42
ST_z_minus -Z, Rr : Store Indirect and Pre-Dec.     0 0 0 0 0 0 0 0 0 0                   0   1
ST_z_plus Z+, Rr : Store Indirect and Post-Inc.     2 0 0 0 0 0 0 0 0 0                   2
ST_z Z, Rr : Store Indirect                         0 0 0 0 0 0 0 0 0 0                   0   1
STD_y Y+,q,Rr : Store Indirect with Displacement   # # 0 # # 0 0 0 0 0                 217
ST_y_minus -Y, Rr : Store Indirect and Pre-Dec.     0 0 0 0 0 0 0 0 0 0                   0   1
ST_y_plus Y+, Rr : Store Indirect and Post-Inc.     0 3 0 0 0 0 0 0 0 0                   3
ST_y Y, Rr : Store Indirect                         0 0 0 0 0 0 0 0 0 0                   0   1
ST_x_minus - X, Rr : Store Indirect and Pre-Dec.    0 0 0 0 0 0 0 0 0 0                   0   1
ST_x_plus X+, Rr : Store Indirect and Post-Inc.    # # 0 0 0 0 1 0 # #                1145
ST_x X, Rr : Store Indirect                         2 0 0 0 0 0 0 0 0 0                   2
LDS Rd, k : Load Direct from SRAM                  # 3 0 0 0 0 7 0 0 0                   54
LDD_z Rd, Z+,q : Load Indirect with Displacement   # 3 0 4 0 0 3 0 0 0                   34
LD_z_minus Rd, -Z : Load Indirect and Pre-Dec.      0 0 0 0 0 0 0 0 0 0                   0   1
LD_z_plus Rd, Z+ : Load Indirect and Post-Inc.      4 0 0 0 0 0 0 0 0 0                   4
LD_z Rd, Z : Load Indirect                          0 0 0 0 0 0 0 0 0 0                   0   1
LDD_y Rd,Y+,q : Load Indirect with Displacement   #   #   0   #   #   0 0 0 0 0      547
LD_y_minus Rd, - Y : Load Indirect and Pre-Dec.   0   0   0   0   0   0 0 0 0 0        0   1
LD_y_plus Rd, Y+ : Load Indirect and Post-Inc.    0   0   0   0   0   0 0 0 0 0        0   1
LD_y Rd, Y : Load Indirect                        0   0   0   0   0   0 0 0 0 0        0   1
LD_x_minus Rd, - X : Load Indirect and Pre-Dec.   0   0   0   0   0   0 0 0 0 0        0   1
LD_x_plus Rd, X+ : Load Indirect and Post-Inc.    0   0   0   0   0   0 0 0 0 0        0   1
LD_x Rd, X : Load Indirect                        2   0   0   0   0   0 0 0 0 0        2
LDI Rd, K : Load Immediate                        #   #   3   #   #   2 40 16 # #    632
MOV Rd, Rr : Move Between Registers               #   #   0   #   0   0 3 0 0 #      917
BRID k : Branch if Interrupt Disabled             0   0   0   0   0   0 0 0 0 0        0   1
BRIE k : Branch if Interrupt Enabled              0   0   0   0   0   0 0 0 0 0        0   1
BRVC k : Branch if Overflow Flag is Cleared       0   0   0   0   0   0 0 0 0 0        0   1
BRVS k : Branch if Overflow Flag is Set           0   0   0   0   0   0 0 0 0 0        0   1
BRTC k : Branch if T Flag Cleared                 6   #   0   0   0   0 0 0 0 3       54
BRTS k : Branch if T Flag Set                     0   0   0   0   0   0 0 0 0 0        0   1
BRHC k : Branch if Half Carry Flag Cleared        0   0   0   0   0   0 0 0 0 0        0   1
BRHS k : Branch if Half Carry Flag Set            0   0   0   0   0   0 0 0 0 0        0   1
BRLT k : Branch if Less Than Zero, Signed         0   6   0   0   #   0 0 0 0 0       39
BRGE k : Branch if Greater or Equal, Signed       0   0   0   0   0   0 0 0 0 0        0   1
BRPL k : Branch if Plus                           0   6   0   #   0   0 0 0 0 0       94
BRMI k : Branch if Minus                          0   0   0   0   0   0 0 0 0 0        0   1
BRLO k : Branch if Lower                          #   #   0   #   0   0 0 0 0 #      756
BRSH k : Branch if Same or Higher                 5   #   0   1   0   0 0 0 0 1       25
BRCC k : Branch if Carry Cleared                  0   0   0   0   0   0 0 0 0 0        0   1
BRCS k : Branch if Carry Set                      0   0   0   0   0   0 0 0 0 0        0   1
BRNE k : Branch if Not Equal                      #   #   0   4   2   0 3 2 # #     2217
BREQ k : Branch if Equal                          #   0   0   #   0   0 10 0 0 0      43
BRBC s, k : Branch if Status Flag Cleared         0   0   0   0   0   0 0 0 0 0        0   8
BRBS s, k : Branch if Status Flag Set             0   0   0   0   0   0 0 0 0 0        0   8
SBIS P, b : Skip if Bit in I/O Register is Set    0   0   0   0   0   0 0 0 0 0        0   1
SBIC P, b : Skip if Bit in I/O Register Cleared   0   0   0   0   0   0 0 0 0 0        0   1
SBRS Rr, b : Skip if Bit in Register is Set       #   #   0   0   0   0 0 0 0 0      236
SBRC Rr, b : Skip if Bit in Register Cleared      #   #   0   0   0   0 0 0 0 2       46
CPI Rd,K : Compare Register with Immediate        #   #   0   #   #   0 3 2 # #     1259
CPC Rd,Rr : Compare with Carry                    #   #   0   #   #   0 3 2 # #     3256
CP Rd,Rr : Compare                                #   #   0   #   0   0 0 0 0 #      771
CPSE Rd,Rr : Compare, Skip if Equal               0   0   0   0   0   0 0 0 0 0        0   1
RETI : Interrupt Return                           0   0   0   0   0   0 1 0 0 0        1
RET : Subroutine Return                           #   #   0   1   1   0 0 0 0 5      168
ICALL : Indirect Call to (Z)                      8   0   0   0   0   0 0 0 0 0        8
RCALL k : Relative Subroutine Call                #   #   0   3   3   0 1 2 2 9      184
IJMP : Indirect Jump to (Z)                       4   8   0   0   0   0 0 0 0 0       12
RJMP k : Relative Jump                            #   #   3   #   #   1 4 3 3 5      385
SER Rd : Set Register                             0   0   0   0   0   0 0 0 0 0        0   1
LPM: Load Program Memory and Post-Inc             #   #   0   0   0   0 0 0 # #       92
DEC Rd : Decrement                                #   #   0   #   0   0 0 0 0 #      879
INC Rd : Increment                                0   0   0   0   0   0 0 0 0 0        0   1
NEG Rd : Two's Complement                         0   0   3   0   0   0 0 0 0 0        3
COM Rd : One’s Complement                         8   #   0   0   0   0 0 0 0 4       88
EOR Rd, Rr : Exclusive OR Registers               #   #   1   1   1   0 2 1 1 3      112
ORI Rd, K : Logical OR Register and Constant          2   0   0   0   0   0   0   0   0   0       2
OR Rd, Rr : Logical OR Registers                      8   3   0   0   0   0   0   0   0   0      11
ANDI Rd, K : Logical AND Register and Constant        6   8   0   4   0   0   6   0   0   0      30
AND Rd, Rr : Logical AND Registers                    #   6   0   0   0   0   7   0   0   0      26
SBIW Rdh:Rdl,K : Subtract Immediate from Word         4   #   0   2   0   0   3   0   0   0      28
SBCI Rd, K : Subtract with Carry Constant from Reg.   #   3   0   0   0   0   0   0   0   3      25
SBC Rd, Rr : Subtract with Carry two Registers        #   #   0   0   0   0   0   0   0   9     294
SUBI Rd, K : Subtract Constant from Register          #   #   0   #   0   0   0   0   0   1      67
SUB Rd, Rr : Subtract two Registers                   #   #   0   0   0   0   0   0   0   7     187
ADIW                                                  #   #   0   0   #   0   0   0   #   #     140
ADC Rd, Rr : Add with Carry two Registers             #   #   0   #   #   0   0   0   0   #    6599
ADD Rd, Rr : Add two Registers                        #   #   0   #   #   0   0   0   0   3     438
SEI : Global Interrupt Enable                         0   0   0   0   0   0   0   0   0   0       0   1

                                                                                              23651
             Bins
   1     1            1   47
   1     1           50
  56    56          100
   1     1          150
   1     1          200
   2     2          250
   2     2          300
   1     1          350
   1     1          400
   1     1          450
   1     1
  70    70
   1     1
   1     1
   1     1
   1     1
   1     1
   4     4
   1     1
  54    54
   1     1
   6     6
   1     1
   1     1
1272   500
 412   412
   1     1
  18    18
 148   148
 398   398
 222   222
 208   208
  78    78
  84    84
   1     1
   4     4
   1     1
 434   434
   1     1
   6     6
   1     1
   1     1
2290   500
   4     4
 108   108
  68    68
   1     1
   8     8
   1     1
1094   500
   1     1
   1     1
   1     1
   1     1
   1     1
   4     4
1264   500
1834   500
   1     1
   1     1
   1     1
   1     1
 108   108
   1     1
   1     1
   1     1
  78    78
   1     1
 188   188
   1     1
1512   500
  50    50
   1     1
   1     1
4434   500
  86    86
   8     8
   8     8
   1     1
   1     1
 472   472
  92    92
2518   500
6512   500
1542   500
   1     1
   2     2
 336   336
  16    16
 368   368
  24    24
 770   500
   1     1
 184   184
1758   500
   1     1
   6     6
 176   176
 224   224
    4     4
   22    22
   60    60
   52    52
   56    56
   50    50
  588   500
  134   134
  374   374
  280   280
13198   500
  876   500
    1     1
Upper Limit Frequency
           0          0
          50        67                                        Instruction coverage histogram
         100        12    0
                                          80
         150          4
         200          3                   70
         250          3
                                          60
         300          1
         350          1                   50




                              Frequency
         400          3
         450          2                   40
500+                16                    30

                                          20

                                          10

                                           0
                                               -50   0      50   100   150   200   250   300   350
                                                         Instruction coverage (number of times executed)
         350   400   450   500
er of times executed)
Upper Limit Frequency
           0          2
                                                                Better Histogram
          50        65
                                      70
         100        12
         150          4
                                      60
         200          3
         250          3               50
         300          1




                          Frequency
         350          1               40
         400          3
         450          2               30
         500        16
                                      20

                                      10

                                      0
                                           -50   0   50   100   150   200   250    300   350   400   450
                                                                      Data Value
450   500
Upper Limit Frequency
           1        49
                                                                Better Histogram
          51        18
                                      60
         101        12
         151          4
         201          3               50
         251          3
         301          1               40




                          Frequency
         351          1
         401          3               30
         451          2
         501        16                20


                                      10


                                      0
                                           -49   1   51   101   151   201   251    301   351   401   451
                                                                      Data Value
451   501
Upper Limit Frequency
          50        67
         100        12
         150          4
         200          3
         250          3
         300          1
         350          1
         400          3
         450          2
         500        16
Upper Limit Frequency
          50        67
         100        12
         150          4
         200          3
         250          3
         300          1
         350          1
         400          3
         450          2
         500          1
         550          0
         600          1
         650          0
         700          0
         750          0
         800          1
         850          0
         900          1
         950          0
        1000          0
        1050          0
        1100          1
        1150          0
        1200          0
        1250          0
        1300          2
        1350          0
        1400          0
        1450          0
        1500          0
        1550          2
        1600          0
        1650          0
        1700          0
        1750          0
        1800          1
        1850          1
        1900          0
        1950          0
        2000          0
        2050          0
        2100          0
        2150          0
        2200          0
        2250          0
        2300          1
2350   0
2400   0
2450   0
2500   0
2550   1
2600   0
2650   0
2700   0
2750   0
2800   0
2850   0
2900   0
2950   0
3000   0
3050   0
3100   0
3150   0
3200   0
3250   0
3300   0
3350   0
3400   0
3450   0
3500   0
3550   0
3600   0
3650   0
3700   0
3750   0
3800   0
3850   0
3900   0
3950   0
4000   0
4050   0
4100   0
4150   0
4200   0
4250   0
4300   0
4350   0
4400   0
4450   1
4500   0
4550   0
4600   0
4650   0
4700   0
4750   0
4800   0
4850   0
4900   0
4950   0
5000   0
5050   0
5100   0
5150   0
5200   0
5250   0
5300   0
5350   0
5400   0
5450   0
5500   0
5550   0
5600   0
5650   0
5700   0
5750   0
5800   0
5850   0
5900   0
5950   0
6000   0
6050   0
6100   0
6150   0
6200   0
6250   0
6300   0
6350   0
6400   0
6450   0
6500   0
6550   1
6600   0
6650   0
6700   0
6750   0
6800   0
6850   0
6900   0
6950   0
7000   0
7050   0
7100   0
7150   0
7200   0
7250   0
7300   0
7350   0
7400   0
7450   0
7500   0
7550   0
7600   0
7650   0
7700   0
7750   0
7800   0
7850   0
7900   0
7950   0
8000   0
8050   0
8100   0
8150   0
8200   0
8250   0
8300   0
8350   0
8400   0
8450   0
8500   0
8550   0
8600   0
8650   0
8700   0
8750   0
8800   0
8850   0
8900   0
8950   0
9000   0
9050   0
9100   0
9150   0
9200   0
9250   0
9300   0
9350   0
 9400   0
 9450   0
 9500   0
 9550   0
 9600   0
 9650   0
 9700   0
 9750   0
 9800   0
 9850   0
 9900   0
 9950   0
10000   0
10050   0
10100   0
10150   0
10200   0
10250   0
10300   0
10350   0
10400   0
10450   0
10500   0
10550   0
10600   0
10650   0
10700   0
10750   0
10800   0
10850   0
10900   0
10950   0
11000   0
11050   0
11100   0
11150   0
11200   0
11250   0
11300   0
11350   0
11400   0
11450   0
11500   0
11550   0
11600   0
11650   0
11700   0
11750   0
11800   0
11850   0
11900   0
11950   0
12000   0
12050   0
12100   0
12150   0
12200   0
12250   0
12300   0
12350   0
12400   0
12450   0
12500   0
12550   0
12600   0
12650   0
12700   0
12750   0
12800   0
12850   0
12900   0
12950   0
13000   0
13050   0
13100   0
13150   0
13200   1

				
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