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                                          Dindar Öz
                                          MS Student
                                    Boğaziçi University
                          Department Of Computer Engineering


In this paper, a class of interconnection network topologies is explained. Orthogonal
binary vectors are main components of this connection model. Firstly, orthogonal graphs
is defined by two integers ,m , n , and a set Q it has 2m nodes and 2m - n links for each
mode defined in the set Q.The name “orthogonal” comes from the connection propeerty
of two nodes, which is explained later.


Consider we have p processors and p*p memory modules. Each processors has an id and
their acces rule is defined according to the that id. Think each memory module has an
index of i,j ,where Mi,j denotes memory module of ith row and jth column. Then the
acces rule of this system is defined as
                               Pk accesses Mij
                               if      k= i for all j ( By rows )
                               or      k= j for all i ( By columns

Here ,it can be easily seen that each processors has access to exactly 2p-1 memory
modules, and each memory modules ,except an the diagonal, are acessed by 2 processors.
We define this acces rule by vector operations to make calculations and analysis easier. If
we write the indices of modules and processors in binary mode then we get binary
vectors. Then the access rule becomes;

If we generalize the access rule by mode q then

The rule simply states that, the processor Px has access to the memory module My if its
index matches on n bits starting at the bit position q.


Let Ym denotes the set of all binary vectors of length m. So the cardinality of Ym is 2^m.
For example if m= 2 then Ym = { 00, 11, 01, 10 }. Let Q be the orderet set of
nonnegative integers smaller than m. For m=2 , Q = { 0, 1} . We define a new oparation
·   as below;
The · operator maps a vector from Ym to Ym by shifting the entering vector’s bits to
left by a given integer q . Let z be the special vector of length m which has starting n bits
as 1 and all other remaaining bits as 0 .

The inner product of mode q is defined as;

and if inner product is equal to 0 then two vectors are said to be orthogonal mode of q

The previous result appears also here. Two vectors are orthogonal if and only if they
match on n bits starting at bit position q.

An orthogonal graph G (n,m,Q * ) where Q * Í Q , is an undirected graph with 2m nodes.

Alink (edge) exists between two nodes y and y’ if and only if there exists a q Î Q * such
that y ^ q y’ . N(q) is defined as the number of nearest neighbours under modeq

Theorem 1 (Degree) .

The degree of an orthogonal graph G(n,m, Q * ) is given by
D = N( q1 ) + N( q2 ) + .... + N( q# Q * )+

     - N ( q1 , q2 ) – N ( q1 , q3 ) - .... N( q# Q * - 1 , q# Q * )

     - N( q1 , q2 ,... q# Q * )
where # Q * denotes rhe cardinality of Q * . Here the expression is acquired by summing

up all neighbours in all modes in Q * . İf we calculate the number of neigbours for a

single mode in Q * , it can be easily seen that

                                        N(q) = 2m - n where q Î Q *

For special set of Q * , there may be no neighbour that is connected by more than one
mode. This special set is called set of disjoint modes. In this case, since all N() functions
which takes more than          one modes as a parameter drops to zero. Then the degree
expression gets simpler;

                 D = ( 2m - n - 1 ) ´ # Q *       , if Q * is disjoint set of modes.

Theorem 2 ( Connectivity )

An orthogonal graph G (n,m, Q * ), where Q * = ( q0, q1,...ql ) , l £ m is of one component
( connected ) if and only if q0 · z n Ù q1 · z n Ù ......ql · z n = 0 .

This equation simply means that the zeros in the mask vectors of set Q * must cover all
the bitso of length m. If this coverage happens then it gets possible to go from any node
two any other node in the graph by changing 0 bits in some mask vector in Q * , which
implies connectivity.
Theorem 3 (Diameter)

Given a connected orthogonal graph G(n, m, Q * ) there exists a set Q |* Í Q * whose
cardinality is k such that

                   é m ù         ê m      ú ê mod(m - n + 1) ú
                   ê    ú£ k £ 2 ê        ú+ ê               ú
                   ê - nú
                    m            ê - n + 1ú ë
                                 ëm       û  ê  m- n         ú

In the best case every modes covers m-n different bits ( 0-bits covers, and there are m-n
bits in a mask vector). For all bits to be covered , m / (m-n) modes is used. So the left
side of the inequality is qlear. Consider the worst case. Every bit position canbe covered
by at most two different modes in Q * uniquely. If the third mode existed , then one of
those three modes would be obsolete, and therefore should not have been taken in
diameter calculation. So 2* (m/ (m-n)) is the worst case.


Omega graph is a subset of orthogonal graph with disjoint set of modes. It requires that
we choose m and n such that for some integer w ³ 2 , m = w (m-n) or m = wm/(w-1).
Q * is such that for all qi and qi + 1 in Q * qi + 1 - qi mod m = m - n and # Q * = w .

These graphs called w - graphs wG (n , m ) . 4 G (3 , 4) , 2 G ( 2 , 4) are some examples.
Note that m G (m-1 , m) is special graph called hypercube. ( See Figure 1)
                              Figure 1. 4 G( 3, 4), Hypercube


A special connection topology , orthogonal graph is introduced. Orthogonal
multiprocessing systems ( OMP ) provides p processors accesses to p*p memory
modules. The definition of orthogonal graphs is very general definition and based on
binary vector operatios. Access rule in orthogonal systems is defined by vector
orthogonality. By means of these rules , we can say that , there is no resource conflict in
orthogonal systems since system allows only one processors to access to a certain
memory modules in a certain time. Omega graphs , hyper cubes and MDA systems are all
subset of our general orthogonal network set.

1. “Definition and Analysis of a Class of Spanning Bus Orthogonal
Multiprocessing Systems” Isaac D.Scherson Department of Electrical
Engineering Princeton University Princeton New Jersey 08544

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