# Sequential Logic by ajizai

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```									Sequential Logic

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Introduction to Computer Architecture
Sequential Logic
 In many digital designs there is a need for logic circuits whose out-
puts depend not only on the present inputs but also on the past
history

 This is achieved by building memory-type circuits, which are able
to store information about the past history of the circuit, such
circuits are known as sequential logic circuit

Example
Red
Sequential traffic                                  Outputs
lights controller                Amber
Green

Clock

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Introduction to Computer Architecture
Sequential Logic
 The state of a system is its condition at a particular moment, described
by the value of its outputs or variables

 The traffic light controller requires four states, named S0, S1, S2, S3 ,

Red               Red, Amber

S0                  S1

S3                  S2

Amber              Green

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Introduction to Computer Architecture
Sequential Logic
Combinational vs. Sequential Logic

X1                             Z1     Network implemented from
X2                             Z2     switching elements or logic
-   Switching   -
gates. The presence of feedback
-   Network     -                distinguishes between sequential
-               -                and combinational networks.
Xn                             Zm

Combinational logic
no feedback among inputs and outputs
outputs are a pure function of the inputs
(A, B, Carry In) mapped into (Sum, Carry Out)

A
B           Full     Sum
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Introduction to Computer Architecture
Sequential Logic
Sequential logic

inputs and outputs overlap
outputs depend on inputs and the entire history of execution!

network typically has only a limited number of unique configurations
these are called states
e.g., traffic light controller sequences infinitely through four states

new component in sequential logic networks:
storage elements to remember the current state

output and new state is a function of the inputs and the old state
i.e., the fed back inputs are the state!

Synchronous systems
period reference signal, the clock, causes the storage elements to
accept new values and to change state

Asynchronous systems
no single indication of when to change state
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Introduction to Computer Architecture
Representations of a Digital Design

Truth Tables
tabulate all possible input combinations and their associated
output values

to form Sum and Carry                         Carry in to form Sum and
Carry Out
A   B   Sum   Carry                            A    B Cin     Sum Cout
0   0    0     0                               0    0 0        0   0
0   1    1     0                               0    0 1        1   0
1   0    1     0                               0    1 0        1   0
1   1    0     1                               0    1 1        0   1
1    0 0        1   0
1    0 1        0   1
1    1 0        0   1
NOTE: 1 plus 1 is 0 with a                         1    1 1        1   1
carry of 1 in binary

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Introduction to Computer Architecture
SR Latches with Control input
S and R are allowed to change the flip-flop only when C = 1.

If C=0, S and R can’t change output

S
Q

C

Q’
R                                                                            Function Table
Logic Diagram

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Introduction to Computer Architecture
D Latch
Want to get rid of the undesirable SR condition where both S and R are 1.

D
Q

C

Function Table
Q’

Logic Diagram

Also called a transparent latch
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Introduction to Computer Architecture
Graphic symbols for Latches

S                     S                                  D

R                     R                                  C

SR                    S’ R’                              D

Graphic Symbol for Latches

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Introduction to Computer Architecture
Other Flip-Flops
• Each flip-flop is made of interconnection of gates.

• The edge-triggered D flip-flop is the most efficient
flip-flop since it requires the least number of gates.

• Other flip-flops are made using the D flip-flop and
extra logic.

• Two flip-flops widely used are the JK and T flip-flop.

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Introduction to Computer Architecture
JK Flip-Flop
• Three flip-flop operations:
Set, Reset, Complement o
utput.

• JK performs all three

J

J                                                                     C

D              Q
K
K
CLK              C           Q’

Graphical Symbol

Circuit Diagram
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Introduction to Computer Architecture
JK Flip-Flop
D = JQ’ + K’Q

if J=1 , K=0 then D=Q’+Q=1
if J=0 , K=1 then D=0
if j =1 , K=1 then D = Q’

J

J                                                                        C

D              Q
K
K
CLK               C           Q’

Graphical Symbol

Circuit Diagram
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Introduction to Computer Architecture
T Flip-Flop
T (Toggle) flip-flop is a complementing one.

T flip-flop is obtained from a JK when inputs J and K are tied together.

J                                                                D                  Q
T                                          T

C
C                  Q’
K                          T

From D flip flop
From JK flip flop

C

Graphical symbol
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Introduction to Computer Architecture
T Flip-Flop
If T=0 ( J=K=0) output does not change.
If T=1 ( J=K=1) output is complemented.

A T flip-flop can also be made of D flip-flop and a XOR.

D = T XOR Q = TQ’ + T’Q

J                                                                D                  Q
T                                          T

C
C                  Q’
K                          T

From D flip flop
From JK flip flop

C

Graphical symbol
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Introduction to Computer Architecture
Characteristic Tables
• JK Flip-flop

•   J   K    Q(t+1)
•   0   0    Q(t)     No change
•   0   1    0        Reset
•   1   0    1        Set
•   1   1    Q’(t)    Complement

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Introduction to Computer Architecture
Characteristic Tables
• D Flip-flop

• D    Q(t+1)
• 0    0    Reset
• 1    1    Set

• T Flip-flop

• T    Q(t+1)
• 0    Q(t) No change
• 1    Q’(t) Complement

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Introduction to Computer Architecture
Registers
• Sequential circuits are classified based in their
function, e.g., registers.

• Register: A group of flip-flops each storing one
bit of information.

• Registers include flip-flops and gates: flip-flops h
old the information, gates control how the inform
ation is transferred to the register.

• Counter is a register that goes through a
predetermined sequence of states.
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Introduction to Computer Architecture
4-bit Register

Clear: Cleans the output to all 0’s.

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Introduction to Computer Architecture
1                 1

To fully synchronize the system                                                  I0
clock signals should arrive at the
same time at all flip-flops.                              1

Therefore we do not control the clock
by gates.                                                                        I1
1

I2

Load =0, register content does not change                  1

I3

1

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Introduction to Computer Architecture
Slower compared to parallel addition, but uses less equipment.

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Introduction to Computer Architecture

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Introduction to Computer Architecture
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Binary Ripple Counter
• Count-down counter: A binary counter with reverse count: Starts
from 15 goes down.

• In a count-down counter the least significant bit is complemented
with every count pulse. Any other bit is complemented if the previous
bit goes from 0 to 1.

• We can use the same counter design with negative edge flip-flops to
make a count-down flip-flop.

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Introduction to Computer Architecture
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BCD Ripple Counter
A BCD counter starts from 0 ends at 9.

0000         0001         0010             0011            0100

1001         1000         0111             0110            0101

State Diagram of a Decimal BCD-Counter

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Introduction to Computer Architecture
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Logic Diagram of BCD Ripple Counter
Q1 is applied to the C inputs of Q2 and Q8

Q2 is applied to the C input of Q4

J and K are connected to either 1 or flip-flop outputs

0000      0001       0010       0011          0100

1001       1000      0111       0110          0101

State Diagram of a Decimal BCD-Counter

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Logic Diagram of BCD Ripple Counter
Verification: Does the circuit follow the states?

Q1 is complemented with every count (J=K=1)

Q2 complements if Q1 goes from 1 to 0 and Q8 is 0

Q2 remains 0 if Q8 becomes 1

Q4 complements if Q2 goes from 1 to 0

Q8 remains 0 as long as Q2 or Q4 is 0
When Q2 and Q4 are 1, Q8 complements when Q1
goes from 1 to 0. Q8 clears and the next Q1 transition.

0000        0001         0010        0011           0100

1001         1000        0111        0110           0101

State Diagram of a Decimal BCD-Counter                                      25
Introduction to Computer Architecture
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Example : Traffic Light Controller

•Reset                          RED          S0 00
•S0

RED / YELLOW       S1 01
•S1         •S3

GREEN          S2 10
•S2

YELLOW
S3 11

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Introduction to Computer Architecture
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Example : Traffic Light Controller
State Transition Truth Table

S    Current         Next             Outputs
State           State
A      B       A’     B’     R      Y      G
S0   0      0       0      1      1      0      0
S1   0      1       1      0      1      1      0
S2   1      0       1      1      0      0      1
S3   1      1       0      0      0      1      0

A’=AB                B’=B

R=A                   Y=B                                        G=A.B

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Introduction to Computer Architecture

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