Poster

High Level Design using SyncCharts: a Case Study

Charles André – I3S Lab. – Nice-Sophia Antipolis

University/CNRS http://www.i3s.unice.fr



SyncCharts Tools

• A state-transition based model with

– Hierarchy

• Graphical Editor

– Concurrent evolutions • Compiler SyncCharts  Esterel

– Preemptions Encoder/Decoder • Simulation

• A mathematical semantics – Xes (interactive esterel simulator

– Synchronous process algebra

with source code debugging

• Fully compatible with the Esterel 0+-00-0+0

language • Formal verification

– Can use mixed description encoding decoding – Xeve (symbolic model-checker)

• Graphical: SyncCharts

• Textual: Esterel









encoding: {0,1} *  {-U, 0, +U} *

decoding: {-U, 0, +U} *  {0,1} *

k n Standard encoding:

Requirement 1 n  1: u

k 1

k

U In what follows: -U  n; 0  z; +U  p

0z 1  {n,p} alternately

Requirement 2 4 successive 0:



0000PzzV

n  4 :   u n

 0   u n1  0   u n2  0   u n3  0  

Parity Violation







Example: design of the encoder Simulation

SyncCharts-based Design

:Encoder





:PureEncoder :BackEnd

In:boo lean :FrontEnd Minu s



Bin Zero

Out:MZP •Decompose into interacting agents

Clk Plus



•Detector (4 consecutive 0’s)

•Parity manager

•Sequence generator

•Output manager

:PureEncoder

Bout

Bin Zero

:Detector :Decision

FourZeros



Even

Violation

Alternation Plus



•Tests of scenarios (Esterel studio)

:Parity :NonZero

Min us









behavior

•Prove safety properties









•Circuit optimization (if HW controller)

Performance

High-level behavioral description (e.g., the Encoder)

a syncChart

structural translation

Esterel program

Esterel’s compiler

Blif 105 states

SIS

an optimized circuit 35 states



As efficient as the hand-coded

Safety Properties solution









Property :

Requirement 1: Requirement 2: Encoder/Decoder:

At each instant : one and only one

k n

n  4 :

u

signal in {n,z,p} is emitted Beyond the sixth instant:

n  1: U

k 1

k   u n

 z   u n 1  z   u n  2  z   u n 3  z   Bout is identical to Bin, upto a

6 instant delay

Observer: An Esterel module

loop Observer: a flat syncChart = a FSM Observer: a syncChart with preemption Observer:

present (n and not z and not p)

or (not n and z and not p)

OBSERVER

or (not n and not z and p) O B S E R V E R _ R 2



6_stage_shift_register

else # z z z z

Violation



emit non_exclusive T o o M a n y Z p

end present Encoder

z

n Decoder

each tick p o r n Bin Bout









I3S Laboratory (UMR6070) BP121 – 06903 Sophia Antipolis cédex - FRANCE