Update on the Tracking
Chamber and Readout
Electronics
University of Houston
October 2, 2003
MECO collaboration meeting
Electronics update
• The short straw prototype has been upgraded and repaired:
– New flexible cables for anode signals and loose wires repaired
– ASD preamp board and shielding box completed;
– 32 channel anode board and 32 channel cathode board with adjustable
gain completed
– 32 channel timing output with ECL driver completed
• DAQ program and trigger system completed
• After 3 month of discussion and work with LBNL, we now have 28
ELEFANT chip samples (~200 channel).
• A 64-channel digitizer front -end system is under design.
Components selection is completed, FPGA simulation design is
completed, and board design begun.
• Alternative cathode strip designs are being considered.
• We have all licenses for CMOS mixed signal chip design, and we are
able to use MOSIS and Cadence.
E. Hungerford Update on the Tracking Chamber and Readout Electronics October 3, 2003 2
SP-II upgrade
• Redesign the connection and
protection for anode flex cable
• ASD shielding box is completed
• Prototype improved and repaired
• 32 channels of A and of T
electronics working
E. Hungerford Update on the Tracking Chamber and Readout Electronics October 3, 2003 3
MDAQ-2
Installed on a 2.4GHz Linux PC system, connected to a single
board computer (SBC) module, MVME-5100-0161, located in a 7-
slot-VME-mini-crate.
Wiener VC32 interface VME module connects to Wiener CC32
CAMAC controller
CODA system and VxWork software.
Real time
trigger interface
installed
LeCroy ADC
2249 run-control
test succeeded.
Events recorded
at rates up to a
few kHz.
E. Hungerford Update on the Tracking Chamber and Readout Electronics October 3, 2003 4
The induced charge distributions on the
pads are wider than expected
• The predicted distribution is a spread on ~3 pads. This is observed for
the distribution when horizontal to straw (Mathieson (NIM 227A, 1984).
• Perpendicular to the straw the charge spreads over 7strips
Induced charge with pads direction
Horizontal Percentage of total charge (%) 90
80
Horizontal to straw
70
60 Perpendicular to straw
50
40
Perpendicular 30
20
10
0
1 2 3 4 5 6 7
Pads number
E. Hungerford Update on the Tracking Chamber and Readout Electronics October 3, 2003 5
Two possible scheme of readout
• In order to reduce the channel number of readout pads if the Z
resolution is reduced (~1.5mm), two methods are considered.
• A highly segmented cathode pad readout was developed 12
years ago. With printed resistive ink on the pads, Z- resolution is
100um to 1000um corresponding to 1pC to 100fC anode charge.
• A chevron pad readout has also been investigated. The position
resolution is approximately the same.
• These methods can reduce the total channel number by 1/2
Chevron Pads Resistive straw & Pads Segmented pads
readout (1991)
12mm
E. Hungerford Update on the Tracking Chamber and Readout Electronics October 3, 2003 6
Digitizer front-end prototype System
• This system consists of 64 channels preamplifier boards, ADB boards, CMB board, and PC.
• 4 ADB boards, each one accepting signal from a 16-channel preamplifier board, are plugged into a
CMB board.
• A CMB board controls the whole system, collects data from Elefant chips, and sends them to a PC
thru a NI high speed DIO board.
• Preamplifier board design is done. The schematic file input for ADB is finished. FPGA and CPLD
design for CMB board is done and schematic design will start soon.
• This design will be reported On 2003 IEEE Nuclear Science Conference.
DAC
NI PCI-6534
Data
16k FIFO Transmitter
&
Command
Receiver
Shaper Gain Readout
(CPLD)
ASD Elefant Sequencer TXer
8
L.Conv
ADB
8x2 Controller
Hit point Trigger Clock
Multiplexer Decision 60MHz
(CPLD) 4
ADB CMB
external trigger input
E. Hungerford Update on the Tracking Chamber and Readout Electronics October 3, 2003 7
Programmable Logic Device
not A not B
A B
• PLD
D Q
– First Programmable Logic chip
– A set of fully connected macrocells, which are typically
comprised of some amount of combinatorial logic (AND
and OR gates, for example) and a flip-flop CLK
– Address decoder
• CPLD – Complex PLD
– Density increased, multiple PLD with additional
interconnection
– Signal delay is predictable and short
– More complicated logic design, high performance logic
design
• FPGA
– A large amount of macrocells (logic block), flexible
interconnection, programmable I/O block
– Flexible than CPLD
– register-heavy and pipelined applications, the fast
processing of data streams.
– In place of a processor-plus-software solution.
E. Hungerford Update on the Tracking Chamber and Readout Electronics October 3, 2003 8
What’s VHDL?
• Very High Speed Integrated Circuit Hardware Description Language
• Describe the structure and behavior of digital electronic hardware
designs
• IEEE Std 1076-1987 and 1076-1993
• Support top down, bottom up design methodology, like C language
VHDL Programming a
library ieee; out
use ieee.std_logic_1164.all;
b
entity plus2 is
port ( a, b : std_logic; Truth Table
out : std_logic); a b out
end plus2;
0 0 0
architecture a1 of plus2 is
begin 0 1 1
out to do Logic FIFO
initialize, -- 1 => write start of data frame
readhitmap, -- 1 => read hitmap from a ADB
see if
asserthitmap, -- 1 =>Trigger hitmap is empty
L1_Accept 16
writeADBnum,-- 1 => write ADB, elefant addrs.
Decision Making
=> write hitmap
writehitmap, -- 1 Logic Control
Trigger
readtag, -- 1 => readout tag
readcounter, -- 1 => readout counter WR Buf
pattern RD Buf
writechannelnum, -- 1 => write channel number
readstart, -- 1 => readout data
readincword, -- n
nextchannel, -- 1 => increase channel number
16
nextelefant, -- 1 => increase elefant number
incbuffrd); -- 1 => increase buff_rd pointer 2 2 8
scintillator Wr_addr Rd_addr Data from Elefant
E. Hungerford Update on the Tracking Chamber and Readout Electronics October 3, 2003 14
Waveform of ADBC
• FPGA is designed using VHDL.
• We select Xilinx Spartan-II product as the device.
• All the simulation is done in Xilinx Integrated Development Environment.
The waveform is shown in the following window.
– This waveform matches the waveform of Elefant chip. It makes sure that FPGA will
work functionally.
E. Hungerford Update on the Tracking Chamber and Readout Electronics October 3, 2003 15
Waveform of Data Transmitter (TXer)
• TXer is designed using VHDL and implemented in a Xilinx CPLD.
– It transfer data from FIFO to PC through a parallel data bus with the speed up to 20MHz.
– It also receive command from PC and does the appropriate configuration through the serial
bus between the CMB board and ADB boards.
• This transceiver design is done. The following window shows the simulation
waveform. It matches the NI high speed DIO input timing waveform and TI FIFO
output waveform.
E. Hungerford Update on the Tracking Chamber and Readout Electronics October 3, 2003 16
October 2, 2003
MECO collaboration meeting