Applications
Engineering
Doing what we said we would do…
or
Why customers come to us first...
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Stability in High Speed LDO Regulators
An overview of the design relating to low drop out (LDO) regulators.
Design guidelines given for the selection of components based on
performance and stability requirements.
Typical questions that generally need or get asked:
What are my input and output requirements?
Do I have transient response and magnitude requirements?
Can I use a regulator or do I need a controller?
What do I need for output capacitors?
If my regulator is oscillating, what do I change to stop it?
My regulator response is slow, so how do I speed it up without causing it to
oscillate?
The following slides introduce the different components
and block diagrams for LDO regulators.
ON Semiconductor Page 5
Example LDO Controller Block Diagram
Block diagram showing dual
LDO controller.
Startup, Over current, and
Shutdown functions.
Band Gap reference for
setting DC output voltage.
Error Amplifier for controlling
external N-channel
FET.
Second channel FET turn on
for shorting input to output.
MC33567 Dual LDO Controller
ON Semiconductor Page 6
LDO Regulator Block Diagram
VR Error Amplifier Output Driver & Load
Reference + V1
Input A(s) Driver Supply
-
Output
B(s)
Load
Feedback Divider
V2 VO
C(s)
ON Semiconductor Page 7
LDO Regulator Schematic
VCC
LDO Controller
Driver
Ro Q1
V2 R1 VO
V1
Load
Ca Cb Co
Rl
U1
VR
Error Amp
Rs
R2
Vref Feedback
Output
Reference Input Divider Capacitor
ON Semiconductor Page 8
Simplified Block Diagram and Transfer Function
VR V1 VO H(s) VR
A(s) B(s)
+
-
V2
C(s)
VO 1 1 N(s)
H(s) AV
VR C(s) 1 1 D(s)
A(s) B(s) C(s)
1 R1
AV 1 or 1
C(s) R2 AC
DC
ON Semiconductor Page 9
Error Amplifier Detail - A(s)
Ao ωa 1
A(s)
s ω ω 1
Error Amplifier
VR
1 s s s 1
o 1 ω1
+
A(s) V1
- Ao - error amp open loop gain
ωo - dominant error amp pole
V2
V1 A(s) (VR - V2)
ω1 - secondary error amp pole
ωa - error amp gain bandwidth
Open loop gain greater than 60dB (for less than 0.1% DC output error).
Dominant pole usually set for device, although some devices allow adjusting
via compensation pin.
Gain bandwidth usually specified: Ao fo
Solve for gain bandwidth pole: ωa 2πAo fo
Error amp designed to have secondary pole greater than gain bandwidth and
usually NOT specified. If not, let: ω1 ωa
For stability analysis, assume frequency range: ωo ω ω1
ON Semiconductor Page 10
Feedback Divider Detail - C(s)
R1
V2 VO C
Cb 1 1 sCbR1 VO sCaRT VR AV
V2
Ca R2
AV 1 sCa Cb RT
VR D
R1
AV 1 RT Ra Rb
R2
Want to design divider for DC gain of Av and AC gain of 1.
E
Want V1 independent on reference input, Vr.
Need AC gain of 1 for frequencies greater than low frequency pole of error
amp.
LDO controller with fixed output voltage has divider built-in and optimized. F
If adding to existing internal divider, follow same guidelines.
Use following design guidelines to obtain these result.
G
Title: Circuit1
ON Semiconductor Page 11
Proj ect 1
Feedback Divider Detail - C(s) - Continued
Divider Design Guidelines:
VO AV R1 100
AV DC R1 R2
A V 1 Cb
VR 10ωaCa ωaR2
VO - output voltage (known).
VR - reference voltage (known).
AV - DC gain (solve for).
ωa - gain bandwidth (from error amp analysis).
Ca - error amp input capacitance (use 10pf if not specified).
- first divider resistor (solve for).
R1
- second divider resistor (solve for).
R2 - divider compensation capacitor (solve for).
Cb
Final solution for divider transfer function - C(s):
V2 C(s) VO 1
C(s) ( DC) 1( AC)
AV
ON Semiconductor Page 12
Output Driver and Load Detail - B(s)
VCC
B(s)
s ω 1
c
2 1
1 1 1 β
Cgd
s β
s 1
1
ωf
Ro ωc ωf C
gm Rs ωc gm Rs
V1
1 1 Cgd
ωc
Cgs
gm ωf Ci Cgs Cgd β
Error Amp Rs Co
D
Ci Ro Cgs Cgd
Output
Driver
VO
Co Transfer function for B(s) shown mainly for
Output Rl
Capacitor reference.
E
Rs
Load Too complicated to deal with directly.
Will develop design guidelines combining
this withF other functions to develop overall
VO B(s) V1 closed loop transfer function.
ON Semiconductor Page 13
G
LDO Closed Loop Transfer Function - H(s)
Combining A(s), B(s), and C(s) into the
N(s) N(s)
expression for H(s) yields the following, H(s) AV AV 1, AC
which is ONLY shown for reference. D(s) D(s)
s
N(s) 1
ωc
s4 1 s3 1 1 β s3 1
β 1 β
ω1 ωa ωc ωf gm Rs ω1 ωa ωc gm Rs ωf ωa ωc ωf
gm Rs
D(s)
s2 s2 1 1 β 1 1
1 gm Rs ωf s ωa ωc 1
ω1 ωa ωa ωc
The expression for H(s) contains 4 poles and one zero.
It is far too complicated to work from directly.
Stable response requires poles to be in left hand plane.
Analyze pole locations in terms of circuit parameters to make poles be
critically or over-damped (no gain peaking in closed loop response).
ON Semiconductor Page 14
LDO Closed Loop Transfer Function - H(s) - Continued
LDO Regulator Stability Design Guidelines:
1
1 1
1
1
Rs
3 ωp 1
ωp ωa gm
ω1 ωf 20 1
3 ωp
ωa gm
1 1 1 1 1
Co Rs 5 τ
ωc ω a ωp ωp gm Rs ωa
ωp - secondary pole for open loop (solve for).
ω1 - error amp second pole (known or assumed).
ωf - driver pole frequency (if driver built in, let ωp ω1
).
ωa - gain bandwidth (from error amp analysis).
gm - maximum driver transconductance gain (if driver built in,
then 1 is the output impedance of the regulator).
gm
- ESR resistance of output capacitor (solve for).
Rs
- output capacitor (solve for).
Co
- overall loop response time (solve for).
τ
ON Semiconductor Page 15
LDO Closed Loop Stability Analysis Conclusion
Following design guidelines for voltage divider and stability will yield stable
LDO regulator.
Design can be optimized for speed with stable operation.
Little or no overshoot ringing for output transient currents.
Design guidelines can be used in reverse to find error amp gain bandwidth if
output capacitor and ESR given.
Guidelines show designer which parameters to change to improve stability
and/or loop response time for design and/or actual circuits.
Guidelines help designer to select proper controller/driver for application.
No need to solve for poles/zeros or graphically analyze Bode plots for unity
gain phase margins.
All conditional guidelines must be met for stability.
Guidelines do not guarantee perfect operation due to unknown parasitics and
unknowns.
Still need to simulate and prototype final design.
Following is a design example demonstrating use of guidelines.
ON Semiconductor Page 16
Example Design using Guidelines
Example LDO regulator design
12V 3.3V demonstrating design guidelines.
MTD3055
1/2-MC33567
NFET
Following graphs show closed loop
LDO Controller
response for changes in circuit.
1.8V
Output
Circuit at left shows components
-
Internal used for examples.
Divider Output
Load
Error Amp
+ Cap
Design guidelines valid for other
1.25V Ref circuit configurations as well.
Gnd
Gnd
These include PFET controllers and
bipolar (NPN and PNP).
Circuit parameters: Output stability necessary for steady
MC33567 - 5MHz gain bandwidth
50 ohm output impedance state and transient output currents.
Optimized internal divider
MTD3055 - 7 mhos transconductance gain
2200 pf input capacitance
Load - 0.9A (2 ohms)
ON Semiconductor Page 17
Frequency Response Analysis
ON Semiconductor Page 18
Waveform for varying ESR of output capacitor.
Rs = 30 milliohms appears optimal.
(Co = 10,000uF).
Changing the ESR (Rs) of the output capacitor beyond the recommended upper
and lower limits tends towards instability (gain peaking).
Making the ESR larger speeds up the closed loop response but may increase the
magnitude of the initial transient response due to fast changes in output current.
ON Semiconductor Page 19
Waveform for varying output capacitance.
Co > 100uF yields same response.
(Rs = 30 milliohms)
Output capacitance less than lower limit tends towards instability (gain peaking).
Output capacitance greater than lower limit yield same result (choose type and value
to meet ESR requirements).
ON Semiconductor Page 20
Waveform for changing output driver - gm and Ci.
MTD3055: gm = 7, Ci = 2200pf
MTD3302: gm = 28, Ci = 6600pf
(Co = 500uF, Rs = 30mohm)
System optimized for using MTD3055.
Changing output driver FET can impact loop stability (as shown for this example).
If drivers need to be interchangeable, design for higher gain device (gm) and others
will be stable (although loop will be slower).
ON Semiconductor Page 21
Waveform for varying gain bandwidth of controller
Designed for (Af)o = 5MHz.
(MTD3055, Co=500uF, Rs=30mohm)
System optimized for gain bandwidth of MC33567 (5MHz).
Making gain bandwidth higher tends towards instability (gain peaking).
If designing with error amp compensation, can achieve stability by varying gain
bandwidth.
ON Semiconductor Page 22
Transient Response in Stable LDO regulators
Transient response for changes in output currents becomes straight forward if LDO
regulator closed loop response is stable.
Magnitude of transient depends on rate/magnitude of change and ESR of output
capacitor.
Worse case is step change in output current ( ).
ΔIO
Time for transient to return
Typical Transient Response
to nominal output is
proportional to closed loop
response time.
ΔIO
Following is example of IO
previous regulator design ΔVO ΔIO Rs
transient response for stable
and “less than stable”
conditions. VO
ΔVO
ts 5 τ
ON Semiconductor Page 23
Transient Response Example for Previous Design
τ 0.3sec (for optimized design)
ts 1.5 sec (from graph)
MTD3055: gm = 7, Ci = 2200pf
(Co = 500uF, Rs = 30mohm)
ΔIO 1A Rs 30m
ΔVO 30mV (from graph)
From graph, optimized design is critically damped.
Over optimized designs slower but stable.
Designs outside of guidelines tend to oscillate.
Response time and transient amplitude agree with guidelines.
ON Semiconductor Page 24
Presentation Summary
Specify design output voltage and current (steady state and transient).
Follow design guidelines.
Select controller best suited.
Simulate and prototype circuit.
Adjust components for optimal performance.
ON Semiconductor Page 25
MicroIntegrationTM
A small-package-scale integration effort that combines multiple discrete, logic
and MOS devices, which may include passive devices (resistors, capacitors,
inductors).
Reduces the total number of discrete & passive components thereby simplifying
and or reducing:
- System Cost - Procurement activity
- Design Complexity - Overall size
- Insertion cost - Component count
- Performance inconsistencies - Solder reliability issues
To Turn Into
This… This…
ON Semiconductor Page 26
Customer benefits
Lower manufacturing costs Improve marketplace opportunities
- Assembly line setup time - Performance improvement
- Capital equipment utilization - Size reduction
- Equipment costs - Reliability improvements
- Assembled wrong part ( yield) - Component interaction reduction
- Reduced insertion costs
Reduce overhead costs
Lower materials costs
- Inventory Purchase Management
- Component costs
- Floor and shelf space
- Board/substrate costs
- Inspection
- Eliminate parts (eg.: shields)
- Component Obsolescence
ON Semiconductor Page 27
Three types of products comprise the portfolio
Transient Protection Arrays Filter circuits
+Vcc
I/O 1
I/O 2
Drive Circuits
ON Semiconductor Page 28
MicroIntegrationTM Markets
Automotive
– 42/14v systems, in-car entertainment systems
Computing
– Power Supplies, Laptop, PC/ MTB PC, Server/ MTB Server, Work Station, Main Frame, Mid-range,
Storage, Disk Drives, Peripherals, Printers, Monitors, Scanners
Consumer
– Power Supplies, Set-Top Boxes, Game Consoles, Smartcards, MP3s, DVDs, VCRs, Camcorders,
Digital Cameras, Appliances, CD/ DVD Players, Handheld Game Boys
Wireless & Portable
– Power Supplies/chargers, Mobile Phones, Cordless Phones, Pagers, HH PC/PDA,Smartcards,.
ON Semiconductor Page 29
Transient Voltage Suppression
(TVS)
Transient Protection Applications
IC Protection
Input I/O IC Card
voltage
Input
Connector
ON Semiconductor Page 31
Filters
Low Pass Pi filter with TVS Protection
Transient Protection diodes
0
3
Attenuation 6
9
12
15
18
21
24
27
30
1 10 100 1000 3,000
Defines Cut off frequency Frequency(MHz)
ON Semiconductor Page 33
Filter Circuits
#6 #5 #4
R
#1 #3
R R
ON Semiconductor Page 34
Drive Circuits
Drive Circuits
ON Semiconductor Page 36
Charge Controller Solution
Analog Device
MicroIntegrationTM MC33340, MC33342
Battery Fast Charge
Controllers
ON Semiconductor Page 37
Today’s Solution For Lithium-Ion Battery Management
ON Semiconductor Page 38
Power Sequencer
Application: Market Segment:
3.3V/1.8V Power Sequence Computing
End Products:
Mother Board
ON Semiconductor Page 39
Lithium Battery Driver
Simulates
the battery.
Q4 D1
Q2SA1182 MBR130P R8
470k
Battery V R3
10k
R6
7.5
V C2
22pf
230k R7
charge
4
Q2SD1819 3
V+
V5 +
Q5
R1 1
4.0Vdc 10K OUT
U1A 2
V-
Q1 LM324/MC - V7
2.2k Q2SD1819 9V
11
R2 Q2 R11
IC control V
D12
D1N5231
V 2N7002LT1 10k
R10
R9 47k
330
V6
0.3Vdc
0
Simulates 12 ma load
for IC supply current.
Application: Market Segment:
Lithium Battery Driver Wireless,Consumer
End Products:
Hand Helds
ON Semiconductor Page 40
Foldback Current Limiter
9V
R9 1k R1 10
C1 R3 10K
1uf
D3 D2
D1N4148 D1N4148
Q1
Q2SA1162
R10
1k Q2
Q2SA1162
R11 R2
4.3K 43k
Output
2
R12
Enable 10K Q3 D4
Q2SC2712 SMBJ10
1
0
Application: Market Segment:
Over Current Protection Consumer
End Products:
Set Top Box- 3 per box.
ON Semiconductor Page 41
uP to FET Driver - Automotive
12 V Bat
R7
3.3v Q5
1k
Q2N2907
R6
R4 1k
1k R8
Q3
R5 R10
1k
1k
1k
R1
Q1
Q2N2222 FET
R9 input
uP 1k
Q2N2222 1k
input 1k
Q4
R2
R3 Q2N2222
1k
0
Application: Market Segment:
Bias Driver Circuit Automotive
End Products:
Engine Control Module Title
Size Document Number
A
Date: Friday , October 26, 2001 Shee
ON Semiconductor Page 42
MicroIntegrationTM Packages
MicroLeadless™
ON Semiconductor Page 43
MicroLeadless™ Series
0402 Diode Package 04025 Transistor Package
.040 x .020 .040 x .025
0808 Multilead Package
.080 x .080
ON Semiconductor Page 44
MicroLeadless™ Package Platform
ON Semiconductor Page 45
Flip chip model vs MicroLeadlessTM model
Bump inductance
Need library for
parasitics
Flip chip
Bump
inductance
Bonding inductance
Need library for
parasitics
MicroLeadlessTM
Ground
inductance
ON Semiconductor Page 46
Bumped flip chip S21 vs frequency
ON Semiconductor Page 47
MicroLeadlessTM S21 vs frequency
ON Semiconductor Page 48
Alex Lara
Applications Engineer
• BSEE from University of Guadalajara
• 5 years experience in applications
• Motorola, ON Semiconductor
• Engineering Lab Manager
• Multiple articles and application notes
ON Semiconductor Page 49
STANDARD DESCRIPTIVE JOB TITLE FOR AN APPLICATIONS
ENGINEER WITHIN THE SEMICONDUCTOR MARKET:
Develop new product ideas and specifications; build hardware/software prototypes
to verify new product feasibility; design and build new product evaluation and demo
boards; develop SPICE macro models and perform system simulations of new
products and applications; assist in evaluating and debugging new products;
evaluate and build comparative matrices of Competitive products; generate product
briefs, data sheets and application notes; conduct on-site design programs of new
products with market leading Alpha site companies; and interface with customers
and sales staff and provide technical training to Sales and FAE's.
Applications Engineering Key Activities
• Develop new applications concepts
• New designs implementation
• Technical Reports
• Simulation of applications circuits
• Design-ins
• Applications Notes Development
• Troubleshooting Customer Application needs
• SPICE simulations Development
ON Semiconductor Page 50
ON
Semiconduct
or
Universal
Serial Bus
ON Semiconductor Applications Engineerin
Activities for USB Port Applications
ON Semiconductor Page 51
Background
USB, or Universal Serial Bus, is a peripheral bus connectivity standard which was conceived, developed and is supported by a
group of leading companies in the computer and telecommunication industries – Compaq, DEC, IBM, Intel, Microsoft, NEC and
Northern Telecom. The current standard published and implemented on most of the USB devices is version 1.1, nevertheless,
the good news is, USB is getting even faster, USB 2.0 promises even higher data transfer rates, up to 480 Mbps. The higher
bandwidth of USB 2.0 will allow high performance peripherals, such as monitors, video conferencing cameras, next-generation
printers, and faster storage devices to be easily connected to the computer via USB. The higher data rate of USB 2.0 will also
open up the possibilities of new and exciting peripherals. USB 2.0 will be a significant step towards providing additional I/O
bandwidth and broadening the range of peripherals that may be attached to the PC.
USB 2.0 is expected to be both forward and backward compatible with USB 1.1. Existing USB peripherals will operate with no
change in a USB 2.0 system. Devices such as mice, keyboards and game pads, will not require the additional performance that
USB 2.0 offers and will operate as USB 1.1 devices. All USB devices are expected to co-exist in a USB 2.0 system. The higher
speed of USB 2.0 will greatly broaden the range of peripherals that may be attached to the PC. This increased performance will
also allow a greater number of USB devices to share the available bus bandwidth, up to the architectural limits of USB.
USB 1.1 devices operate at two different levels of speed:
• Low speed, 1.8Mb/s equivalent to 900KHz (ENCODE, NRZI – Non Return Zero Inverter)
• Full speed, 12Mb/s equivalent to 6MHz (ENCODE, NRZI – Non Return Zero Inverter)
USB 2.0 devices operate are compatible to operate at three different levels of speed:
• Low speed, 1.8Mb/s equivalent to 900KHz (ENCODE, NRZI – Non Return Zero Inverter)
• Full speed, 12Mb/s equivalent to 6MHz (ENCODE, NRZI – Non Return Zero Inverter)
• High speed, 480Mb/s equivalent to 240MHz (ENCODE, NRZI – Non Return Zero Inverter)
ON Semiconductor Page 52
USB Connectivity
USB allows for multiple peripheral connectivity with one (1) Host 1 PC.
Host PC-USB Hub Connection
PDAs
Cell
Phones
D. Cameras
Add other HUBs
Scanners Printers
ON Semiconductor Page 53
USB Opportunities Areas
1) ESD Protection and surge protection
• Devices must comply with the IEC 61000-4-2
USB Device/Circuit/Component • Comply with Telcordia (formerly Bellcore) GR1089
on Surge 8x20usec waveform
Protection • USB 2.0 now requires Transmission Speeds up to
480Mbits/sec (240MHz), that forces to get lower
capacitances (<5pF)
USB Power Management for 2) Power Management
• 5V – 3.3V Regulators
Host and Peripherals • Features
• Power switch (pending to research)
3) EMI Filtering / Termination – Detection
USB Signal Integrity • Pi Filters (RC), T Filters (LC)
• Pull up & Pull down resistors for speed detection
(Rpu, Rpd)
• Impedance matching resistors (Zhsdrv)
ON Semiconductor Page 54
USB ESD Applications
Considerations for the USB ESD and TVS Protection
• IEC 61000-4-2 Contact and Air Discharge compliance for ESD
Protection.
• Obtaining the lowest insertion loss in the transmission line over a
specific operating bandwidth.
• Lower capacitances (less than 5pF) to support USB 2.0
transmission speeds up to 480Mbits/sec (240MHz).
[example… ESD/TVS from connection your PDA to your computer]
ON Semiconductor Page 55
USB ESD Applications (cont’d)
Typical USB Application
HOST Dual USB port D. Cameras
PDAs
PC protection
Printers
Scanners
etc.
Single USB
port protection
ON Semiconductor Page 56
USB ESD Applications (cont’d)
Compliance with IEC 61000–4–2, ESD International Standard
This International Standard relates to the immunity requirements and test methods for electrical and electronic
equipment subjected to static electricity discharges, from operators directly, and to adjacent objects. It
additionally defines ranges of test levels which relate to different environmental and installation conditions and
establishes test procedures. The object of this standard is to establish a common and reproducible basis for
evaluating the performance of electrical and electronic equipment when subjected to electrostatic discharges.
In addition, it includes electrostatic discharges which may occur from personnel to objects near vital equipment.
IEC 61000-4-2 Test Levels
This figure shows a real
8KV contact waveform taken
from the ESD generator.
This figure shows how the TVS
clamps the ESD condition from 8KV
to 8.7V, this is the way in which
protection against ESD conditions is
achieved by using TVS
ON Semiconductor Page 57
USB ESD Applications (cont’d)
Low capacitance (less than 5pf) for High speed I/O Data lines (USB 2.0)
“Low capacitance (< 5.0 pf)” is one of the most important characteristics that any device intended to be used in USB applications
must have in order to minimize the signal attenuation at high speed data rate (480 Mbs, USB 2.0). This characteristic is critical,
otherwise, the functionality of the USB system could be affected dramatically during high speed operation. Actually, the USB2.0
spec establishes that the capacitance between I/O data lines lines must no be higher than 5pf.
Theoretical principle used to
Simplified Junction
Junction capacitance Model predict the capacitance between
capacitance Model
I/O lines for the NUP4201DR2
device
Real Lab measurements
The total devices characterized showed
an average capacitance value of around
4.45 pf between I/O lines which
C=4.52pf
complies with the USB 2.0 specification
(5.0 pf maximum) and reflects the results
obtained from the pspice model.
ON Semiconductor Page 58
USB EMI Filtering/Termination
EMI Filtering for USB 2.0 Applications.
For USB 2.0 applications, the usage of common mode choke inductors is very common for EMI filtering
purposes since no extra capacitance is added between the I/O data lines.
Upstream Downstream
Common mode
choke
inductors
ON Semiconductor Page 59
USB EMI Filtering/Termination
EMI Filtering for USB 2.0 Applications.
The equivalent PSPICE circuit for a TDK Choke model ACM2012-900-2P is shown below and also, its
configurations for common and differential mode operation:
1
L1
2 1
L1_3
2
3.1n 3.1n
Common Mode C1 C2 C1_3
0.84p 0.02p 0.84p
R4 45 R3 R1 R2 R1_3 R3_4
Input1 Output1
0.065 14 880 14 0.065
V1 = 0 V4 V
R5 V
V2 = 300mV 45
TD = R12 C12 TX1 C12_2 R12_2
TR = 500ps 1G 0.95p 0.95p 1G
TF = 500ps R7
PW = 1.58ns R6 45 R3_2 R1_2 R2_2 R1_4 R3_3 45
PER = 4.1666ns 0
880
0.065 14 14 0.065
C1_2 C2_2 C1_4
0.84p 0.02p 0.84p
L1_2 L1_4
1 2 1 2
L1
3.1n L1_3
3.1n
1 2 1 2
3.1n 3.1n
Differential Mode C1 C2 C1_3
0.84p 0.02p 0.84p
R4 45 R3 R1 R2 R1_3 R3_4
Input1 Output1
0.065 14 880 14 0.065
V1 = 0 V4 V
R5 V
V2 = 300mV 45
TD = R12 C12 TX1 C12_2 R12_2
TR = 500ps 1G 0.95p 0.95p 1G
TF = 500ps R7
PW = 1.58ns R6 45 R3_2 R1_2 R2_2 R1_4 R3_3 45
PER = 4.1666ns 0
880
0.065 14 14 0.065
C1_2 C2_2 C1_4
0.84p 0.02p 0.84p
L1_2 L1_4
1 2 1 2
3.1n 3.1n
ON Semiconductor Page 60
USB EMI Filtering/Termination
EMI Filtering for USB 2.0 Applications.
Common and Differential mode response of the TDK Choke model ACM2012-900-2P:
0
Common Mode.
In common mode operation, the Choke
will have very high attenuation and will
- 10 not allow the noise to go into the
system. As shown in the graph
(Common Mode), it starts having
high attenuation (-10dB or higher) when
- 20 the frequency is around 50MHz.shows a
high loss characteristics.
- 30
1 . 0 MHz 1 0 MHz 1 0 0 MHz 1 . 0 GHz 1 0 GHz
2 0 * L OG1 0 ( V( R5 : 2 ) / V( R4 : 2 ) )
Fr e q u e n c y
0
Differential Mode.
In differential mode operation, the choke
will not have high attenuation unless the
-5
noise signal is very high frequency
(5GHz or higher). As shown in the graph,
it starts having high attenuation (-10dB or
- 10
higher) when the frequency is around
5GHz.
- 15
1 . 0 MHz 1 0 MHz 1 0 0 MHz 1 . 0 GHz 1 0 GHz
2 0 * L OG1 0 ( V( R5 : 2 ) / V( R4 : 2 ) )
Fr e q u e n c y
ON Semiconductor Page 61
USB EMI Filtering/Termination
EMI Filtering for USB 2.0 Applications.
L1 L1_3
1 2 1 2
3.1n 3.1n
C1 C2 C1_3
0.84p 0.02p 0.84p
R4 45 R3 R1 R2 R1_3 R3_4
Input1 Output1
V1 = 0
V2 = 100mV
TD =
V2
V+
0.065 14 880 14 0.065
R5
45
V+ V1= USB 2.0 signal applied
TR = 10ps TX1
TF = 10ps
PW = 0.09ns
PER = 0.2ns
R12
1G
C12
0.95p
C12_2
0.95p
R12_2
1G
(240MHz)
V1 = 0
V2 = 300mV
TD =
V1
0
V2 = Noise signal
TR = 500ps
TF = 500ps
PW = 1.583ns
R6 45 R3_2 R1_2 R2_2 R1_4 R3_3
R7
45 (5GHz)
PER = 4.166ns
880
0.065 14 14 0.065
V- V-
C1_2 C2_2 C1_4
0.84p 0.02p 0.84p
L1_2 L1_4
1 2 1 2
3.1n 3.1n
2 0 0 mV
TDK Choke
Filtering response
1 5 0 mV (Differential mode)
1 0 0 mV
5 0 mV
0V
0s 1ns 2ns 3ns 4ns 5ns 6ns 7ns 8ns 9ns 10ns
V( R5 : 2 , R7 : 1 ) V( R4 : 2 , R6 : 2 )
T i me
ON Semiconductor Page 62
USB EMI Filtering/Termination
EMI Filtering for USB 2.0 Applications.
R3 45 R2 7 L2 7nH
1 2
V1 = 0 V1
V+ V1= USB 2.0 signal applied
V2 = 100mV R6
TD =
TR = 10ps
45
V+
(240MHz)
TF = 10ps C1 C2
PW = 90ps
PER = 200ps
3pf 3pf V2 = Noise signal
(5GHz)
V1 = 0 V2 0
V2 = 300mV C3 C4
TD = 3pf 3pf R4
TR = 500ps 45
TF = 500ps
PW = 1.58ns
PER = 4.166ns R5 45 R1 7 L1 7nH
V-
1 2
V-
2 0 0 mV
LC Filter,
Filtering response
1 5 0 mV (Differential mode)
1 0 0 mV
5 0 mV
0V
0s 1ns 2ns 3ns 4ns 5ns 6ns 7ns 8ns 9ns 10ns
V( R3 : 1 , R5 : 2 ) V( R6 : 2 , R4 : 1 )
T i me
ON Semiconductor Page 63
CONCLUSION:
• Applications Engineers are key in the definition and understanding of the guide lines
for New Products Development.
• Applications Engineers are key to increase the business of the companies because
most of the time they represent an added value for the customers which allows to
create a relation-ship between the company and the designers, thereby, creation of
new business opportunities.
• Applications Engineers are key to promote the companies’ products by educating
the sales department, supporting trade-shows and developing demo-kits.
• Applications Engineers are key to win design-ins because they can help in
suggesting the most proper device for any particular application and also they can
show and explain the capability of the companies’ products.
ON Semiconductor Page 64
ON Semiconductor Page 65