IC_Transistors_Resistors by xiaoyounan

VIEWS: 3 PAGES: 17

									IC Transistors and Resistors



    I.     Resistors
    II.    Bipolar Transistors
    III.   MOS
    IV.    DMOS



                                 Chris Kendrick
                                 Jan. 29, 2003
                                 BiCMOS Design
     Resistor Voltage Coefficient




Figure 1 A p type region in an n type tub forms the resistor.




     http://adev.onsemi.com/knowledge_net/index.html
                                   Resistor Voltage Coefficient
                                      % Change PHV Resistance vs. Body Bias

                      25.00%


                                    30x300
% Change Resistance




                      20.00%
                                    12x300
                                    6x300
                      15.00%        12x120
                                    12x30


                      10.00%


                                                                              VApplied = 5V
                      5.00%



                      0.00%
                               0      10          20          30          40                  50

                                                  Body Bias (V)
                                Resistor Temperature Coefficient

                                           PHV Resistance vs. Temperature

                                       80.0%


                                       60.0%            VBody = 5V
% Change in Resistance




                                       40.0%

                                                                            30x300
                                       20.0%                                12x300
                                                                            6x300

                                        0.0%
                         -100    -50            0          50         100   150      200

                                       -20.0%


                                       -40.0%
                                                    Temperature (C)
Resistor Voltage limits

        • The maximum resistor voltage is NOT
        defined by the tub it’s sitting in!


              Diffusion            Breakdown (V)
      Buried Layer – Isolation           95
      PWell – Epi                        95
      PHV – Epi                          60
      NHV - PWell                        43
      PSD - Epi                          30
      NSD - PWell                        17.5
      NSD – PHV                          12
      NSD – PSD (in PWell)               5.8


        • The voltage rating of the tub determines
        the spacing of PHV to Epi
   Lateral PNP Saturation




http://adev.onsemi.com/knowledge_net/index.html
                     Low current NPN/PNP biasing

      • What’s the lowest current bipolars can be biased at?

                                                      Lateral PNP
  C              E                              B


      FOX                 FOX             FOX



                 PSD Epi               PHV      NSD
PSD PHV   PHV                    PSD

                     Substrate
          PNP (PHV/Epi - Emitter 21x 21
               UDR) cross-section




                                                      ICmin ~ 5uA
                            Low current NPN/PNP biasing

            • What’s the lowest current bipolars can be biased at?

                                                              Vertical PNP
      C             B          E                        C


           FOX                                 FOX
            PWell
                                   PSD
PSD       PHV    NSD    NHV Epi          NSD            PHV
                                                  PSD

                           Substrate
                PNPV (PSD/NHV - Emitter 28 x 28
                      UDR) cross-section




                                                              ICmin ~ 20nA
                          Low current NPN/PNP biasing

        • What’s the lowest current bipolars can be biased at?

                                                             NPN
                E                        B           C


       FOX                 FOX                 FOX
        PWell

                    NSD                              NSD
PSD   PHV                 Epi      PSD   PHV

                       Substrate
             NPN (NSD/PWell - Emitter 21 x 21
             UDR) cross-section




                                                           ICmin ~ 20nA
           MOS Safe Operating Area
• Hot carrier injection limits NMOS operating voltage
                                                   S                G                   D
                                                           Poly

          BPSG                                                                                      BPSG
          FOX                                                                                       FOX

                                                                  PWell

                                                                  Epi
                                                                            NSD


                                                            Substrate

                                                  Low Voltage NMOS cross-section

                                    4.0E-05
                                    3.5E-05
                                    3.0E-05
                 Bulk Current (A)




                                    2.5E-05
                                    2.0E-05
                                    1.5E-05
                                    1.0E-05
                                    5.0E-06
                                    0.0E+00
                                              0        1     2          3           4       5   6
                                                                 Gate Voltage (V)
                                                LV NMOS Hot Carrier Injection
• Maximum Vds determined from HCI measurements 10% degradation in 10 yrs
• Transient Vds rating based on 10% duty cycle

                                                                             LV LVT NMOS 100x6
                                                                     Time to 10% IDlin degredation vs. Vds
                               1.0E+09
                                              Measured Vds Max (V)                Id 10%                           10 yrs -> Vds=4.6V
                                                     Device               1 yr.             10 yr.
                                             LV NMOS 100x6                5.5                5.1
Time @ 10% Idlin degredation




                               1.0E+08
                                             LV NMOS 100x16               6.8                6.5
                                             LV LVT NMOS 100x6            5.1                4.6
                                             LV LVT NMOS 100x16           6.4                6.1
                               1.0E+07




                               1.0E+06




                               1.0E+05
                                      0.15          0.16         0.17             0.18                0.19   0.2             0.21       0.22
                                                                                                 -1
                                                                                         1/Vds (V )
                                         LV LVT PMOS drain-source leakage
• Drain-source leakage determines maximum Vds at high temperature
• Minimum channel length targeted based on process variation and independent
  SEM measurement
                                                      LV LVT PMOS Leakage vs. Gate Length (Vds=5V)
                                                                    L29894, wf #19
                         1.0E-06
                                   4.5          5.0              5.5               6.0              6.5   7.0       7.5
                         1.0E-07
                                                                                                                Flat_27
                         1.0E-08
                                                                                                                Flat_150
                                                          1.43um                                                Center_150
Leakage Current (A/um)




                         1.0E-09
                                         150C                                              1.70um
                                                                                                                Top_27
                         1.0E-10                                                                                Top_150
                                                                                                                Flat_poly1_27
                         1.0E-11
                                                                       1.69um
                         1.0E-12

                         1.0E-13

                         1.0E-14
                                         27C
                         1.0E-15
                                                       Minimum Poly2 CD = 1.57um
                         1.0E-16
                                                                           Gate Length (UDR)
                                        DMOS Specific Rdson
                        Active Area width


                                                    Rsp = Rdson x transistor active area

                                                  transistor active area = # cells x cell area
Active Area length




                                                  Device      Rdson (W)   Area (cm2)   Rsp. (mW.cm2)
                                               LV NLDMOS      0.66        5.19E-4      0.34
                                               MV1 NLDMOS     1.93        7.32E-4      1.41
                                               LV PLDMOS      2.58        5.19E-4      1.34
                                               MV PLDMOS      4.92        7.32E-4      3.6
                                               VDMOS_HEC      1.53        1.77E-3      2.7




                     Ex : LDMOS transistor
                        DMOS Specific Rdson
   S                   G                              D
                                                              • More components to Rdson
                                                              than just channel resistance
N+ P+ N+                             N+ P+          N+         RCH + REpi + RBL + RMetal
   PHV                                PHV PW       Sinker

    N-Epi
 N-Buried Layer                                               • Series resistance causes ‘bend’
            P-substrate                                       in ID vs. VG curve

                       6.0E-02

                       5.0E-02

                       4.0E-02
             IDS (A)




                       3.0E-02

                       2.0E-02

                       1.0E-02

                       0.0E+00
                                 0      2   4     6       8   10    12
                                                VGS (V)
        A useful way to extract DMOS series resistance
           C W
(1)   I   ox (V  V )V                    V V    I R
       D         GS T DS                      DS   DS   D S
             L

               I        V
       G   DS             DS
(2)     M V     (1  R  (V    V )) 2                           Substituting (2) into (3) gives,
            GS         S    GS    T
                                                                              ( I D  GM (VGS  VT ))VDS
                                            ID                       RS 
        
              COXW                                                                       2
                                                                                          ID
(3)
                L          VGS        VT VDS  I D RS 

          Device       size (cells)           R-series (Ohms)   Total rdson (OHMs)       % series resistance

      NLDMOS_13V          5x20                     0.37                0.69                     54 %

      NLDMOS_30V          5x20

      NLDMOS_45V          5x20                     1.44                1.99                     72 %

      PLDMOS_13V          5x20                     1.25                2.66                     47 %

      PLDMOS_45V          5x20                      2.8                5.0                      36 %

      VDMOS_HD           15x46                     1.63                1.84                     89 %
      VDMOS_HEC          13x46
                                                    DMOS Clamped Inductive Switching
• Clamping the flyback voltage below the DMOS breakdown increases energy
  capability.
• Power dissipation eventually allows parasitic bipolar to turn on, killing device

                                                                                                                                           Energy Capability
                                                                                                                                          Device Comparison

                                                                                                                          300
                                                                                                                                                                  y = 2.8072x0.6032

                                                                                                                          250                                                                 0.6421
                                                                                                                                                                                  y = 1.7849x

                                                                                                                                                                                      y = 1.9762x0.6223
                                                                                                        Energy (mJ/mm2)


                                                                                                                          200


                                                                                                                          150                                           47V VDMOS_HD

                                                                                                                                                                        47V VDMOS_HEC

                                                                                                                          100                                           47V MV2_NLDMOS
                       80                                                                       2.0

                       70
                                     Vd                                                                                                                                 Power (47V VDMOS_HD)
                                     Id                                                         1.5
                       60

                       50                                                                                                  50                                           Power (47V VDMOS_HEC)
  Drain Voltage (V)




                                                                                                1.0
                       40
                                                                    to                                                                                                  Power (47V MV2_NLDMOS)
                       30
                                                                                                0.5
                       20

                       10
                                                                                                                            0
                                                                                                0.0
                        0                                                                                                       0   500     1000               1500              2000                  2500
                      -10                                                                       -0.5
                      -5.00x10
                               -4
                                    -2.50x10
                                               -4   0.00     2.50x10
                                                                       -4
                                                                            5.00x10
                                                                                      -4
                                                                                           7.50x10
                                                                                                   -4
                                                                                                                                                   Time (uS)
                                                      Time (sec.)
                    Energy capability can determine device size

                          DMOS Rdson vs. Energy Capability

             30.0                                                      160.00


             25.0
                           Rdson                                       140.00

                           Energy Capability                           120.00
             20.0
                                                                       100.00
Rdson (W )




             15.0                                                      80.00

                                                                       60.00
             10.0
                                                                       40.00
              5.0
                                                                       20.00

              0.0                                                      0.00
              0.0E+00        2.5E-03           5.0E-03   7.5E-03   1.0E-02
                                           Area (cm 2)

								
To top