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Lecture 34 Some IC circuits Amit Kumar Mishra ECE, IIT G A/D Conversion Techniques If vX > vREF, output voltage is high corresponding to logic 1. If vX < vREF, output voltage is high corresponding to logic 0. vREF is time-dependent reference voltage, varied till unknown input is determined within quantization error of converter. Ideally ADC logic chooses bi so that v V n b 2 i VFS X FS i 1 i 2n 1 Counting ADC n-bit DAC used to generate any one of 2n outputs by applying appropriate digital input word. vX determined by sequentially comparing it to each possible DAC output. • Maximum conversion time occurs for full- scale input signal requiring 2n clock periods. • Binary value in counter is smallest DAC voltage larger than unknown input, not the DAC output closest to unknown input. • If input varies, binary output is accurate representation of input signal value at the instant the comparator changes state. • Requires minimum amount of hardware, inexpensive to implement. Successive Approximation ADC •Binary search used by SAL to determine vX. •n-bit conversion needs n clock periods. Speed limited by time taken by DAC output to settle within a fraction of an LSB of VFS and by comparator to respond to input signals differing by small amounts. •Slowly varying input signals not changing by more than 0.5 LSB (VFS /2n+1 ) during conversion time (TT = nTC) are acceptable. •For a sinusoidal input signal with p-p amplitude= VFS, f f c o n2 2 n •To avoid this frequency limitation, high speed sample-and-hold circuit is used ahead of the successive approximation ADC. •Very popular ADC with fast conversion times, used in 8- to 16- bit converters Single-Ramp (Single-Slope) ADC •Reference voltage varies linearly with a well- defines slope from slightly below 0 to above VFS v N v KNT X n if K= VFS / 2nTC. X C V 2 FS •Maximum conversion time occurs for full- scale input signal requiring 2 n clock periods. •Counter output is value of vX at the time end- of-conversion signal occurs. •Ramp voltage can be generated using an integrator connected to a constant reference voltage. •Dependence of ramp’s slope on RC product which is susceptible to changes due to temperature variations or aging is a limitation of this ADC. Dual-Ramp (Dual-Slope) ADC T 2nT T NT 1 C 2 C T T T 1 1 1 1 2 v x (t )dt VREF (t )dt RC 0 RC T vx T 1 N 2 n V T 2 REF 1 •Absolute values of R and C don’t affect operation. •Digital output word gives average value of vX during first integration phase. •Conversion time is given by: T (2n N )T 2n1T T C C •Can be used to get resolutions exceeding 20 bits but at lower conversion rates. Parallel or Flash ADC Unknown input simultaneously compared to 7 different reference voltages (3-bit converter). Logic network encodes comparator outputs into 3-bit binary output representing quantized value of input voltage. Very fast speed ( up to 108-109 conversions/sec), limited only by delays of comparators and logic network. Output continuously reflects input delayed by comparator and logic network. Requires 2n-1 comparators and reference voltages for n-bit conversion. Used for resolutions up to 10 bits. Delta Sigma ADCs Feedback loop attempts to force integrator output to zero. MT NT (M N )T V C V C V C 0 X RC REF RC REF RC V V REF (2m 2 N ) If M=2m X 2m N/M is average value of binary bit stream at output.LSB is VREF= 2m Effective resolution is determined by the time for which the output is averaged. Called oversampled because internal ADC samples integrator output at 16 Converter operation is considerably to 512 times Nyquist rate.Digital complex for time-varying input filter produces higher resolution. signals. Many Thanks
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