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					Vetcha Prasad Kumar
320/9, 29th B Main,                                                         Email: vechaprasad@yahoo.com
BTM I stage,                                                              Residence Phone: +91-80-6684625
Bangalore-68. INDIA.                                                 Office Phone: +91-80-5528940, Ext:136
_______________________________________________________________________________________________________________________

Experience Summary

Over Four and Half years of experience in the following areas of:
      Digital Circuit/Programmable ASIC/FPGA design.
      RTL coding and State Machine Implementation.
      RTL synthesis, optimizing the RTL for area or timing and place & route
      TB Coding, Functional/Timing simulation
      Firmware development in C and Assembly for 80x86, MCS-51 & ADSP-2105
      Ultrasound Medical system, Processor design, Bus interface units and Controller design
_______________________________________________________________________________________________________________________

Employment Details:
1. Presently working for CG-CoreEl Programmable Solutions Pvt Ltd, Bangalore as Sr.Design
   Engineer from Oct’03 to till date.
2. Presently working for CG-CoreEl Programmable Solutions Pvt Ltd, Bangalore as Design
   Engineer from April’01 to Sep 2003.
3. Worked in Embedded Systems and Software (EmSyS) unit of Larsen and Toubro Limited,
   Mysore, as Asst.Software Engineer from Sep 1999 to Mar 2001.
4. Worked in Medical Research & Development of Larsen and Toubro Limited, as Diploma
   Engineer Trainee from Sep 1998 to Sep 1999.
 Educational Background
                                                                                              Year of
  School/College/University                                      Degree                                    %Marks
                                                                                              passing
                                                       Diploma in Electronics
 NTTF Electronics Centre-Bangalore                 (Recognized as equivalent to US
                                                                                                1998           74
   (An ISO 9001 Training Institution)            Bachelor Degree of Science by A&M
                                                 Logos International Inc, New York)
 Z.P.P.H.School- Gannavaram                                    SSLC                             1995           80

TECHNICAL SKILLS:
 Programming Languages:              VHDL, C & C++, Assembly Language for ADSP 21xx, MCS-51 and
                                     80x86, TCL, FLI, SystemC, MFC

 Design Expertise:                   RTL simulation, Schematic based Designs, State Machine Design,
                                     FPGA Design, Place & Route and Test bench coding

 Domain Expertise:                   Ultrasound Medical systems, Processor design, bus interfaces, Controller
                                     design, Various FPGA architecture and High speed bus interfaces

 Domain Knowledge:                   RTOS, Smart cards, DFT

 Hardware Platforms:                 Synplify, Leonardo Spectrum, Quartus, Max Plus II, Xilinx ISE,
                                     ModelSim, TransEDA Verification navigator, Identify, Chipscope-Pro,
                                     Xilinx EDK, Seam less Co-verification
 Configuration Management:           Star Team


                                                                                                   Page 1 of 6
 Operating Systems:                  Win NT, Win 2000, UNIX SUN Operating System

PROFESSIONAL EXPERIENCE

MPC855T bus master with integrated 3-channel DMA and slave interface to
SDRAM & SMAC
Organization: Patni Computer Systems Ltd                                                        Nov 2003-Till Date
Team Size: 4                                                                                            4 Months

Involves development of 3 channel DMA controller with Master and slave interface to MPC855T.
Ethernet Frame Data is transferred from / to Serial Media Access Controller (SMAC) to / from
SDRAM controlled by MPC855T.
My Role in the Project
      Freezing the Specification on site with client
      Architecture development
      Developing the bus controller and DMA registers module
      RTL integration
      Synthesis and Xilinx Place route for the 50 MHz on Spartan –II device.
      Responsible for Integration, meeting the timing goal, final delivery to customer acceptance
Environment: VHDL, C, Assembly Language for MPC855T, TCL, ModelSim, Synplify, Logic
Analyzer
_______________________________________________________________________________________________________________________

4-Port Layer-2 gigabit switch
Organization: CG-CoreEl Programmable Solutions Pvt Ltd                                         July 2003- Till Date
Team Size: 12                                                                                            6 Months

Implementation of 4-port layer-2 gigabit switch on Virtex-II Pro FPGA. It is IEEE 802.1Q and 802.1D
compliant.
My Role in the Project
     Processor team lead role
     Design and Integration of Power PC405D and processor peripherals into the switch.
     Developing the OPB and PLB (comparable to AHB & APB) master and slave devices
     Developing a DMA controller with buffer chaining.
     Developing a firmware required for the layer 2-managed switch
     Responsible for Integration, meeting the timing goal, boar development and verification of the
         Switch in real time
Environment: VHDL, Verilog, C, Assembly Language for PPC405D, TCL, Xilinx EDK, Modelsim,
Synplify, Logic Analyzer
_______________________________________________________________________________________________________________________

FPGA Verification of WLAN chipset
Client: Athena Semi                                                                           May 2003-June 2003
Team Size: 3                                                                                             1 Month

Verification of WLAN chipset, which is compatible with IEEE 802.11a,b and g standards, on FPGA.
My Role in the Project
      Verification of WLAN IP, which was developed for ASIC, on the Virtex 6000&4000 FPGA.
      Data path analysis has been carried out to achieve 80Mhz frequency, which was targeted for
         ASIC, from the existing maximum frequency of 30Mhz.
      Generation of Virtex platform components to replace the ASIC library components



                                                                                                   Page 2 of 6
        Synthesis, Place and route constraints and scripts were developed to constrain multiple clocks
         and the false paths.
        Basic operations are verified on the board

Environment: Verilog, TCL, Solaris, Synplify, Identify, Logic Analyzer
_______________________________________________________________________________________________________________________

Design and Development of 8086
Client: Mistral Software Pvt Ltd                                                                Jan 2003-Feb 2003
Team Size: 6                                                                                             2 Months

Implementation of 100% software and cycle compatible Intel’s 8086 Microprocessor on Spartan II
FPGA.
My Role in the Project
     Optimizing the RTL for area. Involves partitioning the logic among the modules, RTL code
       review, analysis and modifying the module architecture
     Modification of instruction queue, address generation, Execution unit and bus    interface
       unit modules architecture
     Performed functional simulation
     Synthesized on ASIC and FPGA technologies with false paths and multi-cycle path constraints
     Performed Timing simulation
Environment: VHDL, 8086 Assembly Language, TCL, ModelSim
_______________________________________________________________________________________________________________________

Development of Memory Management unit of ARM1020E
Organization: CG-CoreEl Programmable Solutions Pvt Ltd                                         Nov 2002-Dec 2002
Team Size: 4                                                                                            2 Months

Implementation of Memory Management unit of ARM processor
My Role in the Project
     Guiding the B.E. and MSc students and developing the architecture
     Technology independent CAM RTL development and verification of the same
     TLB, Address generation, control logic development
     Performed functional simulation
     Synthesized on FPGA technology
     Performed Timing simulation
Environment: VHDL, ModelSim
_______________________________________________________________________________________________________________________

Crater- Fast 8031, Pipelined architecture Core
Organization: Space Application Centre (SAC), TCS, CMC                                          Feb 2002-Oct 2002
Team Size: 4                                                                                             8 Months
URL: CG-CoreEl - Products [ IP-Cores, Microprocessors ]_Crater

World’s highest performance pipelined 8031 Microcontroller core built for high-speed SOC
applications. Crater is binary-compatible with the industry standard 8031/8051 8-bit Microcontroller.
My Role in the Project
      Pipelined processor Architecture Design
      Team lead role
      RTL Design and Development of Dependency Control logic, Pipeline, Address generator
      Development of Test Cases in assembly and C
      Verification, Simulation Code Coverage analysis and Synthesis
      RTL optimization for Area


                                                                                                   Page 3 of 6
      C library development for standard I/O functions
      Dhrystone Benchmark execution on Crater
      Verification on the Virtex-II Pro evaluation board
Creativity/Innovation: Procedure to find out the dependency issue in pipelined architecture. Step by
step procedure to find out the various hazards in pipeline architecture.

Environment: VHDL, C, MCS-51 Assembly Language, TCL, FLI, Keil, SDCC, ModelSim,
TransEDA Verification navigator, Leonardo spectrum, Chipscope-Pro, ISE 5.2
_______________________________________________________________________________________________________________________

Development of CGC 8031-Intel 8031
Organization: CG-CoreEl Programmable Solutions Pvt Ltd                                          Nov 2001-Jan 2002
Team Size: 2                                                                                            3 Months

Implementation of 100% software and cycle compatible Intel’s 8031 Microcontroller on Spartan II
FPGA.
My Role in the Project
     RTL code review, analysis and modifying the module architecture, removal of internal tri-
       states, converting into synchronous design
     Performed functional simulation
     Synthesized on ASIC and FPGA technologies with false paths and multi-cycle path constraints
     Generation of FPGA netlist file
Environment: VHDL, C, MCS-51 Assembly Language, TCL, ModelSim, Leonardo spectrum
_______________________________________________________________________________________________________________________

TMS 9995-16 bit Processor
Organization: CG-CoreEl Programmable Solutions Pvt Ltd                                          Apr 2001-Oct 2001
Team Size: 4                                                                                             7 Months
URL: CG-CoreEl -Products [ IP-Cores, Microprocessors ]_TMS 9995

Design and Development of software and I/O compatible TMS9995 Microcontroller.
My Role in the Project
         Code analysis and documentation
         Developing the test suits
         Testing and debugging the TMS 9995 at board level
         Documentation and delivery of TMS 9995
Environment: VHDL, TMS 9995 Assembly Language
_______________________________________________________________________________________________________________________

Ultrasound Scanner Design for Electronic Transducer
Organization: L&T EmSyS                                                                         Apr 2000-Jan 2001
Team size: 3                                                                                            9 Months
URL: Medical Ultrasound Image processing card

System is based on 80486DX2, 100MHZ processor and consists of ISA Bus Add-on cards for image
processing, storage, printing and display on PAL Monitor.
My Role in the Project:
          Team lead role
          DSP (ADSP 2105) program modification to store the image data as required by electronic
             probes
          RTL Development in VHDL, Synthesis and Place & Route for electronic transducer add-
             on FPGA-ACEX 1K family
          Software development in C and Assembly for 80x86



                                                                                                   Page 4 of 6
         System Verification, meeting IEC605 standard and CE marking requirements and
          releasing the product
Environment: VHDL, C, Assembly language for 80x86 and ADSP 2105, Maxplus II, Quartus
_______________________________________________________________________________________________________________________

Frame averaging & AGC generation card
Organization: L&T EmSyS                                                                        Dec 1999-Apr 2000
Team Size: 2                                                                                            5 Months
URL: Image Processing and Real-Time Display for Ultrasound Machines

Implementation of programmable clock generation logic and image averaging based on user interface.
It replaces the TTL logic devices implemented PWA using Programmable Peripheral Interface
(PPI)(8255), PAL, counters, adders, flip-flops, latches, buffers and basic gates (AND, OR). The board
consists of 50 ICs and converted into single FPGA

My Role in the Project
     RTL coding, schematic entry for Frame averaging & AGC generation circuit.
     Development of RTL code for 8255
     VHDL memory implementation of PROMs
     Synthesis and Place & route.
     Board development and Verification in system
Environment: VHDL, Schematic Capture & entry, Maxplus II
_______________________________________________________________________________________________________________________

Ultrasound scanner product up gradation
Organization: L&T EmSyS                                                                        Dec 1998-Dec 1999
Team Size: 2                                                                                           12 Months

Reducing the system cost and stabilizing the Ultrasound scanner, which is based on mechanical transducer
technology
      Replacing the obsolete components, and fine-tuning the board level issues to reduce the design
        failures
      The software for the ultrasound scanner, which is developed in C & C++ are modified, to
        accommodate the new requirements.
      Hardware and firmware has been changed/corrected to fine-tune the system level issues.

Environment: C, VHDL, Assembly for 80x86
_______________________________________________________________________________________________________________________

PC Based simulator
Organization: L&T EmSyS                                                                        Sep 1998-Nov 1998
Team Size: 4                                                                                            3 Months

Designed for final testing of Ultrasound scanner to perform the testing/calibration faster and easy
My Role in the Project
     Involves GPIB interface and programming with Data Acquisition card (48 I/O channels and
        two ADCs).
     Software, which controls the testing equipments (oscilloscope...etc, which are connected to
        GPIB interface) & data acquisition card, developed in C.
     Designed data acquisition card using the 8255 (Programmable Peripheral Interface (PPI)) and
        ADC.
     Circuit design for interface logic and Board development




                                                                                                   Page 5 of 6
Environment: C, DOS, Digital storage oscilloscope (DSO)




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