Our Simple Machine
A Simple Machine
In this section we’ll define
(SM213)
a simple machine with simple instructions
a simulator for this machine that will allow us to
execute programs
Releted Material:
CPSC 213 Companion We’ll use the machine to execute Java and C
- 2.3
programs
To define our machine we need to specify
its instruction set
its registers
its memory
Based on Mike Feeley’s original slides; Modified by George Tsiknis
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Instruction Set Architecture (ISA) Instruction Format
Instruction format defined by CPU hardware
its the hardware “API” for a CPU implementation Each instruction is a number that combines
e.g., IA32 (aka x86) for many Intel implementations an operation code (opcode) that picks a hardware
An instruction is a sequence of binary values (like function
everything else) one or two input operands (where input comes from)
Two types of ISA one output operand (where result goes)
RISC (Reduced Instruction Set Computer)
– as simple instructions as possible (few memory instructions)
– fixed-size instructions
– examples: SPARC, MIPS
CISC (Complex Instruction Set Computer)
– variable-size instructions
– many memory access instructions
– Examples: Intel’s and AMD’s IA32
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ISA: Example Instruction On the side: hexadecimal notation
Example of an add instruction
Bit Pattern in Hex Asembly Code Comments
Often we are interested in the bit pattern of the
6101 add r0, r1 r1 = r0+r1 registers or main memory
Instead of binary, we can use hexadecimal
Example of a sequence of instructions (with memory each hex digit is 4 bits (0, … , 9, A,…, F)
access) that compute: a = a+1
For instance:
Suppose a is in memory location 0x1000
0001100011111011
0000 00001000 ld $0x1000, r0 r0 = 0x1000 in hex is
1001 ld 0x0(r0), r1 r1 = a 18FB
6301 inc r1 r1 = r1+1 and it is shown as
3100 st r1, 0x0(r0) a = r1 0x18FB
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Instruction Types On the side: Signed Numbers
Memory access First bit of the number indicates its sign:
load, store (between memory and a register ) 0 – positive, 1 – negative
ALU operations Signed integers are represented in two’s
arithmetic: add, sub, mult, div, complement
logical: and, or, xor, shift left,
sign extended shift right (bits filled with sign bit)
For instance, to negate the short integer 2 :
zero extended shift right (bits filled with zero)
etc.
Control flow
jump, branch (unconditional and conditional )
used for implementing loops, if statements, etc.
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Addressing Mode SM213 Addressing Mode
Indicates how to interpret the value of an instruction
operand Mode for our machine (a subset of IA32/s):
Typical modes:
immediate : operand’s value is part of the instruction Mode Operands Value
register: operand’s value is in a register
base+displacement : operand’s value is in the memory address
immediate v v (a 32 bit constant)
specified by a register and a constant value register r register[r]
indexed: operand’s value is in the memory address specified by base +
the contents of two registers o b memory[ register[b] + 4*o ]
displacement
In real ISA’s there is a mode part in the instructions
memory[ register[b] +
In our machine, op ode determines the addressing mode indexed i b
4 * register[i] ]
there is no separate mode part
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Assembly Language Our SM213 Machine
Symbolic representation of machine instructions Registers
8 32-bit general purpose registers named 0-7
One to one correspondence between assembly Memory
and machine instructions byte addressed
– like an array of bytes
An assembler translates assembly code into stores data and instructions
machine code (instruction-by-instruction) data transfers aligned 32-bit words
A disassembler translates machine to instruction transfers aligned 16-bit words
it is Big Endian
assembly code integers are stored in two’s complement
To generates assembly code for a C program Instruction Set Architecture (ISA)
myprog.c you can do includes opcode and operand specifiers
gcc –O1 –S myprog.c formatted as 16-bit number represented as 4 HEX digits
– one (or two) hex digit for op code, rest for operands
native assembly code will be in file myprog.s – uses extra 32-bit word following instruction if necessary
type “uname –a” to find the ISA of a Unix system • note that this word will not necessarily be 32-bit aligned
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Some SM213 Assembly Codes SM213 ISA (cont’)
opCode Operation Addressing modes in assembly format:
ld load from memory
st store into memory Mode Format Example
mov move between registers immediate $# ld $0x3A, r0
add add integers register r# add r0, r1
inc increment an integer
base +
dec decrement #(r#) ld -8(r1), r2
displacement
and bitwise logical and of two 32-bit values
indexed (r#, r#, 4) st r1, (r2, r3, 4)
not bitwise complement of a 32-bit value
gpc get program counter value SM213 ISA will be build incrementally
shr shift right
We’ll be considering snippets of Java and C code and
shl shift left decide on the instructions we need to implement them
halt stop program
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Simulator for the SM213 What’s Next ?
Executes the SM213 ISA
It is really a SM213 assembler We’ll start studying C
Is written in Java simple staff first
Has a GUI that displays We’ll keep adding instructions to SM213 ISA
the assembly code and the machine code of the instructions
the content of each register (general and special) We’ll translate the C statements into SM213
the content of the memory Assembly
GUI allows the user to
change the assembly code
type new assembly code
change values in registers and memory
trace the execution of the program
You’ll study and work with it in the labs
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