Regulation and Dynamics Regulation and Dynamics

Regulation and Dynamics

Regulation and Dynamics

Frédérick BORDRY

Frédérick BORDRY



3 Regulation

on

Tracking

si

Ses



Ts y(t)

yref(k) Power

T 1/S DAC

converter



Digital k.Ts

÷k

Anti

controller Digital

R Filter

ADC aliasing

filter

Oversampling









Powering Workshop - 28th November 2000 Fk. Bordry SL/PO

Glossary

– Accuracy

– Accuracy

Long term setting or measuring uncertainty taking into consideration

Long term setting or measuring uncertainty taking into consideration

the full range of permissible changes* of operating and environmental

the full range of permissible changes* of operating and environmental

conditions.

conditions.

Precision



**requires definition

requires definition



– Reproducibility

– Reproducibility

Uncertainty in returning to aaset of previous working values from

Uncertainty in returning to set of previous working values from

cycle to cycle of the machine.

cycle to cycle of the machine.



– Stability

– Stability

Maximum deviation over aaperiod with no changes in operating

Maximum deviation over period with no changes in operating

conditions.

conditions.



Accuracy, reproducibility and stability are defined for aagiven period

Accuracy, reproducibility and stability are defined for given period



Precision is qualitative . Accuracy is quantitative.

Powering Workshop - 28th November 2000 Fk. Bordry SL/PO

Power Converter Tolerances for LHC

Power Converter Tolerances for LHC

Circuit Nominal Current One Year One day 1/2 hour Resolution

Type Current Polarity Accuracy Reproducibility Stability

(A) (ppm of Inominal) (ppm of Inominal) (ppm of Inominal) (ppm of Inominal)

± 50

Main Bends, Main Quads Unipolar ± 10 ±3 1

13000 ± 20 with calibration

8000/ ± 100

Inner triplet Unipolar ± 20 ± 10 15

6000 ± 20 with calibration?

Dispersion suppressor Unipolar ± 70 ± 10 ±5 15

6000

Insertion quadrupoles Unipolar ± 70 ± 10 ±5 15

6000

Separators (D1,D2,D3,D4) Unipolar ± 70 ± 10 ±5 15

6000

Trim quadrupoles Bipolar ± 200 ± 50 ± 10 30

600

SSS correctors Bipolar ± 200 ± 50 ± 10 30

600

Spool pieces Bipolar ± 200 ± 50 ± 10 30

600

Orbit correctors Bipolar ± 1000 ± 100 ± 50 30

120/60









Precision Control





Powering Workshop - 28th November 2000 Fk. Bordry SL/PO

Power converter : voltage ripple specification

Power converter 50 HzRipple 300 HzRipple

type pk-pk pk-pk

(mV) (mV)

[13kA, ±180V] 20 130

[13kA, 18V] 50 350 Load identification

[8kA,8V] 5 30

[6kA,8V] 5 30

[4kA,8V] 5 30



[±600A,±10V] 5 20

[±600A,±40V] 5 20



[±120A,±10V] 5 20



[±60A,±8V] 200 1200 20 ; 120



[900A, 550V] 40 250

[900A,1000V] 80 450



Powering Workshop - 28th November 2000 Fk. Bordry SL/PO

Voltage loop

Current loop



I

Iref B

Vref

+ εΙ V

Reg. G(s)

-

F(s) εV









Imeasured









Powering Workshop - 28th November 2000 Fk. Bordry SL/PO

Closed Loop

Closed Loop

Disturbances

Perturbations

Feed P

Yref + ε Y

Reg. System

-

F(s) H(s)



Transducer

G(s)



Open loop : system H(s) ; system with controller F(s).H(s)

Closed loop : HCL(s) = F(s).H(s) / [ 1 + F(s). H(s) G(s) ]

Steady state error : F(s) must contains the internal model of the reference (the

transfer function that generates Yref(t) from the Dirac impulse ; e.g. step =

(1/s) * Dirac ; ramp = (1/s2) * Dirac,...

Powering Workshop - 28th November 2000 Fk. Bordry SL/PO

Choice of the desired performances

Choice of the desired performances



The choice of desired performances in terms of the response time

(bandwidth) is linked to the dynamics of the open-loop system and to

the power availability of the actuator during the transient :

acceleration of the natural response requires control peaks that are

greater than the steady-state values

U Y

Umax/Ustat ≅ desired speed/natural speed

≅ desired bandwidth / natural bandwidth

≅ fCLB / fOLB



Or, the actuators will have to be chosen as a function of the

desired performances and the open-loop response of the system





Powering Workshop - 28th November 2000 Fk. Bordry SL/PO

Choice of the desired performances (cont’d)

Choice of the desired performances (cont’d)





The robustness of the closed-loop system

is linked to the ratio fCLB / fOLB

(sensitivity to the uncertainty or variation of the

model parameters)



If the ratio is too high => bad robustness and

If the ratio is too high => bad robustness and

need to have a good knowledge of the process

need to have a good knowledge of the process

model (high frequency identification ;; e.g.

model (high frequency identification e.g.

LHC string dipole)

LHC string dipole)

or use of adaptive control

or use of adaptive control

Powering Workshop - 28th November 2000 Fk. Bordry SL/PO

Main LHC quadrupole

Main LHC quadrupole [13000A,18V]





Ω

Magnet chain ::L=0.27 H ;;R = 0.8 mΩ => ustat = R.13000 ≅ 10.4 V

Ω

Magnet chain L=0.27 H R = 0.8 mΩ => ustat = R.13000 ≅ 10.4 V

T = L/R = 340 ss => ffOLB ≅ 0.47 mHz

T = L/R = 340 => B ≅ 0.47 mHz

OL







Large signal ::umax/ustat ≅ 1.7 => ffCL ≅ 0.8 mHz => tt = 430 ss

Large signal umax/ustat ≅ 1.7 =>

CL

B ≅ 0.8 mHz => R = 430

B R





Small signal ::ffCL = 1 Hz => ffCL //ffOL ≅ 2200 !!!!…

Small signal

CL

BB = 1 Hz =>

CL

BB

OL

BB ≅ 2200 !!!!…





Then ustat = 7.6 //2’200 ≅ 3.5 mV

Then ustat = 7.6 2’200 ≅ 3.5 mV

Ω

=> ∆II= 3.5 mV/0.8 mΩ = 4.4 A = 0.035 % Inom = 350 ppm Inom

Ω

=> ∆ = 3.5 mV/0.8 mΩ = 4.4 A = 0.035 % Inom = 350 ppm Inom









Powering Workshop - 28th November 2000 Fk. Bordry SL/PO

LHC orbit corrector

LHC orbit corrector [±60A,±8V] (arc corrector)



Ω

Magnet : L=7 H ; R = 30 mΩ (60m of 35 mm2)

T = L/R = 300 s => fOLB ≅ 0.5 mHz

Ustat = R.I = 1.8V



Large signal : umax/ustat ≅ 4 => fCLB ≅ 2 mHz => tR = 175 s

(dI/dtmax ≅ 1A/s)



Small signal : fCLB ≅ 1 Hz => umax/ustat ≅ 1/ 0.5 10-3 = 2000 !

Ω

Then ustat = 6 / 2000 = 3mV => ∆I = 3mV/30 mΩ = 0.1 A = 0.15 % Imax

Is it enough ? fCLB ≅ 0.1 Hz ?



LHC Project Note 183 : “The power converters involved in analogue feedback

of the local orbit may need to deal with correction rates between 10 and 500 Hz”;

fs (rate ?) = 500 Hz => fCLB ≅ 50Hz (∆I = 1% : Umax = 2400 V ?????...)

(Umax= 8V => ∆I = 30 ppm Imax)

Powering Workshop - 28th November 2000 Fk. Bordry SL/PO

Closed-loop bandwidth : small signal amplitude

Chromaticity sextupoles SF1 and SF2

SF1, SD1, SF2, SD2 64 circuits

SF1 : beam 1 and beam 2 ; one per arc => 16 circuits

SD1 : beam 1 and beam 2 ; one per arc => 16 circuits

SF2 : beam 1 and beam 2 ; one per arc => 16 circuits



Example : SD2 : beam 1 and beam 2 ; one per arc => 16 circuits

Each circuit: 12 magnets in series for SD families and 10 magnets for SF families

Converter ± 600 Imax (A) ± 10 Umax (Volt)



Lcircuit 0.36 H SF1 and SF2 families

Rcircuit 0.0083 Ohm Ucollision 4.98 V



Time_constant 43.37 s

f open_loop_B 0.0037 Hz 3.7 mHz





Large signal

dI/dtmax 14 A/s



Umax/Ucollision 2.0 = f closed_loop_B/ f open_loop_B



f closed_loop_B 0.007 Hz 7.4 mHz tr 48 s





Small signal

f closed_loop_B 1 Hz



Uavailable/Ucollision 273

Uavailable 5.02 V (= Ummax - Ucollision)



Ustat 0.018 V 18 mV





∆I 2.2 A 0.4 % of Imax



Powering Workshop - 28th November 2000 Fk. Bordry SL/PO

Voltage and current loop bandwidth

Voltage and current loop bandwidth

Cold Circuits Current Converter Inductance Resistance TC max. Ramp U max. Voltage Current

0 to 100% loop loop

(kA) (mH) (mohms) (sec) (sec) (V) (Hz) (kHz)

Main Bend 13.00 [13kA,±180V] 16632 0.8 20790 1300 176.7 500 0.1 to 1.0

Main Quads 13.00 [13kA,18V] 263 to 285 0.8 to 0.97 356 1300 15.2 500 0.1 to 1.0

Inner Triplet 7.00 [8kA,8V] 220 0.33 667 1300 3.5 500 0.1 to 1.0

" " Trim 4.40 [6kA,8V] 38 0.45 84 1300 2.1 500 0.1 to 1.0

Disper. Quads 5.82 [6kA,8V] 21 to 26 0.49 to 0.95 53 360 5.9 500 0.1 to 1.0

Insert. Quads 4.65 to 5.82 [6kA,8V] 15 to 30 0.49 to 0.9 61 360 5.7 500 0.1 to 1.0

Insert. Quads 3.90 [4kA,8V] 74 to 148 0.67 to 0.9 221 360 5.1 500 0.1 to 1.0

Separators 6.00 [6kA,8V] 28 to 50 0.52 to 0.68 96 360 4.9 500 0.1 to 1.0

Q6,pts 3 & 7 0.60 [±600A,±10V] 600 1.8 to 7.02 333 360 5.2 1000 0.1 to 1.0

Q6,pts 3 & 7 0.60 [±600A,±10V] 600 23 26 360 14.8 1000 1 to 2

Spool b3,b5 0.60 [±600A,±10V] 31 to 123 8.28 15 120 5.6 1000 1 to 2

Trim Quads 0.60 [±600A,±10V] 31 to 248 1.8 to 8.28 138 120 6.2 1000 0.1 to 1.0

Trim Quads 0.60 [±600A,±10V] 31 to 248 25 10 120 16.2 1000 1 to 2

SSS Correctors 0.60 [±600A,±10V] 72 to 432 2.34 to 8.28 185 120 7.1 1000 0.1 to 1.0

SSS Correctors 0.60 [±600A,±10V] 72 to 144 26 to 47 5.5 120 28.9 1000 1 to 2

Octupoles 0.60 [±600A,±10V] 13.5 to 18 1.8 to 8.28 10.0 120 5.1 1000 1 to 2

Octupoles 0.60 [±600A,±40V] 13.5 to 18 49 0.4 120 29.5 1000 1 to 2

Spool b4 0.12 [±120A,±10V] 31 35 0.9 120 4.2 1000 1 to 2

Orbit Correctors 0.12 [±120A,±10V] 2240 to 4100 11 to 49 373 120 8.0 1000 0.1 to 1.0

Low B Corr. 0.12 [±120A,±10V] 3.7 to 21 9.4 to 36 2 120 4.341 1000 1 to 2

Orbit Correctors 0.06 [±60A,±8V] 7000 31 226 120 5.4 2000 0.1 to 1.0



Warm Circuits Current Converter Inductance Resistance TC max. Ramp U max. Voltage Current

loop loop

(kA) (mH) (mohms) (sec) (sec) (V) (Hz) (kHz)

Quads 0.81 [900A,550V] 640 410 to 534 1.6 120 436.9 70 5 to 10

Separators 0.81 [1000A,1000V] 1200 1800 1000 1.8 120 822.2 70 5 to 10

Dump Septum 0.88 [900A,550V] 1060 569 1.9 120 508.5 70 5 to 10

Warm Trim/Corr 0.60 [±600A,±40V] 25 64 26 59 2.5 120 35.7 1000 5 to 10





Powering Workshop - 28th November 2000 Fk. Bordry SL/PO

R.S.T control :: generic control

R.S.T control generic control

yref(k) H(z-1)

T 1/S =z -d B(z -1)/A(z -1)

Tracking Regulation

Plant



R



Tracking and Regulation with independent objectives

Tracking and Regulation with independent objectives

This control strategy permits a R.S.T digital controller to be designed for

both stable and unstable systems:

- without restriction on the degrees of the polynomials A(z-1) and B(z -1) of

the plant transfer function

- without restriction on the sampled time delay of the system (d)

This strategy can only be applied to discrete-time models with stable zeroes

(minimum phase systems):

- high sampling period => unstable zeroes

- fractional time delay > 0.5 x Ts

Powering Workshop - 28th November 2000 Fk. Bordry SL/PO

Summary

Summary

Ts

yref(k) y(t)

T 1/S DAC System

k.Ts

Digital Anti

÷k

Digital

controller R Filter

ADC aliasing

Frequency Oversampling filter

Divider

Based on fOLB and power of the actuator : choice of the closed-

loop performances [fCLB (tr ) and Q (M) ]

Robustness ; fCLB / fOLB (Internal saturation : controlability)



fs (sampling period) : choice based on the fCLB

fs = 1/Ts = (6 to 25) * fCLB

Discrete model H(z-1) at Ts

Powering Workshop - 28th November 2000 Fk. Bordry SL/PO

Ramp from to 500A

500 A

[±600A,±10V]

[±600A,±10V]

Superconducting magnet

Superconducting magnet

L= 1 mH

L= 1 mH

Rcircuit = 3.3 mΩ

Rcircuit = 3.3 mΩ

ττ= L/R = ~ 300 ms

= L/R = ~ 300 ms

ADC 16 bits (15 ppm)

ADC 16 bits (15 ppm)





FCLB = 4 Hz



±5mA

500 A (±8 ppm)









Powering Workshop - 28th November 2000 Fk. Bordry SL/PO

4 4

x 10 x 10









1.3 1.3





25 ppm

1.28 1.3









1.26 1.3





1A

1.2999

1.24







1.2999

1.22







1.2999

1.2



1000 2000 3000 4000 5000 6000 7000 8000 9000 8550 8600 8650 8700 8750 8800 8850 8900 8950 9000









4

x 10



Ramp from 200 A to 13000A 1.3







1.3





10 ppm 1.3



[13kA,18V] converter

[13kA,18V] converter 1.3





1mH inductance ;;

1mH inductance 1.3





0.8 mΩ resistance

0.8 mΩ resistance 1.3





(τ = 1.5 s)

(τ = 1.5 s) 1.3





dI/dt = 200 A/s

dI/dt = 200 A/s 8700 8750 8800 8850 8900 8950 9000









Powering Workshop - 28th November 2000 Fk. Bordry SL/PO

Error =

Imeas - Iref





30 ppm









4

x 1 0







1 . 3







1 . 3







Iref 1 . 3

10 ppm

1 . 3



ADC 1 . 3







1 . 3







1 . 3







8 7 0 0 8 7 5 0 8 8 0 0 8 8 5 0 8 9 0 0 8 9 5 0 9 0 0 0









Powering Workshop - 28th November 2000 Fk. Bordry SL/PO

Start of the ramp (from 200 A)

225





dI/dt = 50 A/s

220









215



Iref

210









205

ADC



No lagging error !

200



1200 1400 1600 1800 2000 2200 2400









212.5

215



212.4



214 212.3



212.2



213

212.1



212

212

211.9



211.8

211



211.7



210 211.6



211.5



1950 2000 2050 2100 2150 2200 2060 2070 2080 2090 2100 2110









10 ms

Powering Workshop - 28th November 2000 Fk. Bordry SL/PO

I1

Vcv1

Vcv2



8kA 6kA

I2









1 2 2 3



KEK Fermilab Fermilab KEK







IF = I1 + I2 IK = I1



 r1 r2   1 1 

− − −

d i1   L1 L1   i1  L1 L1 .Vcv1

i 2 =  r1

dt    1

+

1  i 2  1 1

.

1   Vc 2 

− r 2. +    − +  

 L1  L1 L 2   L1 L1 L 2 



Powering Workshop - 28th November 2000 Fk. Bordry SL/PO

Decoupling Principle ::

Decoupling Principle

W U dX X

dX D = A. X + B.U

= A. X + B.U dt

dt

dX K

= ( A + B.K ).X + B.D.W

dt

Ad Bd Choice :

Ad and Bd : diagonal matrices − r1 0 

 L1 + L2 

Ad = 

Decoupling matrices : r2 

 0 − 

K = B-1 . (Ad -A)  L2 

D = B -1 . B  1

 L1 + L 2 0 

Digital : Bd = 

X*(k+1) = F*.X*(k) + H*.U*(k) 1

 0 

with F*= e A. ts ; H* = A-1. (e A. ts - I).B  L2 

ts : sampling period

X*(k+1) = Fd*.X*(k) + Hd*.W*(k)

Powering Workshop - 28th November 2000 Fk. Bordry SL/PO

Dcct 1





DSP 1 ADC

Vconv1

Converter 1

Ikref = I1ref 8kA

Reg. 1 Voltage source

DAC



Vref1

Analog

Digital decouplind card

Vconv1 = V1ref + k1v. V2ref +

K1i. I2

Vconv2 = V2ref + k2v. V1ref +

K2i. i1



DSP 2

I2ref Vref2 Converter 2

-

IFref +

Reg. 2 DAC

4kA

Vconv2

Voltage source

ADC



Dcct 2

Digital





Powering Workshop - 28th November 2000 Fk. Bordry SL/PO

MQM connection ::3 busbars and 3 current leads

MQM connection 3 busbars and 3 current leads



r1

L1

Vcv1

di1

Vcv1 = r1.i1 + L1. + rc.(i1 − i2)

rc dt

di2

Vcv 2 = r 2.i 2 + L 2. + rc.(i1 − i 2)

dt

Vcv2 L2

r2 With r1 = r2 = rc = r



− r1 + rc rc  1 0  Vcv1

d i1   L1 L1 . i1 +  L1 

i 2 = .

dt   rc r 2 − rc  i2  1   Vc 2 

 − −   0  

 L2 L2   L2 





Powering Workshop - 28th November 2000 Fk. Bordry SL/PO

MQM connection ::3 busbars and 3 current leads

MQM connection 3 busbars and 3 current leads MQM

Dcct 1





DSP 1 ADC

Vconv1

Converter 1

I1ref 6kA

Reg. 1 Voltage source

DAC



Vref1

Analog

Digital decouplind card

Vconv1 = V1ref + k1v. V2ref +

K1i. I2

Vconv2 = V2ref + k2v. V1ref +

K2i. i1



DSP 2

I2ref Vref2 Converter 2

Reg. 2 DAC

6kA

Vconv2

Voltage source

ADC



Dcct 2

Digital



Powering Workshop - 28th November 2000 Fk. Bordry SL/PO

Power converter control and high precision issues

Power converter control and high precision issues

3.1 Regulation and dynamics - F. Bordry

3.2 Hardware implementation - J. Pett

3.3 Software implementation - Q. King

3.4 DCCT and Standards Lab infrastructure - F. Power

Tracking Regulation

3.5 On site calibration system - G. Fernqvist

ns

ssio 6

Se & Output current

5 Power

Load

Power input processor

Control Current

signals Measurement



Controller Gateway



I(t)





time

Powering Workshop - 28th November 2000 Fk. Bordry SL/PO

Powering Workshop - 28th November 2000 Fk. Bordry SL/PO