HIGH ENERGY ELECTRON ACCELERATOR RESEARCH ORGANIZATION
REAR ORIENTED ELEMENTRY PARTICLE AND ATOMIC NUCLEOUS
RESEARCH
COPPER/FINESSE BOARD
IMPLEMENTATION DOCUMENTATION
FIRST EDITION
JULY 24, 2003
Doug Shimokawa
University of Hawaii at Manoa
Instrument Development Lab
FINESSE
The FINESSE card is designed to be able to quickly and accurately provide a
pipeline for data into the COPPER board. In order to accomplish this the card uses two
RAM chips, which will alternate back and forth to make simultaneous data input from the
USB, and data output to the COPPER board possible. The FINESSE card is
implemented using a Cypress CY7C68013 chip for the USB interface, a Xilinx
XCV100E FGA, two Cypress CY7C1355a RAM chips, and a Xilinx XC95144XL CPLD
chip. The data will be pipelined through the USB and the FPGA to one of the two RAM
chips. While data is being written to one of the RAM chips it will simultaneously be
pulled off of the other RAM chip by the FPGA and be sent to the FINESSE-COPPER
interface.
USB-FPGA
The handshaking between the USB interface and the FPGA is done with a two-bit
address signal, FIFOADR(1:0), an output enable signal, SLOE, a read strobe, SLRD, a
write strobe, SLWR, and packet end signal, PKTEND, sent to the USB by the FPGA, and
indexed empty, EMPTY, and full flags, FULL, sent from the USB to the FPGA. All of
the handshaking signals, except for the address signals, default as low active, but may be
changed via the FIFOPINPOL register. The address signal selects which of the 4 double-
buffered pipes from the USB that the FPGA will be able to interact with. Pipe 2, address
00, and pipe 4, address 01, are output pipes that allow for data to be written out of the
USB to the FPGA. Pipe 6, address 10, and pipe 8, address 11, are input pipes that allow
the FPGA to write data to be read out from the USB. The pipes are all double buffered,
so although they are able to hold up to two 512-byte packets (using USB2.0, the USB
only allows two 64-byte packets when using USB 1.1), two packets of any size will cause
the pipes to return full. Once the pipe address is set by the FPGA the USB will return the
empty and full flag values to the FPGA. Since all of the handshaking signals are low
active, as long as the empty flag is asserted high, there is data in the USB buffer that can
be read by the FPGA, and as long as the full flag is asserted high there is space in a USB
buffer to write data to. The USB interface will return the empty flag for pipes 6 and 8,
and the full flag for pipes 2 and 4, however these are not of interest to the USB-FPGA
interface. The read and write strobes and the packet end signal are to be asserted low for
one clock cycle for each read, write or non-full end of packet. The output enable signal,
SLOE, must be asserted low for a read to occur. If SLOE is not asserted low, a read will
not occur even if SLRD is asserted low for one clock cycle.
This FINESSE card is designed only to direct data in from the USB to the
COPPER board, so there is no need to write data back to the USB, and thus the pipe
address can always be asserted to 00, the write strobe, SLWR, can always be asserted
high, and the packet end signal, PKTEND, can always be asserted high. The only signal
that needs to be examined is the empty flag, and the only signals that need to be set are
the output enable flag, SLOE, and the read strobe, SLRD. The output enable flag is set to
the inverse of the empty flag. Since both signals are active low, output should be
enabled, SLOE =0, whenever the pipe is not empty, EMPTY =1. The read strobe, SLRD,
should be asserted low for one clock cycle whenever reading is possible, so whenever the
pipe is not empty.
CLK
EMPTY
FIFOADR0
FIFOADR1
SLOE
SLRD
SLWR
PKTEND
Timing for one read from the USB pipe 2 to the FPGA
FPGA-RAM
The interface between the FPGA and one of the RAM chips is done via an 18-bit
memory address signal, A(17:0), 3 chip enable bits, CE(3:1), 4 bank enable bits,
BW(D:A), an advance/load enable bit, ADV/LD, an output enable bit, OE, and a write
(input) enable bit, WEN. In order to configure the RAM chip to work the CE(3:1) signals
need to be set to 010. In this case since the data bus is designed to be 16-bits wide, two
of the memory banks must be enabled, and two of the memory banks should be left
disabled. The BW(D:A) signals are low active, so setting BWA=0, BWB=0 enables banks
A and B, and setting BWC=1, BWD=1 disables banks C and D. The low active ADV/LD
signal enables the RAM chip to take a new memory address and load new data over the
data bus, and must be set low for any reading or writing to occur. The low active OE and
WEN signals should never both be low at the same time. The write enable flag can be set
to the inverse of the empty flag when the address counter has filled an even number of
times. The output enable flag can be set to be low when the address counter has filled an
odd number of times. This ensures that the WEN signal and the OE signal will never both
be active at the same time, and also that output is enabled after when the RAM is full and
writing is enabled when the memory is empty. The address counter is a 18-bit cascade
binary counter that increments once every five clock cycles in order to eliminate edge
effects so that all logic can be performed on stable signals in the third, middle, clock
cycle.
CLK
EMPTY
A 0 1
OE
WEN
ADVLD
CE1
CE2
CE3
BWA
BWB
BWC
BWD
Timing a write to the RAM from the FPGA for RAM addresses 0 and 1
Using two different counters, one for the input and one for the output was a
logical choice in order to simplify the counting logic by just enabling each at the right
time. However, Xilinx ISE would not allow this as on implementation it wanted to pack
both counters into the same place. Therefore the separate read and write counter method
would not work, and instead an 18-bit register was used to store the value of the inactive
counting (the input address count during output, and the output count during input), and
load it back to the counter when necessary.
To implement a design to handle using both of the two RAM chips a ping-pong
system needed to be developed to toggle back and forth between RAM chips. To do this
RAM A should be written to from the USB while RAM B is being read from and sent to
the FINESSE-COPPER interface.
One counter for each of the two RAM chips would be ideal as the input to RAM
and output to the COPPER could be asynchronous, but just as before Xilinx ISE would
not allow the use of multiple 18-bit counters. So instead, one counter was implemented,
enabled whenever the EMPTY flag is high, or when either of the memory chips is not
empty. Therefore there will not be any garbage data written to the COPPER from an
empty RAM chip, and the data read in, and write out are synchronous. Again with a
register to store and reload a memory address to, the design is able to write to the
COPPER when there is no data coming in from the USB, read data to the RAM when
there is no data to be written to the COPPER, and most importantly do simultaneous read
to RAM and write to COPPER operations. When the EMPTY flag changes from high to
low, the current memory address from the counter is stored so that writing to the
COPPER interface can continue, but as soon as there is data to be read in from the USB,
writing to the COPPER will stop, the current writing address is stored, the address where
reading in from the USB is loaded into the counter. Then data will be read in until the
address catches up to where writing stopped, when both will continue. This way if there
is no data to be read in, the data stored in the RAM is not stuck there, while reading data
in from the USB has highest priority.
CPLD
The CPLD needs to provide some of the configuration for the whole FINESSE
board. One of the main duties of the CPLD is to provide a 48MHz clock for all of the
components on the FINESSE board. Also the M(2:0) signals need to be set to 101 in
order for the CPLD to function. Due to lack of pin space on the FPGA the CPLD must
set the BWC and BWD pins high for the RAM B chip.
The CPLD also provides an 8-bit local bus, which can be used to send any signal
form the FPGA to testing pins to be observed on a logic analyzer. This is very important
to the testing phase of the design.
FINESSE-COPPER Interface
The interface between the daughter FINESSE card and the COPPER board will
route data from the FINESSE card to FIFOs on the COPPER board. This will allow the
COPPER board to write the data it receives to tape via network, and therefore efficiently
pass the data all the way from the USB to tape.
This interface has not yet been implemented.
Conclusion
The combination of this FINESSE card and the COPPER board will be an
accurate, efficient data pipeline from the USB to tape for data to be analyzed later. By
implementing the FINESSE card as explained above, the data will be able to pass through
the FINESSE card to the COPPER board as quickly and accurately as possible.