1
KT 6213 COMPUTER ORGANIZATION AND
ARCHITECTURE
ASSIGNMENT 1
DOUBLE DATA RATE SYNCHRONOUS DYNAMIC RANDOM
ACCESS MEMORY (DDR SDRAM)
GROUP 4
GP 00784 RIDZMAN BIN MOHAMAD SELAMAT
GP 00787 SYED AL FIRDAUS JAMALLULAIL BIN SYED AHMAD
UNIVERSITI KEBANGSAAN MALAYSIA
FAKULTI KEJURUTERAAN & ALAM BINA
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CONTENTS
1. Brief History and Specification
2. Fundamental Technology
3. Pros and Cons
4. Technical Issues
5. Future Advancement / New Ideas
6. References
7. Appendixes
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BRIEF HISTORY AND SPECIFICATION
This paper briefly described generally memory evolution and revealed the Double Data Rate
Synchronous Dynamic Random Access Memory (DDR SDRAM) technologies overview. In addition,
this paper will also give the reader an insight into possible future advancements of the computer
memory system.
Background
The general terms of Double Data Rate Synchronous Dynamic Random Access Memory (DDR
SDRAM) is as follows:
“Double Data Rate” – Two data transfers per clock cycle architecture which increases the memory
bus bandwidth and data transfer rates.
“Synchronous” – A DRAM that is synchronized with the computer's clock signal system bus.
Asynchronous DRAM depends on the changes in control input.
“Dynamic" – Every bit of the memory chip required to be refreshed in a certain periodic time to
memorize the data1. Static RAM is different to a Dynamic RAM because the SRAM uses bistable-
latching circuitry to store each bit and does not need to be refreshed periodically.
"Random Access" – The ability of the system to read or write each memory chip cells in any order.
“Memory” – Data or programs that is stored temporary or permanently in an electronic devices or
computer.
In general, computers required to copy all the data and applications to the system memory in order to
perform its tasking. Data were taken from the disk drive to the system memory which is segregated
into cache memory and main memory. Cache memory consists of static RAM (SRAM) integrated
with the processor. Main memory consists of DRAM chips on dual in-line memory modules
(DIMMs) that depend on system form factor.
History
The evolution and brief history of computer Random Access Memory (RAM) are shown in Table 1:
No Year Name / Company Event
1. 1964 Arnold Farber and Created a hard wired memory cell that consisted of
Eugene Schlig tunnel diode latch and transistor gate. The latch was
IBM later replaced by two transistors and two resistors
known as the Farber-Schlig cell.
2. 1965 Benjamin Agusta and Based on the Farber-Schlig cell, created 16-bit silicon
IBM team memory chip consisted of four diodes, 80 transistors
and 64 resistors.
3. 1966 Dr. Robert Dennard Invented DRAM.
IBM
4. 1968 Thomas J. Watson Earlier memory schemes created using capacitors.
1
Nadejda M. Victor and Jesse H. Ausubel. 2002. DRAMs as Model Organisms for Study of Technological Evolution.
Technological Forecasting and Social Change. 69(3):243-262. http://phe.rockefeller.edu/LogletLab/DRAM [26
October 2011].
4
Research Center
5. 1965 - Toshiba "Toscal" BC-1411 electronic calculator went
into production in a form of dynamic RAM built from
discrete components.
6. 1970 Joel Karp and Barbara Created Intel 1103 (1024x1.
Maness
Intel
7. 1973 Robert Proebsting Created Mostek MK4096 (4096x1), the first DRAM
with multiplexed row and column address lines.
8. 1976 - Mostek MK4116 16K DRAM introduced.
9. 1993 Samsung Samsung introduced a synchronous type of DRAM
known as SDRAM KM48SL2000.
10. 1996 JEDEC Double Data Rate DDR 1 SDRAM developed by
JEDEC (JESD79).
11. 2003 JEDEC DDR 2 SDRAM developed by JEDEC with latest
version was updated on Nov 2009 (JESD79-2F).
12. 2007 JEDEC DDR 3 SDRAM was first launched into public with
latest version was updated on July 2010 (JESD79-3E).
Table 1: Computer Random Access Memory (RAM) Evolution2
FUNDAMENTAL TECHNOLOGY
Over the past decade, DRAM (Dynamic Random Access Memory) is the main memory used for all
types of computers. In the other hand, the development of DRAM has invented Double-Data-Rate
Synchronous Dynamic Random Access Memory (DDR SDRAM) and become the latest memory
technology used by computer users worldwide.
Each DRAM cells consists of a storage capacitor and single metal-oxide-semiconductor (MOS)
transistor within an integrated circuit as illustrated in Figure 1 and Figure 2. One bit of information is
stored on each storage cell which represents by bit „1‟ and bit „0‟ represents uncharged cells. In order
to prevent the information from fading and to maintain the validity of the data, the capacitor charge
required to be refreshed periodically thousands of times each second by the dual in-line memory
modules (DIMMs) since capacitors leak charge due to the cell transistor sub-threshold current.
Figure 1: Representation of a Single DRAM Chip on a DIMM3
2
Absolute Astronomy. Dynamic random access memory. http://www.absoluteastronomy.com/topics/. Dynamic random
access memory. [26 October 2011].
3
Hewlett-Packard Development Company. 2010. Memory technology evolution: an overview of system memory
technologies. http://h20000.www2.hp.com/bc/docs/support/SupportManual/c00256987/c00256987.pdf. [25
October 2011].
5
Figure 2: DRAM Cell4
SDRAM is a DRAM that is synchronized with the computer's clock signal system bus. DDR SDRAM
is basically similar to standard SDRAM in terms of command / address protocols, connector design
and packaging but doubles the data transfer rate with the same speed and frequency of the memory
clock. The DDR SDRAM Functional block diagram is as shown in Figure 3, Appendix 1.
DDR SDRAM has evaluated through time from DDR 1, DDR 2 to DDR 3 SDRAM to increase the
data transfer rate, decrease power consumption, ability to store more data and a lot more. The system
design and capabilities are discussed as the following:
DDR 1
The first generation of DDR SDRAM is DDR 1 whereas the designers increase the memory
bandwidth 400% than a basic SDRAM, which are 3.2 GB/s increment. Other technical enhancements
being made is the low-voltage signaling Stub-Series Terminated Logic_2 (SSTL_2), strobe-based data
bus, prefetching and double transition clocking.
SSTL_2 is a 2.5 V operating voltage for DDR 1 whereas the basic SDRAM uses a 3.3 V which
decreases the power consumption and heat dissipation. DDR 1 implements a strobe-based data bus to
resynchronizes incoming data from different DIMMs and locates data more accurately. Prefetching is
a technique that uses two separate pipelines to move two bits (2n-prefetch architecture) in the memory
cell array to the I/O buffer. Double transition clocking means the ability of DDR 1 to deliver double
amount of SDRAM bandwidth by using the clock rising and falling edges to trigger data transfer to
the bus.
DDR 2
DDR2 is the second generation of DDR SDRAM technology. The memory bandwidth increased to
800% than a basic SDRAM, which are 6.4 GB/s increment. Other technical enhancements being made
is the 1.8 V operating voltage gives lower power consumption than DDR 1 and the clock runs faster
gives the DDR 2 to achieve higher performance level and data transfer rate. The DDR 2 technology is
equipped with 240 pin connector to accommodate differential strobe signals.
DDR 3
DDR3 is the third generation of DDR SDRAM technology. The memory bandwidth increased to 6.40
GB/s to 17 GB/s and the clock rates operates faster than DDR 2 from 400 MHz to 1066 MHz. DDR 3
4
Integrated Circuit Engineering Corporation. DRAM technology. Smithsonian The Chip Collection.
smithsonianchips.si.edu/ice/cd/MEMORY97/SEC07.PDF. 7-1. [25 October 2011].
6
technology is equipped with 240 pin connector to accommodate differential strobe signals same as
DDR 2 but with a different position of notch key. Other technical enhancements being made is the
ability to stores more data in the 8 bit pre-fetch buffer than DDR 2, 1.5 V operating voltage gives
lower power consumption than DDR 2 and improves the signal integrity by using the fly-by topology
for the clocks, addresses and control signals5.
Table 2, Appendix 1 summarizes the DDR SDRAM technologies in terms of the component and
module naming conventions, bus speed and the peak bandwidth of each DDR types. Module naming
conventions is determined by the data transfer clock rate.
Table 3, Appendix1 summarizes the SDRAM various types performance. The technology industry
developed rapidly through time to boost system performance as shown in Figure 4.
Figure 4: Peak Bandwidth Comparison of SDRAM and Advanced SDRAM Technologies6
PROS AND CONS OF DDR SDRAM
Pros
1. DDR SDRAM applied the double pumping method that enables the system to achieve double
the bandwidth size compared to Single Data Rate (SDR) SDRAM.
2. Dynamic RAM have a simple structure and less electronic components required rather than
Static RAM which is only one capacitor and transistor per bit.
3. DDR SDRAM utilizes less power making it suitable for laptops.
4. DDR SDRAM has high speed data transfer capabilities which is two data transfer per clock
cycle.
Cons
1. The modern DDR2 SDRAM offers security of supply, high storage capacity, low cost, and
reasonable channel bandwidth but comes with an awkward interface and complicated controller
5
Hewlett-Packard Development Company. 2010. Memory technology evolution: an overview of system memory
technologies. http://h20000.www2.hp.com/bc/docs/support/SupportManual/c00256987/c00256987.pdf. [25
October 2011].
6
Hewlett-Packard Development Company. 2010. Memory technology evolution: an overview of system memory
technologies. http://h20000.www2.hp.com/bc/docs/support/SupportManual/c00256987/c00256987.pdf. [25
October 2011].
7
issues7.
2. The vast technology evolution will results in scarcer DDR availability and computers that
applied DDR SDRAM technology would become obsolete.
3. Not all computers are compatible with DDR SDRAM technology.
4. DDR DIMM sticks only available in smaller capacities such as 512 MB and 1 GB8.
TECHNICAL ISSUES
What we can expect from figure below is that DDR3 is faster but have power consumption problem.
An increase in power consumption from 3,200 Mbps to 4,266 Mbps maximum transfer rate for
DDR4.If the power consumption of 133 SDRAM, DDR4 3,200 Mbps is about three times, DDR4
4,266 Mbps they expect to four times more power. On the other hand, based on DDR3, DDR3 1,600
Mbps (1.5V) is about 2.5 times while DDR3 2,133 Mbps (1.5V) at least three times. It shows that
power consumption would be one step further up for DDR4.
Others technical issues such as speed, point to point switching to the traditional multi-drop bus, the
reducing amount of memory per memory channel and the switch fabric in DDR4 is expected to
promote the stack of DRAM.
Figure 5: Comparison of power consumption PC-1 and 1339
7
Allan, Graham. the love/hate relationship with ddr sdram controllers. http://www.design- reuse.com/articles/13805/the-love-
hate-relationship-with-ddr-sdram-controllers.html [24 October 2011].
8
Strzeszewski, Katie. Advantages & Disadvantages of Ddr Dimm. eHow. www.ehow.com/list_5873577_advantages-
disadvantages-ddr-dimm. [12 November 2011].
9
Swinburne, Richard. 2010. DDR4: What we can expect. http://www.bit-tech.net/hardware/memory/2010/08/26/ddr4-
what-we-can-expect/. [10 November 2011].
8
FUTURE ADVANCEMENT / NEW IDEAS
Figure 6 :Memcon 10 Roadmap9
The advancement product specification for DDR4 will be out in 2012 and some discussions on its
advancement compare to previous technology discussed below:
1) Speed
a) From the Figure 6 above, the new roadmap of DDR4 is expected to scaling the
frequencies from 2,133MHz to 4.2GHz. The pre-fetch (a technique that bridges the gap of
the core and memory speed of the interface) per clock extend to 16 bits, (8 bits up from
DDR3) with internal cell frequency same as DDR2 and DDR3 to reach the target of
4GHz. However the direction is clear by inheritance of memory-based DDR which is the
concept for speed.
b) 4.2GHz DDR4 is unlikely to achieve the rack server memory even though today most
servers use only 1066 MHz DDR3 memory while pc enthusiasts are more likely twice.
2) Power
In facilitating customer migration of DDR4 voltage roadmap, VDDQ is set to be hold
constantly at 1.2V for keeping the I/O voltage to be stable10. By having the high speed DDR4
at 4.2GHZ, the power consumption is increased. Thus giving a risk especially for DDR4
where at 1.2V actually uses 4x the power of SDRAM at 133MHz at 3.3V. By scaling to 1.1V
and 1.05V it brings the power down over 3X, but still it depends to the threshold voltage of
the future manufacturing node9.
3) Density
a) DRAM manufacturers will need to dramatically increase capacities of memory chips by
using multi-layer technique with through silicon via (TSV) technology. As a result,
DDR4 memory chips with very high density will become relatively inexpensive.
Obviously, this will naturally make memory upgrades slightly more complicated as in
order to sustain multi-channel memory performance, all memory modules will have to
replaced with more advanced DIMMs11.
b) For the area capacity, by using a lot of DIMMs, considerably higher power, higher heat
and higher cost where might cause problems in enterprise computing.
10
JEDEC. Main Memory: DDR3 & DDR4 SDRAM. JEDEC Standard & documents.
http://www.jedec.org/category/technology-focus-area/main-memory-ddr3-ddr4-sdram. [11 November 2011].
11
Hassan Mujtaba. 2010. DDR4 memory in works, will reach 4.266GHz. http://wccftech.com/ddr4-memory-works-reach-
4266ghz/. [11 November 2011].
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REFERENCES
JEDEC. 2008. Double Data Rate (DDR) SDRAM. JEDEC Standard JESD79F.
JEDEC. 2009. DDR2 SDRAM Specification. JEDEC Standard JESD79-2F.
JEDEC. 2010. DDR3 SDRAM Specification. JEDEC Standard JESD79-3E.
Nadejda M. Victor & Jesse H. Ausubel. 2002. DRAMs as model organisms for study of
technological evolution. Technological Forecasting and Social Change. 69(3):243-262.
http://phe.rockefeller.edu/LogletLab/DRAM [26 October 2011].
Hewlett-Packard Development Company. 2010. Memory technology evolution: an overview
of system memory technologies. http://h20000.www2.hp.com/bc/docs/support/Support
Manual/c00256987/c00256987.pdf [25 October 2011].
Integrated Circuit Engineering Corporation. DRAM technology. Smithsonian The Chip Collection.
smithsonianchips.si.edu/ice/cd/MEMORY97/SEC07.PDF. 7-1. [25 October 2011].
Allan, Graham. the love/hate relationship with ddr sdram controllers. http://www.design-
reuse.com/articles/13805/the-love-hate-relationship-with-ddr-sdram- controllers.html [24
October 2011].
The Free Library. 1999. SDRAM memory: DRAM and beyond.
http://www.thefreelibrary.com/SDRAM+Memory:+DRAM+And+Beyond-a057603692. [26
October 2011].
Absolute Astronomy. Dynamic random access memory. http://www.absoluteastronomy.com/topics/
Dynamic random access memory. [26 October 2011].
Swinburne, Richard. 2010. DDR4: What we can expect. http://www.bit-
tech.net/hardware/memory/2010/08/26/ddr4-what-we-can-expect/. [10 November 2011].
Gervasi, Bill. 2010. Time to rethink DDR4. Discobolus Designs.
http://discobolusdesigns.com/personal/20100721a_gervasi_rethinking_ddr4.pdf. Retrieved
2011-04-29 [10 November 2011].
JEDEC. Main Memory: DDR3 & DDR4 SDRAM. JEDEC Standard & documents.
http://www.jedec.org/category/technology-focus-area/main-memory-ddr3-ddr4-sdram. [11
November 2011].
Shilov, Anton. 2010. DDR4 Memory to Feature Point-to-Point Topology. Next-Generation DDR4
Memory to Reach 4.266GHz - Report. http://www.xbitlabs.com/news/memory/display
/20100816124343. [11 November 2011].
Hassan Mujtaba. 2010. DDR4 memory in works, will reach 4.266GHz. http://wccftech.com/ddr4-
memory-works-reach-4266ghz/. [11 November 2011].
Strzeszewski, Katie. Advantages & Disadvantages of Ddr Dimm. eHow.
www.ehow.com/list_5873577_advantages-disadvantages-ddr-dimm. [12 November 2011].
10
APPENDIXES
Figure 3: DDR SDRAM Functional Block Diagram12
12
JEDEC. 2008. Double Data Rate (DDR) SDRAM. JEDEC Standard JESD79F.
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Type Component Naming Module Naming Bus Speed Peak Bandwidth
Convention Convention
DDR1 DDR200 PC1600 100 MHz 1.6 GB/s
DDR266 PC2100 133 MHz 2.1 GB/s
DDR333 PC2700 166 MHz 2.7 GB/s
DDR400 PC3200 200 MHz 3.2 GB/s
DDR2 DDR2-400 PC2-3200R 200 MHz 3.2 GB/s
DDR2-533 PC2-4300 266 MHz 4.3 GB/s
DDR2-667 PC2-5300 333 MHz 5.3 GB/s
DDR2-800 PC2-6400 400 MHz 6.4 GB/s
DDR3 DDR3-800 PC3-6400 400 MHz 6.4 GB/s
DDR3-1066 PC3-8500 533 MHz 8.5 GB/s
DDR3-1333 PC3-10600 667 MHz 10.6 GB/s
DDR3-1600 PC3-12800 800 MHz 12.8 GB/s
Table 2: Summary of DDR SDRAM Technologies13
SDRAM DDR SLDRAM RDRAM Concurrent Direct
SDRAM RDRAM RDRAM
Peak 125MB/sec 200MB/sec 400MB/sec 600MB/sec 600MB/sec 1.6
Bandwidth GB/sec
MHz 125MHz 200MHz 400MHz 600MHz 600MHz 800MHz
Standard JDEC JDEC SLDRAM Rambus Rambus Rambus
Body Consortium
Availability 1997 1998 1999 1995 1997 1995
Voltage 3.3V 3.3V 2.5V 3.3V 3.3V 2.5V
Table 3: DRAM Various Types Performance14
13
Hewlett-Packard Development Company. 2010. Memory technology evolution: an overview of system memory
technologies. http://h20000.www2.hp.com/bc/docs/support/SupportManual/c00256987/c00256987.pdf. [25
October 2011].
14
The Free Library. 1999. SDRAM memory: DRAM and beyond.
http://www.thefreelibrary.com/SDRAM+Memory:+DRAM+And+Beyond-a057603692. [26 October 2011].