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PCI

VIEWS: 14 PAGES: 73

									Introduction to PCI System
       Architecture
 Introduction to PCI System
                Direct-Connect Approach(VESA)
                                                                             Main memory


                CPU             Local Bus    Cache       Memory Bus




                                Local Bus
                                Device                   Expansion
                                                         Bridge
Local Bus Design Constraint:
1. Redesign is necessary for                                     Expansion Bus
   next generation processor.
2. Only one local device is                              X-Bus Buffer
   permitted.                                                                    Expansion
                                                                                 Connectors
3. Design of local bus inter
  -face is difficult.
                                                           X-Bus
4. Transfer with one device
   is not permitted while the
   local bus is involved in a
   transfer with another                    I/O Device    I/O Device    I/O Device
   device.
                         Buffered Approach(VESA)


             CPU          Local Bus       Cache      Memory Bus




                          Bus Buffer                 Expansion
                                                     Bridge

                     Buffered Local Bus                      Expansion Bus

                I/O        I/O         I/O           X-Bus Buffer
                Device     Device      Device


                                                       X-Bus
A maximum of three local
bus devices can be placed on
the buffered local bus.                 I/O Device    I/O Device    I/O Device
                  Workstation Approach(PCI)
                                                                  Main          Video
                                                                                Memory
                                                                  Memory

CPU        CPU Local Bus   Host/PCI
                                           Memory Bus
                           Cache/Bridge
                                                                              Motion
                                                                Audio         Video
                                                                              Peripheral
                                                                Peripheral

                                 PCI Bus
                           LAN              Expansion Bus          Graphics
  SCSI Host                Adapter          Bridge
  Bus Adapter                                                      Adapter

                           LAN
                                                                              Video Frame Buffer
SCSI BUS




                Disk
                                                   Expansion Bus
                Tape
                                          Bus           I/O            Memory
                CD                        Master        Slave          Slave
                ROM
       Transfer Rate Comparison:

Bus    Bus Frequency     Transfer           Transfer Rate
ISA    8.33 MHz          2 byte / 2 clock   8.33 MB/s
EISA   8.33 MHz          4 byte / 1 clock   33 MB/s
                         ( Burst Mode)
VESA   33 MHz            4 byte / 1 clock   132 MB/s
                         ( Read, Burst )
                         4 byte / 2 clock    66 MB/s
                         ( Write, Burst )
PCI    33 MHz            4 byte / 1 clock    132 MB/s
                         8 byte / 1 clock    264 MB/s
       66 MHz            4 byte / 1 clock    264 MB/s
                         8 byte / 1 clock    528 MB/s
                         ( Burst Mode )
• PCI: Peripheral Component Interconnect
• Major PCI Revision 2.1 Features
     Processor Independence
     Support for up to 256 PCI functions per PCI bus
     Low power consumption ( Draw as little current as possible )
     Burst used for all read and write transfers
     Supports 66 MHz operation, 64bit bus width
     Fast access ( 60ns at bus speed 33 MHz )
     Concurrent bus operation
     Bus master support
     Hidden bus arbitration
     Low pin count ( Initiator:49pins, Target:47 pins )
     Transaction integrity check( Parity check)
     Three address spaces ( Memory, I/O, Configuration )
     Auto configuration( Configuration register )
     Software Transparency
                     PCI-Compliant Device Signals                For Slave only
                                                                 For Master only
               Required Signals               Optional Signals

                 AD[31:00]                      AD[63:32]

Address/Data
and Command                                                          64-bit
                 C/BE[3:0]#         PCI         C/BE[7:4]#
                                                                     Extension
                                  COMPLIANT
                    PAR                         PAR64
                                   DEVICE
                                                REQ64#
                   FRAM#                        ACK64#
                   TRDY#                         LOCK#
 Interface                                                       Atomic Access
                   IRDY#
 Control           STOP#                        INTA#
                   DEVSEL#                      INTB#
                                                INTC#
                                                                     Interrupt
                   IDSEL                                             Request
                                                INTD#
 Error             PERR#                        CLKRUN#          Clock Control
 Reporting         SERR#                         SBO#               Snoop
                   REQ#                          SDON
 Arbitration                                                        Result
                   GNT#                          TDI
                                                TDO
                   CLK                          TCK
 System            RST#
                                                                     JTAG
                                                TMS
                                                TRST#
 PCI Bus Arbitration
                                      Initiator/ Target

 Initiator ( Master ): The device that initiates a transfer
 Target ( Slave ): The device that currently addressed by the initiator for
                    the purpose of performing a data transfer


                                             PCI
                                            Arbiter
                             GNT0#
                                          GNT1#         GNT2#                 GNT3#


               REQ0#           REQ1#        REQ2#               REQ3#


                    PCI           PCI               PCI               PCI
                   Device        Device            Device            Device
                            MASTER


                             Address, Command/
                PCI          Data, Byte Enables/            Bridge            DRAM
               Device
                             Parity
              SLAVE                                         SLAVE              SLAVE
                        PCI Bus Arbitration Algorithm


                     First Group



                        Master A                             Master X

                                  Second
               Master B           Group             Master Y       Master Z



                   A    B     X     A   B   Y   A    B   Z     A   B    X

• Fairness ( fixed, rotational )
• Bus Parking( on specified master, on last master that acquired the bus )
• Hidden Bus Arbitration( REQ#, GNT#)
• LT ( Latency Timer ): The minimum amount of time that the bus master is
                            permitted to retain ownership of the bus
             Example of PCI Bus Arbitration Between Two Masters
                              ( Master B has higher priority than Master A)

                          1    2         3         4      5    6     7       8          9   10        11      12


       CLK
     REQA#
( Master A -> Arbiter )
     REQB#
( Master B -> Arbiter )
     GNTA#
( Arbiter -> Master A )
     GNTB#
( Arbiter -> Master B )
                                             LT not expired
    FRAME#
( Master -> Target )
      IRDY#
( Master -> Target )
     TRDY#
( Target -> Master )
         AD                        ADDRESS     DATA    DATA   DATA       ADDRESS     DATA        ADDRESS   DATA
( Master <-> Target )

                                     A                                           B                A
 Arbitration for Fast Back-To-Back Accesses


          1        2       3      4       5     6   7   8
CLK


REQ#-

GNT#

FRAME#


AD            ADDRESS   DATA   ADDRESS   DATA




IRDY#

TRDY#


DEVSEL#
                           Delayed Transaction
 Delayed Transaction
   Request Phase: Target latches the request and issues retry

    Completion Phase: Transaction completes on the target bus


         MTXC        Target cannot respond within 16 clocks:
Master
                    1. Address, Command, Byte Enables latched by PIIX4
                    2. Retry issued to MTXC
Target   PIIX4      ( Request Phase )

                    3. Requested data fetched in buffer ( Completion Phase )

                     4. Master Retries the transaction with the
          ISA          same address, command, data
         Device
                   OR no Retry within 215 clocks    Discard the data
Commands That can Use Delayed Transactions


       Interrupt Acknowledge
       I/O Read
       I/O Write
       Memory Read
       Memory Read Line
       Memory Read Multiple
       Configuration Read
       Configuration Write
 The PCI Commands
              PCI Command Types
C/BE#[3:0] is used to indicate the command or
transaction type during the address phase

C/BE[3::0]#                Command Type

0000                       Interrupt Acknowledge
0001                       Special Cycle
0010                       I/O Read
0011                       I/O Write
0100                       Reserved
0101                       Reserved
0110                       Memory Read
0111                       Memory Write
1000                       Reserved
1001                       Reserved
1010                       Configuration Read
1011                       Configuration Write
1100                       Memory Read Multiple
1101                       Dual Address Cycle
1110                       Memory Read Line
1111                       Memory Write and Invalidate
                         PCI Interrupt Acknowledge Transaction

                                      1         2         3            4   5

                       CLK

                 FRAME #
 ( Host Bridge -> INT Controller )
                         AD                Stable               VECTOR
                                           Pattern
( Host Bridge < -> INT Controller )
                     C/BE #                             Byte Enables
                                          INT ACK CMD
  ( Host Bridge -> INT Controller )
                     IRDY #


                     TRDY #


                     DEVSEL #

 ( INT Controller-> Host Bridge )

                     GNT #
Message Code Message Type
( on AD[15:0]                      The Special Cycle Transaction( Halt / Shut Down)
    0000h        Shut Down
                                                  Terminated with Master Abort
    0001h        Halt
    0002h        x86-specific
                                             1       2        3       4   5   6   7    8
                 message
                                   CLK
 0003h-ffffh     Reserved

                                FRAME#
• For an initiator to
                                                 Stable
  broad- cast a message AD[31:0]                 Pattern   Message

  to one or more targets.
                                C/BE#[3:0]       Special    Byte
                                                  Cmd       Enables
• Message type
  on AD[15:0]                   IRDY#


• Message-dependent
                                TRDY#
 data field on AD[31:16]

                            DEVSEL#
• Byte Enable on
  C/BE#[3:0]                GNT#
                                                                                  7 clocks
 The Read and Write Transfers
                                      Read Transaction
                                       ( 33.33 Mb/s )

CLK
               1          2       3           4          5          6            7        8         9

FRAME#

                                                  Wait state for bus ownership

AD                    ADDRESS            DATA-1                DATA-2            DATA-3



C/BE#
                      BUS CMD   BYTE ENABLES          BYTE ENABLES         BYTE ENABLES


IRDY#
                                                                  One more clock before
                                                                  initiator ready to receive data
TRDY# Avoid bus
         contention
                                          Some time is needed for
                                          fetching data
DEVSEL#

                      ADDRESS         DATA                DATA                   DATA
                       PHASE          PHASE               PHASE                  PHASE
                                       Optimized Read Transaction
                                                   ( 132 Mb/s)
                                   1       2      3        4        5         6     7   8
Burst Transfer:           CLK

1. If target memory is
  cacheable.             FRAME#

2. If target memory is   AD            Address        Data1     Data2     Data3
  prefetchable
                                       BUS                      Byte      Byte
                         C/BE#                   Byte Enables   Enables   Enables
                                       CMD


                         IRDY#


                         TRDY#


                         DEVSEL#

                         GNT#
                                  Write Transaction
                                    ( 44.44 Mb/s )
CLK
          1      2         3          4            5     6       7      8   9

FRAME#



AD            ADDRESS     DATA-1          DATA-2               DATA-3



C/BE#
              BUS CMD   Byte EN    Byte EN             BYTE ENABLES


IRDY#



TRDY#


DEVSEL#
              Optimized Write Transaction
                            ( 132 Mb/s)
          1       2        3         4         5      6   7   8
 CLK


FRAME#

AD            Address   Data1     Data2     Data3


              BUS       Byte      Byte      Byte
C/BE#                   Enables   Enables   Enables
              CMD


IRDY#


TRDY#


DEVSEL#

GNT#
                             Addressing

 • Addressing Sequence During Memory Burst
    Linear ( or Sequential ) address mode
    Cache Line wrap mode
   AD1     AD0              Addressing Sequence
    0        0                  Linear
    0        1                  Reserved
    1        0                  Cacheline wrap
    1        1                  Reserved



• PCI I/O Addressing
   AD[31:2] : Target DW of I/O space
   AD[1:0] : The Least-significant byte within the DW that the
    initiator wishes to transfer with ( 00 = byte 0, 01 = byte 1 )
 64 bit PCI Extension
  REQ64#, ACK64#, PAR64,
   AD[64::32], C/BE[7::4]
                   64-bit Read Request with 64-bit Transfer

    CLK       1       2     3      4     5        6    7        8   9
 FRAME#

  REQ64#

AD[31::00]        ADDRESS       DATA-1        DATA-3   DATA-5


AD[63::32]                      DATA-2        DATA-4   DATA-6


C/BE[3::0]#       BUS CMD                BE# ‘s

C/BE[7::4]#                              BE# ‘s

    IRDY#

    TRDY#

  DEVSEL#

   ACK64#
                    64-bit Write Request with 32-bit Transfer

      CLK     1       2         3          4      5   6          7   8   9

  FRAME#
   REQ64#
                  ADDRESS   DATA-1     DATA-2               DATA-3
 AD[31::00]
                            DATA-2
 AD[63::32]
                  BUS CMD   BE# ‘s-1   BE# ‘s-2       BE# ‘s-3
C/BE[3::0]#
                            BE# ‘s-2
C/BE[7::4]#
    IRDY#
    TRDY#
 DEVSEL#
   ACK64#
                    64-bit Dual Address Read Cycle

      CLK     1       2         3   4       5           6       7    8
  FRAME#

AD[31::00]        LO-ADDR HI-ADDR       DATA-1              DATA-3


C/BE[3::0]#       DUAL AD BUS CMD          BE# [3::0]

AD[63::32]            HI-ADDR           DATA-2              DATA-4


C/BE[7::4]#           BUS CMD             BE# [7::4]

    IRDY#

   TRDY#

 DEVSEL#

   REQ64#

   ACK64#
 Premature Transaction Termination
                    Master Initiated Termination

 Reasons

   Transaction completed normally ( Not premature transaction termination )


   Initiator been preempted ( GNT# removed )
     Preemption during timeslice by another bus master
     Timeslice expiration followed by preemption


   Master abort
     No target respond to the address ( DEVSEL# not asserted)
        No device resides at the address
        Special cycle
        Configuration accessing a non-existent target
   Preemption
                           1     2     3   4   5   6      7
    Example
                   CLK
   Preempted
                  GNT#

                  FRAME#
                                                   Internal LT time out sensed

                  IRDY#

                  TRDY#



  Timer           CLK
  Expiration
  Example         GNT#
                           Preempted

                  FRAME#
Time out sensed
                  IRDY#

                  TRDY#
  Example of Master-abort on Single-Data
            Phase Transaction


           1      2      3       4       5        6    7   8
CLK


FRAME#



IRDY#


TRDY#

DEVSEL#                Fast   Medium   Slow   Bridge




        Master Abort : Target doesn’t claim transaction
                  Target Initiated Termination( STOP# )
 Disconnect
   Reasons
     Target slow to complete a data phase which is neither the first nor
       the final data phase ( more than 8 PCI clocks )
     Targets don’t support burst mode
     Memory target doesn’t understand address sequence
     Transfer cross over target’s address boundary
     Burst memory transfer crosses cache line boundary

 Retry    ( if the target cannot permit any data to be transferred )

   Reasons
    Target very slow to complete first data phase ( Greater than 16 PCI clocks )
    Snoop hit on modified cache line
    Resource busy
    Memory target locked
 Target Abort     ( if the target detects fatal error )

   Reasons
     Broken Target
     I/O addressing error
     Address phase parity error
     Master abort on other side of PCI-to-PCI bridge
                Type A Disconnect                    Type B Disconnect
     Know in advance that the next data transfer takes more than 8 PCI clock
            1       2       3      4             1       2      3   4
    CLK                                 CLK



   FRAME#                               FRAME#



   IRDY#                                IRDY#



   TRDY#                                TRDY#


   STOP#                                STOP#




  DEVSEL#                              DEVSEL#


                         Data                         Data
                        Transfer                     Transfer

TRDY# asserted, STOP# asserted,        TRDY# asserted, STOP# asserted,
DEVSEL# asserted, IRDY# deasserted     DEVSEL# asserted, IRDY# asserted
            Type C Disconnect                           Type C Disconnect
           with IRDY# Asserted                       without IRDY# Asserted
                   Current data transfer takes more than 8 PCI clock
            1      2     3       4                    1     2        3   4
 CLK                                        CLK


FRAME#                                      FRAME#



IRDY#                                       IRDY#


TRDY#                                       TRDY#


STOP#                                       STOP#



DEVSEL#                                    DEVSEL#



         Data      TRDY# deasserted, STOP# asserted        Data
        Transfer                                          Transfer
                             DEVSEL# asserted
            Retry Received                           Retry Received
          With IRDY# Asserted                    Without IRDY# Asserted
          1    2      3     4                     1     2         3   4
 CLK                                     CLK


FRAME#                                  FRAME#



IRDY#                                   IRDY#


TRDY#                                   TRDY#


STOP#                                   STOP#



DEVSEL#                                 DEVSEL#

                     TRDY# deasserted, STOP# asserted
              No Data                                  No Data
              Transfer     DEVSEL# asserted            Transfer
                        Occurs in the first data phase
                                                    Target Abort Example

                                                             1     2     3      4
                                                  CLK


                                                 FRAME#
 Master’s response to target abort:
•   Generates an interrupt to alert is related   IRDY#

    device to check its status.
                                                 TRDY#
• Generates SERR#

                                                 STOP#



                                                 DEVSEL#



                                                 TRDY# deasserted, STOP# asserted
                                                           DEVSEL# deasserted
 Shared Resource Acquisition
              Shared Resource Acquisition



• LOCK#
   Usage : Perform read/modify/write of a memory
    semaphore as an atomic series to avoid
    Synchronization Problem.

  Solutions:
   Bus LOCK      : Permissible but not preferred
   Resource LOCK: Preferred
                                Starting an Exclusive Access
                                  ( Establishing LOCK#)

              CLK        1      2            3           4            5
          FRAME#
 ( Master -> Target )
            LOCK#
 ( Master -> Target )
                AD           ADDRESS                    DATA
( Master < -> Target )
             IRDY#
 ( Master -> Target )
            TRDY#
 ( Target -> Master )
         DEVSEL#
 ( Target -> Master )
              GNT#
 ( Arbiter -> Target )
              LOCK# Mechanism Availability:
                Do not assert REQ# if LOCK# is currently asserted.
               If FRAME# and LOCK# are deasserted, assert its REQ#.
                The master continue to monitor LOCK# while waiting for GNT#.
                 If LOCK# is sampled asserted, the master deasserted its REQ#.
               When the master samples bus idle ( FRAME# & IRDY# deasserted)
                and LOCK# deasserted, it has acquisition of the bus and of the
                LOCK#.
              Accessing a Locked Agent : Retry
          1          2             3             4              5
   CLK

FRAME#

 LOCK#                    (driven low by master holding lock)


                ADDRESS                DATA
    AD

  IRDY#

 TRDY#

  STOP#

DEVSEL#

  GNT#                                        Retry
  Continuing & Completing an Exclusive Access
          1       2     3        4         5
   CLK

FRAME#
                                        Release

 LOCK#                                  Continue


              ADDRESS          DATA
    AD

  IRDY#

 TRDY#

DEVSEL#

  GNT#
 Error Detection and Handling

    When Parity Error occurs:
     Configuration status register   : DETECTED PARITY ERROR
     Configuration command register: PARITY ERROR RESPONSE
     Assert PERR#

    Devices excluded from PERR# Requirement
       Chipsets
       Devices that don’t deal with OS/Application program or data
                        Parity on Read Transaction
          1       2           3          4         5            6           7        8           9
  CLK


 FRAME#

 AD           Address                 1st       2nd                   3rd Data
                                      Data      Data

              BUS         1st Byte   2nd Byte 3rd Byte
 C/BE#                    Enables    Enables Enables
              CMD

                        Add phase            1st Data    2nd Data
 PAR                     parity               parity      parity          3rd Data Parity
                                                                                    3rd phase PERR#
                                                                                  earliest       latest
 PERR#                                                    1st phase   2nd phase
                                                           PERR#       PERR#


IRDY#

TRDY#


DEVSEL#
                Parity on Write Transaction
          1       2           3          4           5           6         7          8         9
  CLK


 FRAME#

 AD           Address      1st        2nd                   3rd Data
                           Data       Data

              BUS         1st Byte   2nd Byte
 C/BE#                    Enables    Enables         3rd Byte Enables
              CMD

                        Add phase 1st Data      2nd Data
 PAR                     parity    parity        parity          3rd Data Parity
                                                                          3rd phase PERR#
                                                                        earliest       latest
 PERR#                                          1st phase   2nd phase
                                                 PERR#       PERR#


IRDY#

TRDY#


DEVSEL#
 Configuration Related Issues
Configuration Address Space Format
           Byte Number
       3       2      1      0
                                 00
           Configuration
           Header Space
                                 15




                                      Double Word Number
                                 16



           Device Specific
           Configuration
             Registers




                                 63
                          Configuration Registers
                     Type 0 Configuration Space Header
                31                          16 15                          0
Required                 Device ID                       Vendor ID             00h
configuration                                            Command
                         Status                                                04h
registers
                                  Class Code                  Revision ID      08h

                                  Header Type       Latency   Cache Line
                      BIST                                                     0Ch
                                                     Timer       Size
                                                                               10h
                                  Base Address Registers


                                                                               24h
                                   Cardbus CIS Pointer                         28h
                        Subsystem ID            Subsystem Vendor ID            2Ch

                               Expansion ROM Base Address                      30h
                                         Reserved                              34h
                                         Reserved                              38h
                     Max_Lat       Min_Gnt Interrupt Pin Interrupt Line 3Ch
 Command Register Bit Assignment
                         15                            10   9    8   7    6   5    4    3   2   1   0
                                   Reserved
                         Fast Back-to-Back Enable
                                        SERR# Enable
                                Wait Cycle Control
                               Parity Error Response
                              Palette Snoop Enable
                Memory Write and Invalidate Enable
                        Special Cycle Monitoring
                                     Enable Mastering
                              Memory Access Enable
                                   I/O Access Enable
 Status Register
           15    14   13 12   11   10     9   8   7     6   5    4                      0
                                                                       Reserved
                                                                66MHz-Capable
                                                                UDF Supported
                                                                Fast Back-to-Back Enable
                                                                Data Parity Reported
                                                                DEVSEL Timing
                                                                Signaled Target Abort
                                                                Received Target Abort
                                                                Received Master Abort
                                                                Signaled System Error
                                                                Detected Parity Error
 Class Code Register
          23                16 15            8   7               o

               Class Code    Sub-Class Code Prog I/F


           Basic function      More specific          Device specific
                               device subclass        programming
                                                      interface

 Eg.             06h                01h                    00h
           Bridge device                  PCI/ISA bridge


 Header Type Register
           7           6                                         0

                                    Header Type

                                                     Configuration Header Format
                                                      0 = single function device
                                                      1 = multi function device
 BIST Register
                    7        6       5     4      3             0

                                  Reserved Completion Code

                                               Start BIST
                                               BIST Capable

 Memory Base Address Register
                 31                                             4 3 2 1 0
                                    Base Address                        0
                                         Prefetchable
                                                Type
                                       Memory space
                                       indicator

    Bits 2-1
      00       Base register is 32 bits wide and can be mapped anywhere in the 32-bit memory space.
      01       Base register is 32 bits wide must be mapped below 1M in memory space.
      10       Base register is 64 bits wide and can be mapped anywhere in the 64-bit memory space.
      11       Reserved

     Bit 3 : set 1 if prefetchable, set 0 otherwise
 I/O Base Address Register
           31                                                               2 1 0
                                     Base Address                               1
                                       Reserved
                                       I/O space
                                       indicator



 Expansion ROM Register

                31                                                11   10              1   0

                     Expansion ROM Base Address (Upper 21 bits)             Reserved


                               Address decode enable
                         Configuration Transactions

• Usage: Access PCI configuration registers
      A PCI device or host/PCI bridge require 64 doubleword of config. register
       Each PCI function requires 64 doubleword of config. register
• Transaction type:
 1. Type 0 configuration read or write transaction
 2. Type 1 configuration read or write transaction
 3. Memory mapped configuration mechanism ( PowerPC )


• Configuration mechanism:
 1. Mechanism 1 ( Preferred)
 2. Mechanism 2
   Peer Host/PCI Bridges                                  System
                                                          Memory


                                  Processor
                                                          Memory
                                                          controller


                                               Host Bus

                            Bridge A                        Bridge B

                            PCI Bus 0                                  PCI Bus 4

   Expansion
   Bridge       Bridge D      PCI Device       Bridge E     PCI Device     Bridge C
                              PCI Bus 0
                                                            PCI Bus 0

Expansion bus   PCI bus 1                     PCI bus 3                   PCI bus5


                Bridge C



                PCI bus 2
                  Type 0 Configuration Transaction
    • Two 32 bit I/O ports are utilized at I/O address:

      CONFIG_ADDRESS PORT: 0CF8 h - 0CFB h
      CONFIG_DATA PORT              : 0CFC h - 0CFF h


   • Configuration Address Register at 0CF8h

              31 30       24 23         16 15       11 10    8 7           2 1 0
                                  Bus      Device      Function     DW
                Reserved                                                     0 0
1 = Enable
                          Number Number Number                     Number
Configuration
space mapping 0CFBh      0CFAh      0CF9h                          0CF8h

   • Contents of the AD bus during address phase

              31 30                              11 10       8 7           2 1 0
                                                       Function     DW
                            Reserved                                         0 0
                                                       Number      Number
               0CFBh        0CFAh               0CF9h              0CF8h
                     Implementation of IDSEL

          31 30         24 23         16 15          11 10      8 7         2 1 0
                                Bus      Device         Function       DW
              Reserved                                                         0 0
                            Number Number Number                      Number


                                         Decoder
                  Device Number
          16 15 14 ……….           1 0


          31 30      ……..             16 15          11 10      8 7         2 1 0

                      ……..                              Function       DW
                                                                               0 0
                                                        Number        Number



  IDSEL                   IDSEL                              IDSEL                   IDSEL
                                              ....
PCI Slot 4             PCI Slot 3                      PCI Slot 2               PCI Slot 1
               Type 0 Configuration Read Access
           1         2       3         4    5   6   7   8   9
   CLK


  FRAME#

  AD           Address               Data


  C/BE#        Config Read   Byte Enables
                  CMD



 IRDY#


 TRDY#


IDSEL#




GNT#
     Configuration              START
     Mechanism 1
                           Processor write to     Pass PCI-to-PCI bridge
                           config. address reg.
                           at I/O port 0CF8
                                                  Target bus in the range

                           Host/PCI bridge


                                                        Bus num the         YES
                     YES
                             Bus num the                   same
                                same
                                                        NO
                                    NO                         Type 0 configuration
Type 0 configuration read                                      read or write at config.
or write at config. data                                       data port 0CFC
port 0CFC
                                                       Type 1 config.
                            Type 1 config.              transaction
                             transaction
 Interrupt Related Issues
• Value to be Hardwired into Interrupt Pin Register
       Interrupt Signal Bonded To         Value Hardwired In Pin Register
       Device doesn’t generate interrupts           00h
                INTA# pin                           01h
                INTB# pin                           02h
                INTC# pin                           03h
                INTD# pin                           04h


• Interrupt Line Register Values

    System IRQ Line Interrupt Routed to   Value to be Written In Line Register
                     IRQ0                                0d
                     IRQ1                                1d
                     IRQ2                                2d

                     IRQ15                               15d
        Interrupt Design
          Programmable
INTA#
          Interrupt router


INTA#
INTB#
                                 Slave

            INTA#                8259
INTA#
            INTB#
            INTC#
                       IRQ8-15
INTA#
INTB#       INTD#
INTC#
INTD#



INTA#                                    Master
                                         8259


INTA#
INTB#                        IRQ0-7


INTA#
           Interrupt Chaining

Device          8259

              IRQ 1          Entry 1      ISR 1
 INT A

 INT B        IRQ 2          Entry 2      ISR 2




If INT A and INT B both routed to IRQ1:


                                          ISR 2 with
 INT B         IRQ 1          Entry 2     Entry 1
                                          embedded
 PCI Cache Support
• Snoop
  SDONE : snoop done
  SBO# : snoop backoff. ( HITM when assert.)
• The non-cacheable transaction is regardless of SDONE and SBO#.
• Write Through : only use SDONE




• Memory Target Interpretation of Snoop Result Signal from Bridge

          SDONE    SBO#           Description
             0      X             Standby
             1      1             Clean snoop
             1      0              Hit on a modified line
         Wait States Inserted Until Snoop Completes

 CLK
           1      2      3   4      5   6

FRAME#


               ADDRESS       DATA
   AD


 IRDY#


TRDY#


 SDONE



 SBO#
              Hit to a Modified Line Followed by the Writeback

   CLK
          1       2      3      4      5    6             A       B        C
FRAME#
                                                         writeback transaction
               ADDRESS       DATA-1                   ADDRESS DATA-1   DATA-2
    AD

  IRDY#


 TRDY#

DEVSEL#

 STOP#

 SDONE

  SBO#

               STANDBY        HITM    HITM HITM   HITM CLEAN     STANDBY
 Expansion ROMs
Purpose:
  device-specific power-on self-test code
  device-specific initialization code
  device-specific interrupt routine
  device-specific BIOS routine
  device-specific code to be executed during the system boot process



ROM Detection:
   Check if Expansion       yes        Read if the first two    yes
   ROM base address                 locations on base address         ROM exist
     register exist                  register contain 55AAh



                        Code image copied to system DRAM
                            Execute initialization code
 Code Image Format                     Header

                                      Data structure            Runtime Module
                                                                within the Image
                                      Runtime Code

                                  Initialization Code
                                   (Can be discarded
                                    after execution)
                                             Checksum

                                      Unused space


 PCI Expansion ROM Header Format

       Offset    Length Value         Description
         0h        1h    55h    ROM Signature,byte 1
         1h        1h    AAh    ROM Signature,byte 2
        2h-17h    16h    XX     Reserved(processor architecture unique data)
       18h-19h     2h    XX     Pointer to PCI Data Structure
 Unique Data Area in ROM Header


      Offset     Length                      Description
       02h        1       Overall size of the image
       03h-05h    3       Entry point for the initialization code
                          ( POST performs a far call to initialize the device)

      06h-17h     18      Reserved
         PCI Data Structure Format

Offset   Length            Description
0h        4        Signature, the string “PCIR”
4h        2        Vendor Identification
6h        2        Device Identification
8h        2        Pointer to Vital Product Data
Ah        2        PCI Data Structure Length
Ch        1        PCI Data Structure Revision
Dh        3        Class Code
10h       2        Image Length
12h       2        Revision Level of Code/Data
14h       1        Code Type
15h       1        Indicator (Bit 7, “1” last image)
16h       2        Reserved

								
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