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					Digital TVs
• Introduction and market overview
• System overview
• Xilinx value proposition for Digital TV
   –   Forward Error Correction   –   PCI
   –   MPEG                       –   Data Encryption
   –   Memory Interface           –   Color Space Conversion
   –   IEEE-1394                  –   LVDS
                                  –   Clock Generation/Distribution
   –   USB 2.0
• Summary
Introduction &
Market Overview
  The Digital Age of
Consumer Electronics
           Digital technology brings
                     Higher accuracy
                     Higher reliability
                     Faster speed
                 01010101010 11101000
                     Lower power
                     Lower cost
                  0 1
                01 0   0100010001010101
Digital Logic Spawns New
   Consumer Products
          Digital TV
             Revolutionizing the way we watch
                         Consumer Satellite Modems
                                  Revolutionizing high speed home
                                  Internet access

                                              Desktop Video Editing
                                                 Delivering video editing to the

                                                      MP3 Players
                                                        The new revolution
   Smart Card                                            in portable
     Revolutionizing the way we                         digital music
     purchase products
      ASICs & ASSPs Cannot Meet
     Consumer Market Requirements
                                                                                   AAC or ?
•   Short Product Life Cycles                                          CD
    Changing Standards

                                Market Size ($)
•                                                             Tapes
•   Multiple Standards                            Vinyl LPs
•   Rapidly Evolving Features


                                                     VCR                          VCR+
 Convergence Is Happening!
• Invisible computing embedded within everyday devices
   – Increasing intelligence of everyday appliances
• Digital revolution
   – Infrastructure: Circuit-switched to IP-based networks
   – Analog TV to Digital TV
• Internet is ubiquitous
   – Being deployed within commercial channels
       • Business-to-Business commerce, secure transaction processing,
• Deregulation of global infrastructure
   – Multiple industries such as telecom, cable and utilities
  Integrated Digital TV (iDTV)
• Currently need either iDTV or set-top box to receive digital
  television broadcasts
    – iDTV is basically a TV with an integrated set-top box
• Signals received via normal TV aerial, satellite dish or cable
    – Depends on condition and type of antenna
    – Free-to-air and pay channels available
    – Maybe xDSL?
• Connection or return channel for consumer interaction
    – e.g. POTS/ISDN/Cable
• Analog broadcasts WILL switch off at some point in time!
    – Within 10 years?
        • e.g. aiming for end 2006 in US, 2010 in UK
    – High broadcast coverage required to minimize im pact on consumers
• High Definition Television offers the consumer
  unprecedented broadcast picture quality and digital
  surround sound
• Six times the current standard broadcast resolution in
   – i.e., there are 6 times as many pixels in the same picture
• HDTV sets are typically large scale, wide-screen, home-
  cinema, entertainment centers
• Success of HDTV still dependent on attractive content
  provision and lowering set costs (amongst other things!)
• HDTV - High Definition TV
   – 720p vertical scanning lines or higher
   – 1920x1080i is true HDTV
   – 16:9 aspect ratio
• EDTV - Enhanced Definition TV
   – 480p vertical scanning lines or higher
   – Aspect ratio not specified
• SDTV - Standard Definition TV
   – Digital reception but can be less than EDTV resolution
   – Aspect ratio not specified
   Digital TV Display Types

                                            Cathode Ray Tube (CRT)
                                    Organic Light Emitting Device (OLED)
                                    Liquid Crystal on Silicon (LCOS)
       Plasma Display Panel (PDP)          Digital Light Processor (DLP)
    Field Emission Display (FED)
Liquid Crystal Display (LCD)
     Receivers and Monitors
• DTV Receiver
   – Able to decode/process and display DTV broadcasts
   – These sets have an internal tuner circuit which allows it to
     receive DTV broadcast signals and display them in their
     standard or high-definition format
• DTV Monitor
   – Has no internal processing so it requires a set-top box or
     connection to a processing module
   – Is capable of displaying standard or high-definition images as
     required by DTV standards
Interlace/Progressive Scan
First all odd lines scanned (1/60sec)     then all even lines (1/60sec)       presenting a full picture (1/30sec)

  All lines scanned in single pass      presenting a full picture (1/60sec)
      Aspect Ratio
            • The ratio between picture width
              and height
            • 16:9 more closely represents
4:3           cinema picture formats
            • Digital TV receivers must be
              able to cope with different
              ratios and automatically
              present a picture dependent on
              the display format used
16:9        • Aspect Ratio Conversion
              (ARC) is a common function in
              modern TV sets
Aspect Ratio Conversion

 HDTV Source 16:9    Normal 4:3    Letterbox

  Pan & Scan        Zoom/Window   Anamorphic
     Ratios and Resolutions

Courtesy: Snell & Wilcox
                     ATSC Table III
                   Scanning Formats
Definition    Lines/Frame Pixels/Line Aspect Ratios                   Frame Rates
High (HD)         1080       1920         16:9            23.976p, 24p, 29.97p, 29.97i, 30p, 30i
High (HD)         720        1280         16:9            23.976p, 24p, 29.97p 30p, 59.94p, 60p
Standard (SD)      480       704        4:3, 16:9   23.976p, 24p, 29.97p, 29.97i, 30p, 30i, 59.94p, 60p
Standard (SD)      480       640          16:9      23.976p, 24p, 29.97p, 29.97i, 30p, 30i, 59.94p, 60p

 •    Table III is well known in the broadcast industry
 •    List of standard formats from ATSC A.53 DTV Standard
 •    36 different formats available!
 •    Doesn’t take into account line doubling, etc.
           Displays Driving
• Take an HDTV plasma display panel example:
  – 1920x1080 resolution
  – 24-bit pixels
     • 8-bit Red, Green and Blue values
  – 30 progressive frames per second
• Bandwidth = 1920 x 1080 x 24 x 30 = 1.49Gbps
              Market Overview
• Various broadcast standards
   – Support different broadcast standards worldwide
       • DVB-T, ATSC, ISDB-T, (DMB-T?)
   – MPEG-2 predominantly used as DTV compression standard
• Provides improved quality
   – Support for HDTV
   – Clearer, multi-channel sound
   – Allows broadcasters flexibility in terms of bandwidth vs. quality
Worldwide Digital TV
              Digital TV Trends
• More Channels                        • Improved Quality
   – Increased choices                    – Support for HDTV
       • More specialized channels
       • Immediate feedback to            – No “ghosting” or other
         broadcasters                       interference effects
   – Maxim um use of available            – Sharper digital sound
                                          – Allows broadcasters flexibility in
• New Services                              terms of bandwidth vs. quality
   – Wide-screen
   – Interactive services
   – New text channels
   – Sophisticated on-screen program
   – Email facilities
                   DTV and Consumers
• 40% of consumers have no interest in digital TV*
• Happy with the services they already have
• This portion of the market is being targeted by FTA (free-
  to-air) digital broadcast support
• Analog WILL switch off
• New TVs will inherently support
  digital services
• Plug-in modules for upgrades?
• Logos appearing to help differentiate
  digital TVs from analog (for those who
  are interested)

*Source: Zarlink Semiconductor
  The Market Continues to
 Grow Despite Tough Times

                             STILL GOTTA HAVE IT
        Despite a slumping economy, consumers are still eager to get their hands on
         the latest audio and video gear. And why not? It's mostly cheaper now.
                                                  PERCENT CHANGE 2001 AVERAGE    PERCENT CHANGE
  CATEGORY                      2001 UNIT SALES *    FROM 2000   SELLING PRICE      FROM 2000
  DIGITAL TELEVISION                    325,000           230%         $2,477       -31%
  DVD                                 3,450,000            94            205        -25
  DIGITAL CAMERA                      3,500,000            66            286        -19
  MP3/DIGITAL MUSIC PLAYER              125,000            59            212         -2
  HOME THEATER SYSTEM                   425,000            49            483        +22
  HOME CD BURNER                        125,000            47            374        -20
  DIGITAL CAMCORDER                     475,000            43            808        -16
  *PROJECTED Data: Industry estimates, NPD Intelect Mar ket Tracking

BusinessWeek, September 17, 2001
  F.C.C. Schedule for HDTV

1997   HDTV schedule set and spectrum assigned
2002   All commercial stations to broadcast HDTV
2003   All non-commercial stations to broadcast HDTV
2004   75% of programming to be digitally simulcast
2005   100% of programming to be digitally simulcast
2006   Analog switch off, but only if 85% of market able
       to receive HDTV signals
• Accelerators                            • Inhibitors
  – Higher clarity of pictures (6 times       – Cost of sets still too high for
    the resolution of NTSC)                     widespread adoption
  – Better color purity                       – Lack of consumer awareness
  – Better quality, multi-channel sound         about HDTV
  – HDTV set costs falling                    – Consumer reluctance to
                                                change to HD/digital
  – HD production costs cheaper than          – Still not enough HD content
    film (in the long run)
                                              – Land coverage of broadcasts
  – More HD content being produced
                                              – No guarantees that standards
  – Resolution of modulation scheme             will not change
    debates (8VSB vs. COFDM)                  – Bandwidth resources may be
                                                better used for multicasting
                                                SDTV content
Digital TV System
                                Digital TV System
                                                                                                                   Audio                   Audio
                                                                                                                   MUX                    CODEC
                                         ADC                                                 MPEG-2
                                   SPDIF                                                                                                   Audio
               SPDIF Audio
                                    to I2C                          Memory                                          Color                 CODEC
                                   CODEC                            Controller                                      MUX
                                                                                          Graphics                                         I2C
                                                                                          Controller                                    to SPDIF
             RF in
                        Tuner                                                                                                           CODEC
                                NTSC                                  CPU                 Bridge                                  DAC
                                Video                 MUX                                                        YUV to
                               Decoder                                                                            RGB                         Display
                VSB                                                                                                                DVI
                       1394                    1394
          Home         PHY                     MAC
          Network                                                       Descrambler                I/O Control
               Satellite            QPSK
                                   QPSK                  FEC

                                   QAM                   FEC            PID           RS-232C           Parallel       Serial     Keyboard/Mouse
                       Cable                                         Processor        Interface        Interface     Interface       Interface

Digital           Memory           Mixed Signal          uP or uC   Programmable        IP Block
Xilinx Value

Digital TV / HDTV
     Xilinx Solutions in iDTVs
• Multiple responsibilities within the TV
    – Bridges
        • Enabling different technologies to co-exist
    – Forward Error Correction
        • Reed-Solomon, Viterbi, De-interleaving
    – Enabling broadband local loop in digital modems
        • xDSL, cable, satellite
    – MPEG co-processing
        • DCT/IDCT acceleration
        • Picture quality enhancements allow differentiation
    – Access points
        • Interfaces to broadband and home networks
    – Encryption/Decryption
        • DES, Triple DES, AES
             Front End Interface
• Not cost effective to support multiple receivers
    – Cable, terrestrial, satellite and xDSL
    – Requires multiple iDTV designs

              QPSK Decoder
                and FEC
                                                      Interface required to support
              QAM Decoder                                     multiple ASSPs
                and FEC
                                                     Choice of ASSP influenced by
              OFDM Decoder                                  broadcaster features
                and FEC

                                     Spartan-IIE FPGA Allows
                 xDSL                  Interface To Multiple
     !                                      Front Ends
Forward Error
       What Does FEC Do?

• Enables the receiver to detect and correct errors
  automatically without requesting retransmission
• Based on the addition of redundant parity
  information to the data being transmitted
• One metric of the quality of the communication
  link is measured in terms of Bit Error Rate (BER)
• Widely used in real-time systems for the
  transmission of audio and video data
• Digital Video Broadcasting organization
• Formed in September 1993
• DVB now has more than 300 members
   –   Broadcasters
   –   Manufacturers
   –   Network operators
   –   Regulatory bodies
• Mission : “The creation of a harmonious digital broadcast
  market for all service delivery media”
• Mainly covers Europe but also promoting in U.S. and
DVB Worldwide Adoption
    DVB-T (Terrestrial) FEC
RF in

        Mi xer
                 IF bandpass
                                ADC       2K or 8K
                     filter                             Demod           Inner de-interleave

    Local                      AFC               Pilot and
   oscillator                                   TPS decode TPS                Inner
                                                                         error correction


Video                                Video ES
 out        Video                                                           Outer error
           decoder                                                          correction
                                     Audio ES
            Audio                                PCR
Audio      decoder                                      Demultiplexer

                       Timestamp           27MHz
                         counter            VCO        Program   PSI
• Advanced Television Systems Committee
• Formed in September 1982
• ATSC now has more than 200 members
• Broadcasters
• Manufacturers
• Network operators
• Regulatory bodies
• Co-ordinates television standards among different
  communications media focusing on digital television, interactive
  systems, and broadband multimedia communications. Also
  developing digital television implementation strategies
• Adopted by U.S., Canada, S. Korea, Taiwan and Argentina
    ATSC - 8VSB (Terrestrial)
RF in

    Mi xer 1
                                       Synchronous                               Phase
                 IF 1                                   NTSC                                     Inner
                                         detector                    Equalizer   noise
                                                         filter                              de-interleave
                                       (pilot locked)                             filter

    Local                 Local
  oscillator 1          oscillator 2
                                                                                             Trellis decode

                                                                                           Main de-interleave

                                                                                              Outer error

                                              Transport stream out
• Integrated Service for Digital Broadcast
• Developed and adopted by Japan
• Similar to DVB
   – ISDB-T uses OFDM (Orthogonal Frequency Division Multiplex)
   – Same channel coding (FEC) - Reed Solomon and
• Terrestrial has some additional features
   – RF channel split into 13 segments
   – 3 different modulation schemes can be used on different
     segments at the same time
   – Optional time interleaver for improved mobile reception
   – 4K FFT mode available
• Digital Multimedia Broadcasting
• Jointly developed by Qinghua University in Beijing
    and US-based Legend Silicon
•   Proposed for Chinese and Hong Kong markets
•   DMB-T (terrestrial) uses TDS-OFDM
•   Time domain synchronous OFDM
•   Said to provide better synchronization with mobile
Summary of Terrestrial Systems
 Sy stems                 ATSC 8-VSB                DVB-T COFD      M       ISDB    -T BST-OFD   M
 V ideo                     Main P  rof ile Sy ntax of ISO/I  EC 13818-2 (MPE      G-2 video)
                                                    I      C
                                                     SO/IE 13818-2
                                                                              ISO/IE 13818-7
                         A TSC Standard            (MPE   G-2 Layer II
 A udio                                                                             PE
                                                                                (M G-2 A A C
                        A/52 (D  olby A C   -3)    A udio) and Dolby
                                                           AC  -3
 Transport Stream               I     E
                                 SO/I C 13818-1 (MP       EG-2 TS) transport s tream)
 Outer Coding          R-S (207, 187, t=10)                       S
                                                                R (204, 188, t=8)
                                                  Punctured convolutional code : R        ate 1/2,
 Inner Coding          Rate 2/3 trellis code        2/3, 3/4, 5/6, 7/8 C  ons traint length = 7,
                                                          Polynomials (octal) 171, 133
                                                                           Bitw ise interleav ing,
                                                  Bitw is e interleav ing          f requency
                        12 to 1 trellis code
 Inner Interleav er                                   and f requency           interleaving and
                                                       interleaving             s electable time
                                                                                  interleav ing
 Data Randomiz ation       16-bit PR  BS               16-bit PR  BS              16-bit PRBS

                                                       COFD  M                   M
                                                                       BST-OFD w ith 13
                                                   QSP K, 16QA M,    f requency s egm   ents
                                                       64QA M            DQP SK, QP    SK,
                                                    Heirarchic al       16QA M, 64QA M
                                                  modulation : multi       Heirarchical
                                                     resolution            modulation:
                                                    constellation        three dif f erent
 Modulation                   8-V SB
                                                    (16QA M and          modulations on
                                                      64QA M)             13 segments
                                                   Guard interval :  Guard I  nterval: 1/32,
                                                 1/32, 1/16, 1/8 and  1/16, 1/8 and 1/4 of
                                                1/4 of OFDM s ymbol       OFDM s ymbol
                                                  2modes: 2K & 8K    3 modes: 2K, 4K and
                                                         FFT                 8K FFT
  Reed-Solomon Encoder / Decoder

• Reed-Solomon
  – An error-correcting coding system that corrects
    multiple errors, especially burst-type errors in
    communication systems
  – Transmitter (encoder)
     • Data is encoded to be corrected in an event it acquires
  – Receiver (decoder)
     • Uses the appended encoded bits to determine errors
     • Corrects the errors upon reception of the transmitted signal
Reed-Solomon Decoder
Block Diagram for iDTV
            Reed-Solomon GUIs
• Parameterizable encoder
  and decoder cores
  available from Xilinx
• Simply select DVB/ATSC
  from the Code
  Specification menu
• Reed-Solomon tutorials
  online at Xilinx IP Center
Reed-Solomon Decoder
    DVT Examples
  IP Solutions - Advantages
• The Xilinx decoder core is half the size of any
  competitor’s offering
• Automatically configured from user parameters
   – Supports all major coding standards and custom
• Can be optimized for area or speed
• Incorporates Xilinx Smart-IP technology for
  design predictability

• Viterbi algorithm
   – It is a convolutional code to correct random errors
   – It minimizes the number of sequences in the trellis
     search as new data is received by the demodulator
   – Developed by Dr. Andrew J. Viterbi
      • Co-founder, Retired Vice chairman, Board of Directors of
Viterbi Decoder Block
         Viterbi Decoder IP

• Decoder of convolutional codes
• Customized VHDL source code available,
  allowing generation of different netlist versions
• Customized testbench for pre- and post-synthesis
  verification supplied with the module
             Viterbi LogiCore GUI
•   Fully parameterizable - includes parallel, serial & puncturing options
•   More info at
Spartan FPGA Based Viterbi
                  Outer Interleaver
RS decoder can only correct a limited amount of errors per packet:

Interleaving spreads burst errors across several packets:
        DVB Outer Interleaver
• Previous interleaver example was actually block based whereas
  DVB version is convolutional (Forney algorithm)
• Error dispersion idea is basically the same
   Convolutional Interleaver

• Data is effectively sheared in a DVB interleaver:

 This has the advantage of needing less memory for
Interleaver/Deinterleaver GUI
      iDTV Example
                FEC Summary
• Range of parameterizable cores available
   –   Reed Solomon encoder/decoder
   –   Convolutional encoder
   –   Viterbi decoder
   –   Interleaver/deinterleaver
   –   Turbo codecs
• Intuitive generator GUI enables fast core production
• Tutorials and core details available at...

        The MPEG Algorithm
• The MPEG Encoder is composed of a number of discrete
  algorithmic sections:
• Temporal Processing
   – Seeking out and removing temporal redundancy
      • Involves storing several successive images and performing motion
        estimation, compensation and simple algorithmic processing to derive a
        pixel-by-pixel difference signal
• Spatial Processing
   – Uses DCT to remove the high frequencies not discernable by
     the human eye.
• Statistical or Variable Length Encoding (VLC) to remove
  redundancy in the output from the DCT
           DCT/IDCT Concept
• What is DCT?
   – Returns the discrete cosine transform of ‘video/audio input’
   – Can be referred to as the even part of the Fourier series
   – Converts an image or audio block into it’s equivalent frequency
• What is IDCT?
   – The IDCT function is the inverse of the DCT function
   – The IDCT reconstructs a sequence from its discrete cosine
     transform (DCT) coefficients
                                  DCT/IDCT Concept
                  Original Image

                                                                                                                                Compared to
                   Restored Image
             (Notice Lesser Image Quality)                                                                                      Thresholds,
                                                                                                                                Resulting in
                                                                                                                         IDCT   Data Stream

                                                                              The image is broken into 8x8 groups,
                                                                                each contain ing 64 pix els. Three of
                                                                              these 8x8 groups are enla rged in this
                                                                                 figure, showin g the values of the
                                                                               individ ual pixels, a single byte value
                                                                                        between 0 and 255 .

Courtesy: The Scientist and Engineer's Guide to Digital Signal Processing by Steven W. Smith
DCT/IDCT Concept

Divide picture into
16 by 16 blocks.
                                                 Each block is 8
                                                 pixels by 8 lines.
                      Each macroblock is
                      16 pixels by 16 lines.
                      (4 blocks)


         8X 8                                  Frequency
         Block                                 Coeffici ents

Detailed steps in dissecting a typical digital still
    image prior to being DCT transformed
    DCT/IDCT Compression
• Compression allows increased throughput
  through transmission medium
  – Video & audio compression makes multimedia
    systems very efficient
     •   Increases CPU bandwidth
     •   Higher video frame rates
     •   Better audio quality
     •   Enables multimedia interactivity
• DCT/IDCT are widely used in video & audio
       Spartan-IIE DCT/IDCT
        LogiCore Features
• Combined DCT/IDCT core
• Continuous one symbol per cycle
  processing capability
• Internal precision
   – 14 bit cosine coefficients
   – 15 bit transpose memory
• Optimized for specific Xilinx architecture
• Fully compliant with the JPEG standard (ISO/IEC10918-1)
• Supplied with Verilog and VHDL test benches
          DCT/IDCT Core Overview

DctIDct                                       InProg       • 2D transform decomposed into 2
                                                             1D - operations (Stage 1 and
Pixel Input      Stage 1          Stage 2   DCT Output       Stage 2)
Interface                                   Interface      • Intermediate results stored in
                       Transpose            Pixel Output
                                                             Transpose Memory
IDCT Input
Interface               Memory              Interface      • Forward DCT - 8-bit unsigned
                                                             input,11-bit signed output
                                                           • Inverse DCT - 11-bit signed
                                                             input,8-bit unsigned output
                 CLK       RSTn     CLR                    • Continuous streaming - one
              Half-Duplex Operation                          sample per cycle processing
  Forward or Reverse, Not both simultaneously                capability
Solution - Performance
 Relative Performance

                                     1                3
                              266MHz 32-bit uP 266MHz 32-bit uP   Spartan-IIE
                                               with Multimedia
LogiCore Implementation
Target Device      Spartan-IIE Virtex-E Spartan II
                   xc2s200E-7 xcv200e-8 xc2s150-6

Speed                75 MHz     80 MHz    71.4 MHz
SDTV (27 MHz)           3         3          2
Time Multiplexed
HDTV (75 MHz)          1          1         N/A
Time Multiplexed
Size (Slices)         1759       1759       1728
Controllers and
Spartan-IIE Memory Solutions
             y  or r e r s
               CConnesi gnns
     M  mor           e
       eemory ce DDesi g
       M f er e                                            External Memory
   r  e e r
    eeeRRef e
                                        Block RAM              Interface

  Distributed RAM                          4Kx1                SDRAM
                                           2Kx2                SGRAM
                                                              PB SRAM
        16x1                              256x16             DDR SRAM
                                                             ZBT SRAM
                                                             QDR SRAM
                                      Large FIFOs
   DSP Coefficients
                                      Video Line Buffers
     Small FIFOs                      Cache Tag Memory

        200 MHz Memory Continuum - Transparent Bandwidth
          1998                 1999                2000
      Spartan-IIE Block RAM
• True Dual-port Static RAM - 4K bits
   – Independently configurable port data width
            – 4K x 1; 2K x 2; 1K x 4; 512 x 8; 256 x 16
   – Fast synchronous read and write
       • 2.5-ns clock-to-output with 1-ns input address/data setup

        W                                        R
        R                                        W   Data Flow Spartan-IIE
                                        Port B
              Port A

                         Spartan-IIE                 A to B      Yes
                       True Dual-Port                B to A      Yes
                         Block RAM                   A to A      Yes
       W                                         W   B to B      Yes
       R                                         R
         Spartan-IIE Memory
• Spartan-IIE FPGAs
   – Unique and extensive features, flexible architecture,
     low cost
• Memory controller for interface to different types
  of SRAM, DRAM & Flash memory
   – Xilinx provides FREE VHDL source code for
     implementing the memory controllers in Spartan-IIE
         Memory Controller
         Reference Designs
• DRAM reference designs           • Embedded memory reference
   – 64-bit DDR DRAM controller      designs
   – 16-bit DDR DRAM controller       – CAM for ATM applications
   – SDRAM controller                 – CAM using shift registers
• SRAM reference designs              – CAM using Block SelectRAM
   – ZBT SRAM controller              – Data-width conversion FIFO
   – QDR SRAM controller              – 170MHz FIFO for Virtex
• Flash controller                    – High speed FIFO for Spartan-II
   – NOR / NAND flash controller

   These Reference Designs are Available for Immediate
            Download at the Memory Corner
                  Memory Corner
• Collaboration between Xilinx and major memory vendors to
  provide comprehensive web-based memory solutions
       • Free reference designs (VHDL/Verilog)
       • SRAM, DRAM & embedded FPGA memory solutions
       • Data sheets, app notes, tutorials, FAQs, design guidelines

                                               Of  f s
                                          rner e i i n
                                         oorner O ssggns
                                 m  ry C e D
                                   oory C ncceD e
                              Meem efeeren
                               M R ef re
                              FFree R
 Bandwidth Requirements for
Various Multimedia Applications
        Application               Technique            Speed
   Video Conference Quality          H.261             0.1 Mbps
       Streaming Video              MPEG-4          5Kbps - 10Mbps
         VCR Quality                MPEG-1             1.2 Mbps
       Broadcast Quality            MPEG-2            2 -4 Mbps
                                                                       Require High
   Studio Quality Digital TV        ITU-R 601         165 Mbps
   DVD/Studio Quality TV             MPEG-2           3-6 Mbps       Interconnectivity
           HDTV                       CD-DA            2 Gbps            Solution
           HDTV                    MPEG-2            25 -34 Mbps
      Streaming Audio          MPEG Layer 3 (MP3)    32 -320 Kbps
     Consumer CD-Audio              CD-DA             1441 Kbps
     Consumer CD-Audio           MPEG with FFT      192 -256 Kbps
    Sound Studio Quality         MPEG with FFT        384 Kbps
         Dolby AC-3               5.1 Channels        640 Kbps
    Telephone (Standard)           G.711 PCM           64 Kbps
    Telephone (Standard)         G.721 ADPCM           32 Kbps
     Telephone (Lower)                GSM              13 Kbps
     Telephone (Lower)                CELP            5 -7 Kbps
  Broadband Access (DSL)              ADSL           1.5 - 9 Mbps
Broadband Access (Cable)           DOCSIS              2 Mbps
     IEEE-1394 & Multimedia
• 1394 is the lowest cost, digital interface available
  for audio/video applications
• New audio/video applications are the primary
  market for IEEE-1394
   – Digital Television (DTV)
   – Multimedia CDROM (MMCD)
   – Home Networks
• IEEE-1394 has been accepted as the standard
  digital interface by the Digital VCR Conference
     IEEE-1394 & Multimedia
• The European Digital Video Broadcasters (DVB) have
  endorsed IEEE-1394 as their digital television interface
   – Several of these companies have proposed IEEE-1394 to the
     VESA (Video Experts Standards Association) as the digital
     home network media of choice
• The EIA 4.1 subcommittee has voted for IEEE-1394 as
  the point-to-point interface for digital TV, as well as the
  multi-point interface for entertainment systems
• The American National Standards Institute (ANSI) has
  defined Serial Bus Protocol (SBP) to encapsulate SCSI-3
  for IEEE-1394
             Why IEEE-1394?

• A hardware and software standard for transporting data at
  100, 200, 400, or 800 megabits per second (Mbps)
• A digital interface
   – There is no need to convert digital data into analog and tolerate
     a loss of data integrity
• Physically small
   – The thin serial cable can replace larger and more expensive
• Inexpensive and Easy-to-use
   – There is no need for terminators, device IDs, or elaborate setup
              Why IEEE-1394?
• Hot pluggable
   – Users can add or remove 1394 devices with the bus active
• Scaleable architecture
   – May mix 100, 200, and 400 Mbps devices on a bus
• Flexible topology
   – Support of daisy chaining and branching for true peer-to-peer
• Non-proprietary
   – There is no licensing problem to use for products

          Audio/Video Digital Interface of Choice!
          IEEE 1394 Protocol Stack
                                                          Serial Soft API
                                    Configuration &                  Read, Write, Lock
                                     Error Control
                                                                Transaction Layer                    Channels


                                                                Link Layer (Cycle control, packet
                             Serial Bus                           transmitter, packet receiver)

                                                                 Physical Layer (Encode/Decode,
                                                                   Arbitration, Media Inter face)
                                                                                           Electrical Signal &
                                                                                          Mechanical Interface
                                                                               IEEE 1394
                                                                            Physical Interface

Digital    Memory   Mixed Signal   uP or uC     Programmable    IP Block
              1394 PHY Layer
• The physical layer provides the initialization and
  arbitration services
   – It assures that only one node is sending data at a time
• The physical layer of the 1394 protocol includes:
   – The electrical signaling
   – The mechanical connectors and cabling
   – The arbitration mechanisms
   – The serial coding and decoding of the data being transferred
     or received
   – Transfer Speed detection
           1394 PHY Layer

 Data                         Rx Decoder
                               & Timer
 LReq                         Arbitration        Port
            Link            & Control Logic    Interface
          Interface                              Logic
                                  Tx Encoder

 Reset                PHY Clock
                   Link Layer
• Gets data packets on and off the wire
• Does error detection and correction
• Does retransmission
• Handles provision of cycle control for isochronous
• The link layer supplies an acknowledged
  datagram to the transaction layer
    – A datagram is a one-way data transfer with request
                             Link Layer
                                                                                                     PCI Interface
                                                               CSR                                   ( PCI Master,
                                                                                                      PCI Target)

  IEEE 1394       Packet                                                                             Application
                 Transmit/             Packet                 Link              Host
   Physical                                                  Control                                  Interface
                 Receive,             Analyzer                                Interface
   Interface       CRC

                                       Arbiter            Transmit &
                                                           Receive                                   Interface


Xilinx FPGAs are ideal for implementing Link Layer Functionality

               Digital       Memory        Mixed Signal       uP or uC   Programmable     IP Block
Link Controller IP - Xilinx
 Enabled Differentiation
               DVI Overview
• Interface to link digital graphics sources to digital
• One-way link supporting uncompressed HDTV signals
• Removes an unnecessary analog-digital-analog
  conversion step (current methods) - enables pure digital
  signal to display
• Based on Transition Minimized Differential Signaling
• Developed and promoted by the Digital Display Working
  Group (DDWG)
                DVI & IEEE-1394

               Stream         Bit Rate        Architecture     Command &       Applications
IEEE-1394   Compressed           1394:        Peer-to-peer      Support for      Storage,
              MPEG-2         100, 200, or                      AV command       networking
             Transport        400 Mbps,                          & control
                           800 Mbps to 3.2
                           Gbps, Scalable
  DVI       Uncompressed   Single link DVI:   Point-to-point   No support     Digital interface
              baseband         4.9 Gbps                          for AV         between a
                             Double link                       command &       graphics chip
                            DVI: 9.9 Gbps                        control       and a monitor
Spartan-IIE in Example DVI System
To video inputs & other image processing

                                              Color Space    G

                                                                                                          To display panel
                                                                                           G    Display
                                           Graphics                                        B
                                                            DE                            CLK   Timing
                                           Controller       CLK                           DE


                                                             e.g. SIL190 Tx   e.g. SIL161A Rx

                                                                  TMDS DVI Link

                 Image Processing / Graphics Control                                  Display Driver
                         (e.g. Set-Top Box)                                   (e.g. Plasma Display Panel)
USB 2.0

Universal Serial Bus
        USB - Universal Serial Bus

                                       Modems             Mass Storage
                                   Digital Cameras          Broadband
                                       Printers         Home Networking
                                      Scanners        Residential Gateways
                                    Microphones        Digital Video/Audio
                                  Legacy Conversion    Legacy Conversion

        Low-Speed                   Full-Speed            High-Speed
         1.5 Mbps                    12 Mbps               480 Mbps

Courtesy: Cypress Semiconductor
                              USB 2.0 IP Core

   USB                                                                                            USB
                                Serial               SIE                                        Controller
Datastream   Line                                   Control                Parallel
             Driver                                 Logic                 Interface
                            Engine (SIE)
                                                    Block               Module (PIM)
                  Clock Generator
                      & DLLs                                                  CPU

                                                      Mode              DMA

                              Digital      Memory        Mixed Signal     uP or uC     Programmable      IP Block
The Xilinx USB 2.0 Solution
   XC2S150                                     Mentor Graphics
                                                USB2.0 Core

  SCSI Port

 Mentor Graphics
                                Kawasaki LSI
                                 UTMI Phy
             Mentor Graphics
              8051 eWARP

          First USB2.0 Mass Storage Reference Design
 The Xilinx USB 2.0 Solution
• Kawasaki LSI, Mentor Graphics and Xilinx have
  partnered and developed the industry's first UTMI-
  compliant USB 2.0 upgradable reference design
   – Provides a USB 2.0 to SCSI technology bridge, and can be
     used to provide end-to-end high-bandwidth data storage
      • For hard disk drives, CD writers, DVD ROMs, etc.
   – Flexible and upgradable USB 2.0 technology bridge to multiple
     home networking standards
      • Such as HomePNA, HomePlug, HomeRF, IEEE-1394, IEEE802.11b
 USB 2.0 Mass Storage
Reference Design Details
                   UTMI                         VCI

                             USB 2.0
       USB 2.0
                             Function                 Microcontroller
     Transceiver                                                               DMA
                                                        Inventra             Controller
                            Inventra                  M8051 E-Warp

                                                                   Xilinx S partan-II FPGA

                                                       Program/Data Memory
 USB 2.0                                                  64Kbytes SRAM
 Connector                                                 64Kbytes Flash
                          Xilinx S partan-II®                                     Connector
         Solution - Features
• USB 2.0 Transceiver Macrocell Interface (UTMI)
  compliant physical layer from Kawasaki LSI
• High-speed (480Mbps) USB 2.0 functionality
• Mentor Graphics MUSBHSFC Fully Synthesizable Core
  Optimized for low-cost Spartan-II FPGAs
• Backward compatible with full-speed USB 1.1
• Future-proof, reprogrammable SIE
• Low-cost home networking solution
             PCI - Concept

  – Peripheral Component Interconnect
  – Originated in the PC industry
  – High performance bus that provides a processor
    independent data path between the CPU and high-
    speed peripherals
  – Robust interconnect mechanism developed to relieve
    the I/O bottlenecks
            ASSP Replacement &
System & Memory Controllers,
DLLs, Level Translators ($20)

                                                     Standard Chip
                                                     PCI Master I/F ($15)

        Logic                   *Supported Devices
   External PLD                     XC2S100E          Memory ($9)
   PCI Master I/F ($5)              XC2S150E
                             PCI - A Successful
                           Programmable Solution
                                 External PLD
Relative Component Cost

                                 7K Gates
                                 External DLLs,                           Spartan-IIE
                                 memories,                               FPGAs Lower
                          0.5    Controllers and
                                 translators                             Overall System
                                                   XC2S50E-5 PQ208
                          0.1    PCI ASSP
                                  PCI Master        35K Gates Extra
                                 and Slave I/F           Logic
                                                            Master I/F

                                Standard Chip
Spartan-IIE PCI Solutions

* PCI32: 66 MHz design available using Xilinx XPERTs or Design Services
            Customer Benefits
• Reduces Cost Over PCI ASSPs
   – Cost savings of more than 50%
• Integrate and Replace System Functions
   –   PLL/DLL clock management devices
   –   SSTL-3/HSTL translators
   –   Back plane logic and drivers
   –   External Memory devices
   –   System & caches controllers
• Significant Time-to-Market Advantage
Data Encryption
   Copy Protection and Data
• Motivation for data encryption & cryptography
   – Data privacy (integrity & secrecy)
   – Authenticating the source of the information
• Several methods of data encryption exist
   –   RSA (Rivest-Shamir-Adleman), Diffie-Hellman, RC4/RC5
   –   Secure Hashing Algorithm (SHA), Blowfish
   –   Elliptic Curves, ElGamal, LUC (Lucas Sequence)
   –   DES (Data Encryption Standard) & Triple-DES (TDES)
• Xilinx Spartan-IIE + IP Cores today provide
   – AES, DES, Triple DES, proprietary
        Copy Protection Efforts

Courtesy: EETimes
       Copy Protection
  FPGAs Add Significant Value
• Security Systems Standards and Certification Act (Draft)
   – Calls for interactive digital devices to include security
     technologies certified by the U.S. Secretary of Commerce
• The bill becoming a law will prevent companies from
  shipping products without appropriate security
   – There is however no guidance on security schemes
   – A hardware based security implementation is preferred
• Lack of consensus between companies on the
  encryption schemes and their implementation is leading
  to chaos
• Copy protection for digital video products is in it’s infancy
  and will be a significant area of focus
 Spartan-IIE Advantages Over
Hardware & Software Solutions

           Software                        Hardware
           Solutions                       Solutions

 High Flexibility                               High Performance
Low Performance                                   Low Flexibility

                       High Performance     Enhanced Security &
                        High Flexibility       Performance
                    DES Concept
• The Data Encryption Standard (DES) algorithm
   – Developed by IBM Corporation
   – Most prevalent encryption algorithm
   – Adopted by the U.S. government in 1977, as the federal
     standard for encryption of commercial and sensitive, yet
     unclassified data
   – Is a block cipher
       • Encryption algorithm that encrypts block of data all at once, and then
         goes on to the next block
   – Divides 64-bit plaintext into blocks of fixed length (ciphertext)
   – Enciphers using a 56-bit secret internal key
       Triple-DES Concept

• Triple-DES concept
  – More powerful and more secure
  – Equivalent to performing DES 3 times on plaintext
    with 3 different keys
  – TDES uses 2 or 3 56-bit keys
  – With one key, TDES performs the same as DES
  – TDES implementation: serial and parallel
     • Parallel improves performance and reduces gate count
         Value Proposition in
           DES and TDES
• High performance, many features and cost effective
• High scalability and flexibility
   – Reconfigurable fabric and Internet Reconfigurable Logic
• Embedded solutions
   – FPGA logic not used from DES/Triple-DES soft IP can be used
     for other IP solutions
       • DCT/IDCT and DES/TDES soft IP in a Spartan-IIE FPGA can be used
         in multim edia and imaging applications
   – Increase the value proposition and reduces solution cost
• Spartan-IIE can be programmed with broadcaster
  proprietary conditional access algorithms
                AES (Rijndael)
• AES (Rijndael) chosen by the National Institute of
  Standards and Technology (NIST) as the cryptographic
  algorithm for use by U.S. government organizations to
  protect sensitive (unclassified) information
   – Rijndael block cipher named after its Dutch developers Vincent
     Rijmen and Joan Daemen
• Aimed to replace DES in the long run
   – DES has been successfully attacked using dedicated
     hardware and parallel computer networks
   – DES to be phased out
• Triple-DES expected to remain for foreseeable future
          AES (Rijndael)
IP Solutions - Helion Technology
       Spartan-IIE Encryption
• Spartan-IIE encryption solutions are NIST approved
• The programmable nature of these solutions allows easy
  customization based on end application requirement

     Note: Solution includes encry ption, decryption and key generation
     * 128-bit key im plementation
     ** Key Generation offloaded to embeddedµC/ µP
Color Space
     RGB Unity Color Space
• Mixtures of color components can be mapped into an
  RGB color space covering all variations from black
  (0xR + 0xG + 0xB) to white (1xR + 1xG + 1xB)
      Spectral Response of
          Human Eye
• Green sensing cones in the human eye respond
  to most wavelengths in the light spectrum
          Luminance and Color
• Pictures are almost always represented as pixels on final medium
    – Whether on printed paper or TFT, PDP & CRT displays
• Pixels can be represented with 3 full bandwidth analog RGB
    – Huge storage and transmission bandwidth requirements for high resolution,
      large format displays (up to 200 terabytes during post-production)
• Human eye is more receptive to brightness than it is to color
    – Full resolution of human vision is restricted to brightness variations
    – Color detail resolution is about a quarter that of brightness variations
    – Green objects will produce more stimulus than red objects of the same
      brightness, with blue objects producing the least
• A brightness/luma signal (Y) can be obtained by adding RGB
  values together which are weighted by relative eye response
       Luminance and Color
• ITU CCR 601 says Y = 0.299R + 0.587G + 0.114B
• To save bandwidth, color difference signals are sent with
  luma rather than RGB
• Color difference possibilities
   – R-Y
   – B-Y            As G contributes most to Y, this signal
   – G-Y            would be small and most susceptible to

• Simple maths can be used to reconstruct signals at the
       Color Space Converter
                        Optimized fixed-point
           Input          conversion core        Output
          register                              register

                           1 cycle latency

•   Fully synchronous
•   Registered input and output, 1 internal pipeline stage
•   Low latency (3 cycles)
•   Continuous processing
•   One 3-color conversion every clock cycle
•   Internal 10-bit precision for accuracy
•   Rounded to 8-bit outputs
                     Cores Available
CCIR 601 Standard
•   RGB2YCrCb
•   Y = 0.257×R' + 0.504×G' + 0.098×B' + 16
•   Cr = 0.439×R' - 0.368×G' - 0.071×B' + 128
•   Cb = -0.148×R' - 0.291×G' + 0.439×B' + 128
•   YCrCb2RGB
•   R'= 1.164×(Y-16) + 1.596×(Cr-128)
•   G' = 1.164×(Y-16) - 0.813×(Cr-128) - 0.392×(Cb-128)
•   B' = 1.164×(Y-16) + 2.017×(Cb-128)
•   Y = 0.299×R' + 0.587×G' + 0.114×B'
•   U = -0.147×R' - 0.289×G' + 0.436×B'
•   V = 0.615×R' - 0.515×G' - 0.100×B'
•   YUV2RGB                                                   Color Space
                                                               Color Space
•   R' = Y + 1.140×V                                        Converter Lounge
•   G' = Y - 0.394×U - 0.581×V
                                                             Converter Lounge
•   B' = Y - 2.032×U
          Xilinx Color Space
          LogiCore Solutions
Product/Cores       YCrCb2RGB         RGB2YCrCb         YUV2RGB           RGB2YUV
Virtex / Virtex-E   194 Slices        217 Slices        158 Slices        245 Slices
Synchronous         Full              Full              Full              Full
Supported Family    Spartan           Spartan-II        Spartan           Spartan-II
                    Spartan-II        Spartan-IIE       Spartan-II        Spartan-IIE
                    Spartan-IIE       Virtex            Spartan-IIE       Virtex
                    Virtex            Virtex-E          Virtex            Virtex-E
                    Virtex-E                            Virtex-E
Latency             3 Clock Cycles    3 Clock Cycles    3 Clock Cycles    3 Clock Cycles
                    >95 MHz           >90 MHz           >90MHz            >110MHz
SDTV (27 MHz)
Time Multipliexed   7 (Spartan-IIE)   3 (Spartan-IIE)   8 (Spartan-IIE)   3 (Spartan-IIE)
HDTV (75 MHz)       2 (Spartan-IIE)   1 (Spartan-IIE)   3 (Spartan-IIE)   1 (Spartan-IIE)
Time Multipliexed
Cost                $995              $995              $995              $995
Xilinx Color Space Solutions

• LogiCORE Color Space Converters provide
  straight forward, accurate, high-performance
  conversion useable in a wide range of
  video/image applications
• More area efficient than existing cores
• Speeds ensure operation in all TV and HDTV
• Available through Xilinx Coregen
Clock Generation
& Distribution
       Clock Generation and
• Spartan-IIE DLL circuits provide full clock management
• Clock generation
   – Synthesizing many clocks from a single reference crystal or
• Clock buffering and distribution
   – Providing multiple copies of a single clock
   – SDRAM clocks
• Spread spectrum clocks for EMI reduction
   – DLL circuits allow tolerance for ±2.5% variance
    Introducing the
Spartan-IIE FPGA Family
Xilinx Spartan Series FPGAs
  Performance                           Smallest Die Size
System Features                         Lowest Possible
 Software and                                 Cost

                  Low Cost Plastic Packages
                     Streamlined Testing
           Spartan-IIE FPGAs
  A Natural Fit for Digital Convergence
• Xilinx Solutions Allow Customers To Thrive in Chaos
   – FPGAs traditionally offer fast time-to-market
       • First to market, increases market share and revenue advantage
   – Xilinx Online offers reconfigurability in the field
       • Allows shipped product to support revisions to the spec
       • Enables unique opportunities to add value
       • Increases lifecycle revenue yield and hence, time-in-market
   – Enables rapid product proliferation
       • New designs can be quickly turned into derivatives
   – Superior lifecycle component logistics
   – Proven FPGA technology, software, test benches
• Spartan-IIE FPGAs Are Cost Effective!!!
Taking the Cost Down...
    Cost of 150K Digital Logic Over Time
        Spartan-IIE: The Total

                                   300K Gates
               More Gates       Distributed and         More Performance
                                   Block RAM
                              Fast I/O Performance

                     DLLs                        Easy Design Flow
Feature Rich    System I/O (19)                Free WebPACK SW      Time-to-Market
                 LVDS/LVPECL                     Fast, Predictable
Performance & Density   FPGA Application Trends

                                                                                   " Set-Top Boxes
                                                                                   " Digital TV
                                                                                   " Cable Modem
                                                               "PCI/PCI-X          " Bluetooth
                                                               "FEC                " Home Networking
                                                               "FFT/FIR Filters    " Digital Video
                                                               "IMA (ATM)       "Networking
                                                  "Data Path   "Encryption         " xDSL Modems
                                                  "Memory      "MP3 Decoder        " Line Cards
                                                  "Controllers                  "Computers
                                                                                   " Graphic Cards
                                        "Counters "uControllers                    " Printers
                                        "Adders                                 "Bio-Medical, Industrial
                                 "7400 Series

                         1980s                           1990s                      2000s
Spartan-IIE - System Integration
             Spartan-IIE Features
             Value in Digital Video
Spartan-IIE Silicon Features                       Value for Digital Video Applications
FPGA Fabric and Routing, Up to
                                                Performance in excess of 20 billion MACs/second
    300,000 System Gates
   Delay Locked Loops (DLLs)             Clock multiplication and division, clock mirror, Improve I/O Perf.
     SelectI/O - HSTL-I, -III, -IV                         High-speed SRAM interface
SelectI/O - SSTL3-I, -II; SSTL2-I, -II                     High-speed DRAM interface
    SelectI/O - GTL, PCI, AGP                      Chip-to-Backplane, Chip-to-Chip interfaces
Differential Signaling - LVDS, Bus       Bandwidth management (saving the number of pins), reduced
          LVDS, LVPECL                      power consumption, reduced EMI, high noise immunity
                                           16-bit Shift Register ideal for capturing high-speed or burst-
                                                 mode data and to store data in DSP applications
         Distributed RAM                                  DSP Coefficients, Small FIFOs
                                         Video Line Buffers, Cache Tag Memory, Scratch-pad Memory,
            Block RAM
                                                         Packet Buffers, Large FIFOs
Spartan-IIE LVDS
System Applications, Clock
Distribution, Cost Management,
Pin Savings, EMI Reduction
               What is LVDS?
• LVDS - Low Voltage Differential Signaling
• LVDS is a differential signaling interconnect technology
   – Requires two pins per channel
• LVDS was first used as a interconnectivity technology in
  laptops and displays to alleviate EMI issues
• Technology is now widely used in:
   – A broad spectrum of telecom and networking applications
   – Mainstream consumer applications like digital video and
        Differential Signaling
• Higher performance per pin pair
• Reduced EMI
   – Low output voltage swing
   – Relatively slow edge rates (dV/dt)
• High noise immunity
   – Switching noise cancels between the two lines
   – Data is not affected by the noise
       • External noise affects both lines, but the voltage difference stays about
         the same
• Reduced power consumption
Spartan-IIE Differential I/O

                  TQ144          PQ208         FT256          FG456
Device          User  Diff     User  Diff    User  Diff     User  Diff
XC2S50E         102   28       146   50      182    84
XC2S100E        102   28       146   50      182    84      202      86
XC2S150E                       146   50      182    84      263     114
XC2S200E                       146   50      182    84      289     120
XC2S300E                       146   50      182    84      329     120

      User = Maximum number of User I/Os available
      Diff = Maximum number of Differential Paired I/Os available
   Spartan-IIE LVDS Support
• All IOBs have LVDS/BLVDS/LVPECL capability
• IOBs configured as LVDS can be :
   – Synchronous or asynchronous
   – Input or output
• Two IOBs (pair) form one LVDS signal.
   – One IOB will function as + or P
   – The other IOB will function as - or N.
• LVDS pin pairs are indicated in the datasheet
• Maximum number of LVDS pin-pairs: 120
     Bus LVDS and LVPECL
• Bus LVDS - Bi-directional LVDS
   – The device can transmit and receive LVDS signals through the
     same pins
   – Requires different termination than LVDS
• LVPECL - Low Voltage Positive Emitter Coupled Logic
   – Well known industry standard for fast clocking and
   – Voltage swing (~750 mV) over two differential connections
    Spartan-IIE as a Differential

                                                        Standard LVDS or
 Spartan-IIE FPGA                                       LVPECL receiver, or
                                                        Spartan-IIE LVDS
                         Rs          Zo = 50Ω
                    Q                           OUT     or LVPECL receiver

                              Rdiv              Rt

 Data out                                                           Data in
                                     Zo = 50Ω

                    QB   Rs

Capable of driving any standard LVDS or LVPECL receiver
 Spartan-IIE as a Differential

                                                Spartan-IIE FPGA
     LVDS/LVPECL        Zo = 50Ω
     Line driver   Q               IN

Data out                                                   Data in
                        Zo = 50Ω

                   QB              INX

Spartan-IIE can be driven by any standard LVDS or LVPECL driver
Spartan-IIE receiver complies with the LVDS or LVPECL specs
         Spartan-IIE Core Support
• On-chip memory & storage            • Memory controllers (10+)
    – Distributed, BlockRAM, FIFOs       – SDRAM, QDR SRAM
• Bus products                        • Communications
    – PCI (64- & 32-bit, 33/66MHz),      – ATM (IMA, UTOPIA), Fast
      Arbiter, CAN bus interface           Ethernet (MAC)
• DSP functions (FIR filter)          • Telecom
• Error correction                       – CDMA matched filter, HDLC,
    – Reed-Solomon, Viterbi                DVB satellite, ADPCM speech
• Encryption (DES & TDES)             • Video & image processing
• Microprocessor                         – JPEG codec, DCT/IDCT, color
    – ARC 32-bit configurable RISC,        space converter
      8-bit 8051 microcontroller      • UARTs
       Spartan-IIE Enhances
    Advantages of Programmable
•   Time-to-Market
•   Flexibility
•   Field Upgradable
•   Cost Competitive
Xilinx Programmable Solutions
    Provide Several Benefits
• Accelerating time-to-market
   – Consumer devices require fast time-to-market
   – ASICs & ASSPs take 12-18 months to spin out
       • Immediate production upon design release
   – Fast design iterations
   – Rich, IP portfolio and efficient tools for design and synthesis
• System integration
• Testing and verification
   – Re-programmable means avoiding/reducing risk
   – Solutions are built on a proven FPGA technology with pre-
     verified silicon and IP that guarantees performance
 Xilinx Programmable Solutions
     Provide Several Benefits
• Increased flexibility
   – Product customization to meet customer needs
   – Accommodate multiple standards & spec updates/changes
   – Feature upgrades through field upgradability (IRL)
       • Remote update of software and hardware
       • Increased lifetime for a product (time-in-market) and allows new,
         interesting applications
       • Enable product features per end user needs
   – Broad product line
   – Broad IP and tools solutions
Xilinx Programmable Solutions
 Provide Several Advantages
• Issues in creating a stand-alone ASIC/ASSP
   –   Which standards and formats will win in which geographies?
   –   Choosing the right solution: over-design or under-design
   –   Product customization
   –   Development cost and amortization
• System cost management and assured source of supply
   –   Multiple sourcing for key high $ BOM components
   –   Reduced support costs via IRL
   –   Commodity component flexibility
   –   Programmable logic solutions are standard parts
• Low cost
     PLD Development Flow Advantages
 Accelerating Time-to-Market, Extending Time-
                   Minor Mid-Life                         Major Mid-Life

                 Upgrade Advantage                      Upgrade Advantage
              (Bug fixes & perf. tweaks)               (Sales life extension)


                                 Fixed Chip
• Time-to-Market advantage
  – First to market increase market share and revenue advantage
• Time-in-Market advantage
  – Maintains/extends competitive position
  – Can greatly increase lifecycle revenue yield
   Xilinx Solutions for Digital
• High-speed image/signal processing needs, coupled with large
  bandwidth requirements of HDTV can be met with low-cost
  Spartan-IIE FPGAs with LVDS I/O
• Image processing can be done real-time in FPGAs
    – Cuts down on memory requirements
• Numerous standards (and versions) cause uncertainty so designs
  need flexibility
    – Transmission schemes, MPEG profiles, display formats, color correction
• Xilinx FPGAs can differentiate your product from the competition
  while still conforming to the latest revision of standards
• Spartan-IIE FPGAs offer flexible, cost-effective solutions to ASSPs
• Faster time-to-market and longer time-in-market

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