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					     FSM Word Problems
Notes: Review for Test #2 – Monday
Studio #8: Reading assignment is due next week
Today:
• First Hour: Finite string recognizer, Complex counter
  – Section 8.5 of Katz’s Textbook
  – In-class Activity #1
• Second Hour: Traffic signal controller, Digital
 combination lock
  • Section 8.5 of Katz’s Textbook
  – In-class Activity #2
                                                      1
Katz Material not Covered

 CoCO doesn't cover everything in Katz.
    Omitted material includes:
       ASM charts
       The ABEL language
       all of Chapter 9 is skipped




                                          2
        Word Problems
• One of the most difficult problems is making an
  imprecise description of a finite state machine
  into a precise one.

• Have you covered all the states?

• Omissions can cause failures, crashes, death and
  destruction, etc.

• This is the Hardware equivalent of a Software
  programming error.


                                                     3
Finite String Recognizer
             Serial Finite State Machine


• One input: X
• One output: Z
• Description:
   – Z is 1 if the 3 previous input bits are 010, and
     100 has never been seen.
• Unstated assumptions:
   – RESET starts the FSM at the "reset" state
   – Z is asserted when the following bit is seen.
     A Moore Machine implementation.


                                                        4
                Example
                  Serial Behavior

• X: 0 0 1 0 1 0 1 0 0 1 0

• Z: - 0 0 0 1 0 1 0 1 0 0 0



• Z is 0 even though the three previous inputs are
  010, because 100 was seen earlier.




                                                     5
            Formal Design
State Transition Diagram
                                                        Reset
                                              S0
 • Create sequences of states                 [0]
                                          0         1
   for the strings that the
   machine recognizes:
                                    S1                  S4
         010 and 100.
                                    [0]                 [0]
 • Note we reset to S0.         1                         0

 • Consider the unlabelled          S2                  S5
   transitions.                     [0]                 [0]
                                0                   0
                                                                0,1
                                    S3                  S6
                                    [1]                 [0]
                                                                  6
                    State S3
Diagram Development                                           Reset
                                               S0
                                               [0]    1
• Where do we go from                      0
  S3?
                                     S1                   S4
                                     [0]                  [0]
• A 1 means the last 3
  bits are 101, so go to         1
  S2.                                                          0
                                     S2                   S5
                           01?
• A 0 means we’ve                    [0]                  [0]
  seen 100, so go to
  S6.                            0         1              0           0,1
                                     S3         0         S6
                           010       [1]                  [0]
                                                    100
                                                                            7
        States S1 and S4
Diagram Development
                                                      Reset
                                            S0
• Loop in S1 until we                       [0]
                                        0
  see our first 1.      0                           1
                                  S1              1? S4          1
• Loop in S4 until we             [0]                 [0]
  see our first 0.      0?
                                    1
                                                            0
                                  S2                  S5
                        01?       [0]                 [0]
                                                        0
                              0                                 0,1
                                        1
                                  S3        0         S6
                        010       [1]                 [0]
                                                100
                                                                     8
        States S2 and S5
Diagram Development
                                                            Reset
• S2 means the last 2                         S0
  bits are 01, which                          [0]
  may be a prefix of                      0             1
  010.                     0        S1              1? S4             1
• If the next bit is 1,             [0]                     [0]
  the last 2 bits are                         1
  now 11, maybe a         0?
                                      1                           0
  prefix of 100. That’s
  S4.                               S2        1             S5
                          01?       [0]                     [0]
                                      1       10?
• S5: Last 2 bits are           0                             0
  10. If next bit is 1,             S3                      S6
  maybe that’s a prefix                       0                       0,1
                          010       [1]                     [0]
  for 010. Go to S2.
                                                  100
                                                                          9
Review of Design Steps
                   Katz's Method

• Write sample inputs and outputs to understand it.

• Write sequences of states and transitions for the
  strings that the FSM is to recognize.

• Add missing transitions, using existing states
  when possible.

• Verify that the state diagram matches the FSM.



                                                      10
        Complex Counter

• Design a 3-bit counter, with one input bit, a mode, M.

• If M = 0, step to the next binary number in the
  sequence 000, 001, 010, 011, 100, 101, 110, 111, …

• If M = 1, step to the next Gray code number in the
  sequence 000, 001, 011, 010, 110, 111, 101, 100, ...




                                                           11
Try Some Sample Inputs

 • Note that we can switch modes at any time.

  Mode Input       Current         Next State
      M             State          (Z2 Z1 Z0)
      0            0 0 0             0 0 1
      0            0 0 1             0 1 0
      1            0 1 0             1 1 0
      1            1 1 0             1 1 1
      1            1 1 1             1 0 1
      0            1 0 1             1 1 0
      0            1 1 0             1 1 1


                                                12
                                               Reset

   Formal                            S0
                                   [000]

                              1            0
Representation                 1     S1
                                   [001]

                              1            0
                                     S2
                          1        [010]

 • One state for each     1                0
   output combination                S3
                                   [011]


                              1            0
 • Add appropriate arcs              S4
                                   [100]
   for the mode control
                              1            0
                                     S5
                                   [101]

                                           0
                                     S6
                                   [110]
                              1            0
                                     S7
                          1        [111]       0       13
                                                                               Reset

Do Activity #1 Now                                                   S0
                                                                   [000]

                                                              1            0
                                                               1     S1
                                                                   [001]
                                  Reset
                    S0                                        1
                    [0]
                                                                           0
                                                                     S2
                0             1                            1       [010]

 0                                                                         0
          S1              1? S4             1              1
                                                                     S3
          [0]                     [0]
                                                                   [011]
                    1
0?                                                                         0
            1                           0                     1
                                                                     S4
          S2        1             S5                               [100]
01?       [0]                     [0]
                                                              1            0
                    10?                                              S5
      0     1                       0                              [101]
          S3        0             S6        0,1                            0
010       [1]                     [0]                                S6
                                                                   [110]

                        100                                   1            0
                                                                     S7
FSM String Recognizer                                     1        [111]       0
                                                                                       14
                                                  Complex Counter
   Traffic Light Controller
• A busy highway is intersected by a little used farmroad.
• Detectors C sense the presence of cars waiting on the
  farmroad.
• With no car is on farmroad, the lights remain Green in
  the highway direction.
• If vehicle is on the farmroad, highway lights go from
  Green to Yellow to Red, allowing the farmroad lights to
  become Green.
• These stay Green only as long as a farmroad car is
  detected but never longer than a set interval.
• When these are met, farm lights transition from Green
  to Yellow to Red, allowing highway to return to Green.
• Even if farmroad vehicles are waiting, the highway gets
                                                         15
  at least a set interval as Green.
Diagram of Intersection
                   Farmroad

                    C
                              HL
             FL
                                    Highway




   Highway
                               FL
              HL        C

                   Farmroad
                                              16
       Available Timers

• Assume you have an interval timer that generates
  a short time pulse (TS) and a long time pulse (TL)
  in response to a start timer (ST) signal.

• TS is to be used for timing Yellow lights and TL
  for Green lights




                                                       17
Tabulate Inputs & Outputs
Input Signal    Description
reset           place FSM in initial state
C               detect vehicle on farmroad
TS              short time interval expired
TL              long time interval expired

Output Signal   Description
HG, HY, HR      assert green/yellow/red highway lights
FG, FY, FR      assert green/yellow/red farmroad lights
ST              start timing a short or long interval




                                                      18
Tabulate Unique States

• Some light configurations imply others.


 State             Description
  S0               Highway green (farmroad red)
  S1               Highway yellow (farmroad red)
  S2               Farmroad green (highway red)
  S3               Farmroad yellow (highway red)




                                                   19
      List Assumptions
• Reset places timer in S0, highway green and
  farmroad red.

• Reset also starts the timer.

• Stay in S0 as long as no one is on the farmroad.
• Even if there is a farmroad vehicle, the highway
  stays green at least long as the long time interval.

• (Unstated in Katz) There will never be a bicycle or
  pedestrian on the farmroad.

                                                         20
Traffic Signal State Diagram
                   TL + C
                        Reset
              S0                         S0: HG
    TL•C/ST
                                         S1: HY

                                         S2: FG
     S1                S3
                                         S3: FY

                        TL: long time interval expired
              S2
                        C: detect vehicle on farmroad


                                                    21
Traffic Signal State Diagram
                      TL + C
                           Reset
                 S0                          S0: HG
       TL•C/ST
                                             S1: HY
  TS
                                             S2: FG
        S1                S3
                                             S3: FY
       TS/ST
                          TS: short time interval expired
                 S2
                           ST: start timing a short or long
                           interval

                                                         22
Traffic Signal State Diagram
                      TL + C
                            Reset
                 S0                             S0: HG
       TL•C/ST
                                                S1: HY
  TS
                                                S2: FG
        S1                S3
                                                S3: FY
       TS/ST
                        TL + C/ST
                 S2             TL: long time interval expired
                               C: detect vehicle on farmroad
                        TL • C ST: start timing a short or long
                               interval
                                                                 23
Traffic Signal State Diagram
                      TL + C
                            Reset
                 S0                             S0: HG
       TL•C/ST          TS/ST
                                                S1: HY
  TS
                                                S2: FG
        S1                S3
                                  TS            S3: FY
       TS/ST
                        TL + C/ST
                 S2            TS: short time interval expired
                               ST: start timing a short or long
                        TL • C interval
                                                              24
     Combination Lock
• 3 bit serial lock controls entry to locked room.
• Inputs are RESET, ENTER, 2 position switch for
  bit of KEY data.
• Locks generates an UNLOCK signal when KEY
  matches internal combination.
• ERROR light illuminated if KEY does not match
  combination.
• Sequence is:
    – (1) Press RESET,
    – (2) enter KEY bit,
    – (3) Press ENTER,
    – (4) repeat (2) & (3) two more times.
                                                     25
Incomplete Specification

• Problem specification is incomplete:

   – how do you set the internal combination?
   – exactly when is the ERROR light asserted?




                                                 26
     Make Assumptions
• Make reasonable assumptions, decide whether
   – combination is hardwired into logic or stored
     in a register?
   – error is asserted as soon as an error is
     detected or waits until the full combination
     has been entered?

Our design: combination is stored in a register and
  error is asserted after the full combinationhas
  been entered



Why is it just possibly a bad idea to indicate an error
immediately on seeing the first bad bit ?
                                                          27
Block Diagram of Lock
Operator Data   RESET

                ENTER              UNLOCK
  Internal      KEY-IN
Combination              Combination
                          Lock F SM ERR OR
                L0

 Inputs:        L1
  Reset         L2
                                             Outputs:
  Enter                                       Unlock
  Key-In                                      Error
  L0, L1, L2

                                                        28
 Enumerate the States

• What sequences lead to opening the door?

• Do error conditions on a second pass …




                                             29
      State                                                   Enter                                 Enter

   Diagram of                                                         Comp1               Error1


      Lock                                          Enter
                                                            KI = L1
                                                                               KI  L1

                                                                                                     Enter

                                                                       Idle1               Idle1'
                       Reset + Enter

                               Reset                                                               Enter
                                                              Enter
                   Start

                                                                      Comp2               Error2
                       Reset • Enter
                                                                                KI  L2
                                                            KI = L2
                  Comp0                                                                               Reset
                                                   Reset                                  Error3
        KI = L0               KI  L0                                 Done
                                                                                          [Error]
                                                                  [Unlock]
Enter                                      Enter
                                                                                               Reset
        Idle0                     Idle0'                     Reset


                                                                       Start               Start

                                                                                                             30
   Do Activity #2 Now
Due: End of Class Today.
RETAIN THE LAST PAGE(S) (#3 onwards)!!

For Next Class:
• Bring Randy Katz Textbook, & TTL Data Book
• Required Reading:
  – Sec 11.1-11.3, skim 11.2 of Katz, omit the ABEL and
    ASM descriptions


• This reading is necessary for getting points in
  the Studio Activity!
                                                          31

				
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