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									TinyPowerTM Multi-Channel A/D Type 8-Bit OTP MCU

        HT45R52/HT45R54




        Revision: V1.00   Date: September 21, 2010
                                                                                                                      Contents



Table of Contents
        Technical Document ...........................................................................1
        Features ...............................................................................................1
        General Description ............................................................................1
        Selection Table ....................................................................................2
        Block Diagram .....................................................................................2
        Pin Assignment ...................................................................................3
        Pin Description ....................................................................................4
        Absolute Maximum Ratings ...............................................................5
        D.C. Characteristics ............................................................................5
        A.C. Characteristics ............................................................................8
        OP Amplifier Electrical Characteristics.............................................8
        Power-on Reset Characteristics ........................................................9
        System Architecture .........................................................................10
            Clocking and Pipelining ........................................................................................10
            Program Counter ..................................................................................................11
            Stack ....................................................................................................................12
            Arithmetic and Logic Unit - ALU ...........................................................................12
        Program Memory...............................................................................12
            Structure...............................................................................................................12
            Special Vectors.....................................................................................................12
            Look-up Table.......................................................................................................13
            Table Program Example .......................................................................................14
        Data Memory......................................................................................15
            Structure...............................................................................................................15
            General Purpose Data Memory ............................................................................15
            Special Purpose Data Memory .............................................................................15
        Special Function Registers ..............................................................16
            Indirect Addressing Registers - IAR0, IAR1..........................................................16
            Memory Pointers - MP0, MP1 ..............................................................................16
            Bank Pointer - BP ................................................................................................17
            Accumulator - ACC ..............................................................................................17
            Program Counter Low Register - PCL..................................................................17
            Look-up Table Registers - TBLP, TBLH................................................................18
            Status Register - STATUS ...................................................................................18


Rev. 1.00                                                       i                                             September 21, 2010
                                                                                                                    Contents

            Interrupt Control Registers....................................................................................18
            Timer/Event Counter Registers.............................................................................18
            Input/Output Ports and Control Registers .............................................................19
            Pulse Width Modulator Registers..........................................................................19
            A/D Converter Registers.......................................................................................19
            Serial Interface Registers .....................................................................................19
            Port A Wake-up Register - PAWU ........................................................................19
            Pull-High Resistors - PAPU, PBPU, PCPU, PDPU...............................................19
            Register - CLKMOD.............................................................................................19
            OPA Control Registers - OPAC ............................................................................19
            Miscellaneous Register - MISC............................................................................19
        Input/Output Ports.............................................................................19
            Pull-high Resistors................................................................................................21
            Port A Wake-up ....................................................................................................21
            Port A Open Drain Function..................................................................................21
            I/O Port Control Registers.....................................................................................21
            Pin-shared Functions............................................................................................21
            I/O Pin Structures .................................................................................................22
            Programming Considerations ...............................................................................22
        Timer/Event Counters .......................................................................23
            Configuring the Timer/Event Counter Input Clock Source .....................................23
            Timer Registers - TMR0, TMR1L/TMR1H ............................................................23
            Timer Control Registers - TMR0C, TMR1C..........................................................25
            Configuring the Timer Mode .................................................................................25
            Configuring the Event Counter Mode....................................................................26
            Configuring the Pulse Width Measurement Mode.................................................26
            Programmable Frequency Divider - PFD .............................................................27
            Prescaler ..............................................................................................................27
            I/O Interfacing.......................................................................................................28
            Timer/Event Counter Pins Internal Filter ...............................................................28
            Programming Considerations ...............................................................................28
            Timer Program Example.......................................................................................29
        Pulse Width Modulator .....................................................................30
            PWM Overview ....................................................................................................30
            8+4 PWM Mode Modulation .................................................................................30
            PWM Output Control ............................................................................................30
            PWM Programming Example ...............................................................................31




Rev. 1.00                                                      ii                                            September 21, 2010
                                                                                                                   Contents

        Analog to Digital Converter..............................................................32
            A/D Overview .......................................................................................................32
            A/D Converter Data Registers - ADRL, ADRH .....................................................32
            A/D Converter Control Registers ..........................................................................34
            A/D Input Pin Setup ..............................................................................................35
            A/D Power Supply and Reference Pins ................................................................35
            Using the A/D with the internal OPA .....................................................................35
            A/D Operation.......................................................................................................35
            A/D Interrupt .........................................................................................................36
            Summary of A/D Conversion Steps ......................................................................36
            Programming Considerations ...............................................................................37
            A/D Transfer Function...........................................................................................37

        Operational Amplifier - OPA ............................................................38
            OPA Operation .....................................................................................................38
            OPA Input Offset Cancellation ..............................................................................38
        Serial Interface Function ..................................................................39
            SPI Interface.........................................................................................................39
            SPI Registers .......................................................................................................40
            SPI Control Register - SIMCTL2 ..........................................................................42
            SPI Communication..............................................................................................45
            I2C Interface .........................................................................................................45
            I2C Control Register - SIMAR...............................................................................47
            I2C Bus Communication........................................................................................47
        Peripheral Clock Output ...................................................................49
            Peripheral Clock Operation...................................................................................49
        Buzzer.................................................................................................50
            PB0/PB1 Pin Function Control..............................................................................51
        Interrupts............................................................................................52
            Interrupt Registers ................................................................................................52
            Interrupt Operation ...............................................................................................52
            Interrupt Priority.....................................................................................................52
            External Interrupt ..................................................................................................52
            Timer/Event Counter Interrupt ..............................................................................56
            A/D Interrupt .........................................................................................................56
            SPI/I2C Interface Interrupt.....................................................................................56
            Multi-function Interrupt ..........................................................................................57
            RTC Interrupt........................................................................................................57
            Time Base Interrupt ..............................................................................................58
            Programming Considerations ...............................................................................58




Rev. 1.00                                                     iii                                           September 21, 2010
                                                                                                                   Contents

        Reset and Initialisation .....................................................................59
            Reset Functions ...................................................................................................59
            Reset Initial Conditions .........................................................................................60
        Oscillator............................................................................................65
            System Clock Configurations................................................................................65
            System Crystal/Ceramic Oscillator - HXT.............................................................65
            External System RC Oscillator - ERC ..................................................................65
            Internal RC Oscillator - HIRC ...............................................................................66
            Internal Low Speed Oscillator - LIRC ...................................................................66
            External Oscillator - ECK .....................................................................................66
        System Operating Modes .................................................................66
            Clock Sources ......................................................................................................66
            Operating Modes..................................................................................................67
            Power Down Mode and Wake-up .........................................................................68
            Power Down Mode ...............................................................................................68
            Entering the Power Down Mode ...........................................................................68
            Standby Current Considerations...........................................................................68
            Wake-up...............................................................................................................69
            Fast Wake-Up ......................................................................................................69

        Low Voltage Detector - LVD .............................................................69
            LVD Operation......................................................................................................69
        Watchdog Timer ................................................................................70
            Watchdog Timer Operation...................................................................................70
            Clearing the Watchdog Timer ...............................................................................71
        Configuration Options ......................................................................71
        Application Circuits ..........................................................................72
        Instruction Set ...................................................................................73
            Introduction ..........................................................................................................73
            Instruction Timing .................................................................................................73
            Moving and Transferring Data ..............................................................................73
            Arithmetic Operations ...........................................................................................73
            Logical and Rotate Operations .............................................................................73
            Branches and Control Transfer.............................................................................73
            Bit Operations.......................................................................................................74
            Table Read Operations.........................................................................................74
            Other Operations..................................................................................................74
            Instruction Set Summary ......................................................................................74
        Instruction Definition ........................................................................76




Rev. 1.00                                                     iv                                            September 21, 2010
                                                                                                               Contents

        Package Information .........................................................................86
            20-pin DIP (300mil) Outline Dimensions ...............................................................86
            20-pin SOP (300mil) Outline Dimensions..............................................................88
            24-pin SKDIP (300mil) Outline Dimensions ..........................................................89
            24-pin SOP (300mil) Outline Dimensions..............................................................92
            28-pin SKDIP (300mil) Outline Dimensions ..........................................................93
            28-pin SOP (300mil) Outline Dimensions..............................................................94
            Product Tape and Reel Specifications ..................................................................95
            Reel Dimensions ..................................................................................................95
            Carrier Tape Dimensions ......................................................................................96




Rev. 1.00                                                    v                                          September 21, 2010
                                                                                               HT45R52/HT45R54
                                     TinyPowerTM Multi-Channel A/D Type 8-Bit OTP MCU

Technical Document
· Application Note
  - HA0075E MCU Reset and Oscillator Circuits Application Note




Features
· Operating voltage:                                                  · 4 operating modes: normal, slow, idle and sleep
   fSYS=32kHz: 2.2V~5.5V                                              · Multiple level subroutine nesting
   fSYS=4MHz: 2.2V~5.5V                                               · 12 or 20-channel 12-bit resolution A/D converter
   fSYS=8MHz: 3.0V~5.5V
                                                                      · Integrated operational amplifier
   fSYS=12MHz: 4.5V~5.5V
                                                                      · 2 or 4-channel 12-bit PWM outputs
· OTP Program Memory: 2K´15 or 4K´15
                                                                      · Low voltage reset function: 2.1V, 3.15V, 4.2V
· RAM Data Memory: 192´8 or 384´8
                                                                      · Low voltage detect function: 2.2V, 3.3V, 4.4V
· 18 or 26 bidirectional I/O lines
                                                                      · Bit manipulation instruction
· TinyPower technology for low power operation
                                                                      · Table read instructions
· Two pin-shared external interrupts lines
                                                                      · 63 powerful instructions
· Multiple programmable Timer/Event Counters
                                                                      · Up to 0.33ms instruction cycle with 12MHz system
   with overflow interrupt and 7-stage prescaler
· External Crystal, external RC and internal RC
                                                                        clock at VDD=5V
                                                                      · All instructions executed in one or two machine
   oscillators
· Fully integrated 32kHz oscillator
                                                                        cycles
                                                                      · Idle/Sleep mode and wake-up functions to reduce
· Externally supplied system clock option
                                                                        power consumption
· Watchdog Timer function
                                                                      · Time-Base interrupt
· LIRC oscillator function for watchdog timer
                                                                      · Wide range of available package types
· PFD/Buzzer for audio frequency generation
· Serial Interface Module - SPI or I2C



General Description
These TinyPowerTM Multi-Channel A/D Type 8-bit high                   dustrial application areas. Some of these products
performance RISC architecture microcontrollers are spe-               could include electronic metering, environmental moni-
cifically, designed for applications that interface directly to       toring, handheld instruments, electronically controlled
analog signals. The devices include an integrated                     tools, motor driving in addition to many others.
multi-channel Analog to Digital Converter, Pulse Width
                                                                      The unique Holtek TinyPower technology also gives the
Modulation outputs and an Operational Amplifier.
                                                                      devices extremely low current consumption characteris-
With their fully integrated SPI and I2C functions, design-            tics, an extremely important consideration in the present
ers are provided with a means of easy communication                   trend for low power battery powered applications. The
with external peripheral hardware. The benefits of inte-              usual Holtek MCU features such as power down and
grated A/D, OPA, and PWM functions, in addition to low                wake-up functions, oscillator options, programmable
power consumption, high performance, I/O flexibility                  frequency divider, etc. combine to ensure user applica-
and low-cost, provides the device with the versatility for            tions require a minimum of external components.
a wide range of products in the home appliance and in-




Rev. 1.00                                                         1                                        September 21, 2010
                                                                                                                                               HT45R52/HT45R54

Selection Table
Most features are common to all devices, the main feature distinguishing them are Program Memory capacity, I/O count,
stack capacity and package types. The following table summarises the main features of each device.

                               Program Data                                              Timer                                                                      Package
  Part No.                                                                I/O                                      A/D                          Stack
                               Memory Memory                                      8-bit 16-bit                                                                       Types

              2.2V~
 HT45R52                            2K´15              192´8              18         1              ¾         12-bit´12 12-bit´2                 4               20DIP/SOP
               5.5V
              2.2V~                                                                                                                                           20DIP/SOP
 HT45R54                            4K´15              384´8              26         1                 1      12-bit´20 12-bit´4                 8
               5.5V                                                                                                                                        24/28SKDIP/SOP

Note:   1. The devices are only available in OTP versions.
        2. For devices that exist in more than one package formats, the table reflects the situation for the larger
           package.


Block Diagram


                                                                                                              L o w       W a tc h d o g              W a tc h d o g
                                                                                                           V o lta g e       T im e r             T im e r O s c illa to r
                                                                                                            D e te c t

                                                                                          L o w                                                               R e s e t
                                                                                      V o lta g e
                                                                                        R e s e t                                                            C ir c u it

                                            O T P                                                                                  8 - b it
                                    P r o g r a m m in g                                                                        R IS C                      In te rru p t
                                         C ir c u itr y                                                                          M C U                     C o n tr o lle r
                                                                                                                                  C o re
                                                                                                                                                          E x te rn a l
                                                                                                                                                        R C /C ry s ta l
                                                                                                                                                         O s c illa to r
               I/O                        O T P                       R A M
             P o rts                   P ro g ra m                     D a ta               S ta c k
                                        M e m o ry                  M e m o ry
                                                                                                                           In te rn a l R C
                                                                                                                             O s c illa to r


                                                                                                                              A /D
                                                                                                                         C o n v e rte r



                                                                                                                                       O P A


                                                                                 P r o g r a m m a b le
                       I2C /S P I                      T im e r s                    F re q u e n c y
                                                                                      G e n e ra to r                       P W M
                                                                                                                         G e n e ra to r




Rev. 1.00                                                                                   2                                                            September 21, 2010
                                                                                                                                HT45R52/HT45R54

Pin Assignment

                                                                                                P B 5 /A N 1 3        1            2 4       P B 6 /A N 1 4 /P W M 2
                                                                                       P B 4 /A N 1 2 /T M R 1        2            2 3       P B 7 /A N 1 5 /P W M 3
       P A 3 /A N 3 /P F D     1            2 0      P A 4 /A N 4 /P W M 0                 P A 3 /A N 3 /P F D        3            2 2       P A 4 /A N 4 /P W M 0
    P A 2 /A N 2 /T M R 0      2            1 9      P A 5 /A N 5 /P W M 1              P A 2 /A N 2 /T M R 0         4            2 1       P A 5 /A N 5 /P W M 1
      P A 1 /A N 1 /IN T 1     3            1 8      P A 6 /A N 6 /S D I/S D A            P A 1 /A N 1 /IN T 1        5            2 0       P A 6 /A N 6 /S D I/S D A
      P A 0 /A N 0 /IN T 0     4            1 7      P A 7 /A N 7 /S C K /S C L           P A 0 /A N 0 /IN T 0        6            1 9       P A 7 /A N 7 /S C K /S C L
         P B 0 /A N 8 /B Z     5            1 6      P D 2 /O S C 2                          P B 0 /A N 8 /B Z        7            1 8       P D 2 /O S C 2
  P B 1 /A N 9 /B Z /P C K     6            1 5      P D 1 /O S C 1                   P B 1 /A N 9 /B Z /P C K        8            1 7       P D 1 /O S C 1
    P B 2 /A N 1 0 /S D O      7            1 4      V D D /A V D D                     P B 2 /A N 1 0 /S D O         9            1 6       V D D /A V D D
     P B 3 /A N 1 1 /S C S     8            1 3      P D 0 /R E S                        P B 3 /A N 1 1 /S C S        1 0          1 5       P D 0 /R E S
            V S S /A V S S     9            1 2      P D 3 /O P V IN P /V R E F                 V S S /A V S S        1 1          1 4       P D 3 /O P V IN P /V R E F
         P D 5 /O P O U T      1 0          1 1      P D 4 /O P V IN N                       P D 5 /O P O U T         1 2          1 3       P D 4 /O P V IN N

                                  H T 4 5 R 5 2                                                                         H T 4 5 R 5 4
                             2 0 D IP -A /S O P -A                                                               2 4 S K D IP -A /S O P -A




                                                                                                P B 5 /A N 1 3            1        2 8       P B 6 /A N 1 4 /P W M 2
                                                                                       P B 4 /A N 1 2 /T M R 1            2        2 7       P B 7 /A N 1 5 /P W M 3
                                                                                           P A 3 /A N 3 /P F D            3        2 6       P A 4 /A N 4 /P W M 0
                                                                                        P A 2 /A N 2 /T M R 0             4        2 5       P A 5 /A N 5 /P W M 1
       P A 3 /A N 3 /P F D     1            2 0      P A 4 /A N 4 /P W M 0                P A 1 /A N 1 /IN T 1            5        2 4       P A 6 /A N 6 /S D I/S D A
    P A 2 /A N 2 /T M R 0      2            1 9      P A 5 /A N 5 /P W M 1                P A 0 /A N 0 /IN T 0            6        2 3       P A 7 /A N 7 /S C K /S C L
      P A 1 /A N 1 /IN T 1     3            1 8      P A 6 /A N 6 /S D I/S D A               P B 0 /A N 8 /B Z            7        2 2       P D 2 /O S C 2
      P A 0 /A N 0 /IN T 0     4            1 7      P A 7 /A N 7 /S C K /S C L       P B 1 /A N 9 /B Z /P C K            8        2 1       P D 1 /O S C 1
         P B 0 /A N 8 /B Z     5            1 6      P D 2 /O S C 2                     P B 2 /A N 1 0 /S D O             9        2 0       V D D /A V D D
  P B 1 /A N 9 /B Z /P C K     6            1 5      P D 1 /O S C 1                      P B 3 /A N 1 1 /S C S            1 0      1 9       P D 0 /R E S
    P B 2 /A N 1 0 /S D O      7            1 4      V D D /A V D D                             V S S /A V S S            1 1      1 8       P D 3 /O P V IN P /V R E F
     P B 3 /A N 1 1 /S C S     8            1 3      P D 0 /R E S                               P C 0 /A N 1 6            1 2      1 7       P D 4 /O P V IN N
            V S S /A V S S     9            1 2      P D 3 /O P V IN P /V R E F                 P C 1 /A N 1 7            1 3      1 6       P D 5 /O P O U T
         P D 5 /O P O U T      1 0          1 1      P D 4 /O P V IN N                          P C 2 /A N 1 8            1 4      1 5       P C 3 /A N 1 9

                                  H T 4 5 R 5 4                                                                         H T 4 5 R 5 4
                             2 0 D IP -A /S O P -A                                                               2 8 S K D IP -A /S O P -A




Rev. 1.00                                                                         3                                                      September 21, 2010
                                                                                  HT45R52/HT45R54

Pin Description
                        Configuration
     Pin Name     I/O                                                 Description
                           Option
                                         Bidirectional 8-bit input/output port. Each individual bit on this port
                                         can be configured as a wake-up input using the PAWU register. Soft-
                                         ware instructions determine if the pin is a CMOS output or Schmitt
                                         trigger input. A pull-high resistor can be connected to each pin using
PA0/AN0/INT0                             the PAPU register. PA is pin-shared with the A/D input pins. The A/D
PA1/AN1/INT1                             inputs are selected via software instructions. Once selected as an
PA2/AN2/TMR0                             A/D input, the I/O function and pull-high resistor selections are dis-
PA3/AN3/PFD                  PFD         abled automatically. Pins PA0~PA2 are pin-shared with INT0, INT1
                  I/O
PA4/AN4/PWM0                 SIM         and TMR for the HT45R52 or TMR0 for HT45R54 respectively. Pin
PA5/AN5/PWM1                             PA3 is shared with the PFD. The PFD function is chosen via configu-
PA6/AN6/SDI/SDA                          ration option. The PWM outputs, PWM0~PWM1, are pin shared with
PA7/AN7/SCK/SCL                          pins PA4~PA5, the function of which is chosen using the PWM regis-
                                         ters. PA6 is also pin-shared with the SPI bus data input line, SDI and
                                         the I2C Bus data line SDA. PA7 is also pin-shared with the SPI bus
                                         clock line, SCK, and the I2C Bus clock line SCL. Pins PA0~PA3 can
                                         also be setup as open drain pins using the MISC register.
                                         Bidirectional 4-bit input/output port. Software instructions determine
                                         if the pin is a CMOS output or Schmitt trigger input. A pull-high resis-
                                         tor can be connected to each pin using the PBPU register. PB0~PB3
                                         are pin-shared with the A/D input pins. The A/D inputs are selected
PB0/AN8/BZ
                                         via software instructions. Once selected as an A/D input, the I/O func-
PB1/AN9/BZ/PCK              BZ/BZ
                  I/O                    tion and pull-high resistor selections are disabled automatically. PB0
PB2/AN10/SDO                 SIM
                                         and PB1 are shared with BZ and BZ respectively, the function of
PB3/AN11/SCS
                                         which is chosen via configuration option. PB1 is pin-shared with the
                                         Peripheral Clock line, PCLK. PB2 is also pin-shared with the SPI bus
                                         data output line, SDO. PB3 is also pin-shared with the SPI bus select
                                         line, SCS
                                         Bidirectional line I/O. Software instructions determine if the pin is an
                                         NMOS output or Schmitt Trigger input. A configuration option deter-
PD0/RES           I/O    PD0 or RES
                                         mines if the pin is to be used as a RES pin or as an I/O pin. This pin
                                         does not have an internal pull-high function.
                                      Bidirectional 2-line I/O. Software instructions determine if the pins are
                                      CMOS outputs or Schmitt Trigger inputs. A pull high resistor can be
                                      connected to each pin using the PDPU register. Configuration op-
                                      tions determine if the pins are to be used as oscillator pins or I/O pins.
                                      Configuration options also determine which oscillator mode is se-
                        1.Int. RC OSC lected. The three oscillator modes are:
PD1/OSC1
                  I/O   2.Crystal OSC 1. Internal RC OSC: both pins configured as I/Os.
PD2/OSC2
                        3.Ext. RC OSC 2. External crystal OSC: both pins configured as OSC1/OSC2.
                                      3. External RC OSC+PD2: PD1 is configured as OSC1 pin, PD2 con-
                                      figured as an I/O.
                                      If the internal RC OSC is selected, the frequency will be fixed at either
                                      4MHz, 8MHz or 12MHz, dependent upon which configuration option
                                      is chosen.
                                         Bidirectional 3-line I/O. Software instructions determine if the pins are
                                         CMOS outputs or Schmitt Trigger inputs. A pull high resistor can be
                                         connected to each pin using the PDPU register. PD3 is pin-shared
                                         with the ADC reference voltage input pin VREF. The VREF input is
PD3/OPVINP/VREF
                                         selected via software instructions. Once selected as an ADC VREF
PD4/OPVINN        I/O         ¾
                                         input, the I/O function and pull-high resistor selections are disabled
PD5/OPOUT
                                         automatically. PD3~PD5 is also pin-shared with the OPA function
                                         pin. The OPA inputs and output are selected via software instruc-
                                         tions. Once selected as an OPA input or output, the I/O function and
                                         pull-high resistor selections are disabled automatically.
VDD/AVDD          ¾           ¾          Positive power supply/analog positive power supply.
VSS/AVSS          ¾           ¾          Negative power supply, ground/analog negative power supply, ground


Rev. 1.00                                          4                                        September 21, 2010
                                                                                                                         HT45R52/HT45R54

The following table is for the HT45R54 pins.

                                           Configuration
         Pin Name                 I/O                                                                    Description
                                              Option
                                                                   Bidirectional 4-bit input/output port. Software instructions determine
                                                                   if the pin is a CMOS output or Schmitt trigger input. A pull-high resis-
                                                                   tor can be connected to each pin using the PBPU register. PB4~PB7
 PB4/AN12/TMR1
                                                                   are pin-shared with the A/D input pins. The A/D inputs are selected
 PB5/AN13
                                  I/O               ¾              via software instructions. Once selected as an A/D input, the I/O func-
 PB6/AN14/PWM2
                                                                   tion and pull-high resistor selections are disabled automatically. Pin
 PB7/AN15/PWM3
                                                                   PB4 is pin-shared with TMR1. The PWM outputs, PWM2 and PWM3,
                                                                   are pin shared with pins PB6~PB7, the function of which is chosen
                                                                   using the PWM registers.
                                                                   Bidirectional 8-bit input/output port. Software instructions determine
                                                                   if the pin is a CMOS output or Schmitt trigger input. A pull-high resis-
 PC0/AN16~                                                         tor can be connected to each pin using the PCPU register. PC is
                                  I/O               ¾
 PC3/AN19                                                          pin-shared with the A/D input pins. The A/D inputs are selected via
                                                                   software instructions. Once selected as an A/D input, the I/O function
                                                                   and pull-high resistor selections are disabled automatically.


Absolute Maximum Ratings
Supply Voltage ...........................VSS-0.3V to VSS+6.0V                        Storage Temperature ............................-50°C to 125°C
Input Voltage..............................VSS-0.3V to VDD+0.3V                       Operating Temperature...........................-40°C to 85°C
IOL Total ................................................................80mA        IOH Total..............................................................-80mA
Total Power Dissipation .....................................500mW

Note: These are stress ratings only. Stresses exceeding the range specified under ²Absolute Maximum Ratings² may
      cause substantial damage to the device. Functional operation of this device at other conditions beyond those listed
      in the specification is not implied and prolonged exposure to extreme conditions may affect device reliability.


D.C. Characteristics                                                                                                                                 Ta=25°C

                                                                            Test Conditions
  Symbol                       Parameter                                                                          Min.        Typ.        Max.          Unit
                                                                 VDD                 Conditions
                                                                         fSYS=4MHz                                 2.2         ¾            5.5           V
 VDD            Operating Voltage                                 ¾      fSYS=8MHz                                 3.0         ¾            5.5           V
                                                                         fSYS=12MHz                                4.5         ¾            5.5           V
 AVDD           A/D Operating Voltage                             ¾                       ¾                        2.7         ¾            5.5           V

                Operating Current                                 3V                                                ¾         170          250           mA
 IDD1                                                                    No load, fSYS=fM=1MHz
                (Crystal OSC, RC OSC)                             5V                                                ¾         380          700           mA

                Operating Current                                 3V                                                ¾         240          360           mA
 IDD2                                                                    No load, fSYS=fM=2MHz
                (Crystal OSC, RC OSC)                             5V                                                ¾         490          800           mA

                Operating Current                                 3V     No load, fSYS=fM=4MHz                      ¾         440          660           mA
 IDD3
                (Crystal OSC, RC OSC)                             5V     (note 5)                                   ¾         900         1350           mA

                Operating Current                                 3V                                                ¾         380          570           mA
 IDD4                                                                    No load, fSYS=fM=4MHz
                (EC Mode, Filter On)                              5V                                                ¾         720         1080           mA
                Operating Current
 IDD5                                                             5V     No load, fSYS=fM=8MHz                      ¾          1.8          2.7          mA
                (Crystal OSC, RC OSC)
                Operating Current
 IDD6                                                             5V     No load, fSYS=fM=12MHz                     ¾          2.6          4.0          mA
                (Crystal OSC, RC OSC)



Rev. 1.00                                                                        5                                                   September 21, 2010
                                                                                          HT45R52/HT45R54

                                                        Test Conditions
 Symbol                Parameter                                                    Min.     Typ.      Max.     Unit
                                                VDD            Conditions
            Operating Current                   3V                                   ¾       150       220      mA
IDD7        (Slow Mode, fM=4MHz)                      No load, fSYS=fSLOW=500kHz
            (Crystal OSC, RC OSC)               5V                                   ¾       340       510      mA

            Operating Current                   3V                                   ¾       180       270      mA
IDD8        (Slow Mode, fM=4MHz)                      No load, fSYS=fSLOW=1MHz
            (Crystal OSC, RC OSC)               5V                                   ¾       400       600      mA

            Operating Current                   3V                                   ¾       270       400      mA
IDD9        (Slow Mode, fM=4MHz)                      No load, fSYS=fSLOW=2MHz
            (Crystal OSC, RC OSC)               5V                                   ¾       560       840      mA

            Operating Current                   3V                                   ¾       240       360      mA
IDD10       (Slow Mode, fM=8MHz)                      No load, fSYS=fSLOW=1MHz
            (Crystal OSC, RC OSC)               5V                                   ¾       540       810      mA

            Operating Current                   3V                                   ¾       320       480      mA
IDD11       (Slow Mode, fM=8MHz)                      No load, fSYS=fSLOW=2MHz
            (Crystal OSC, RC OSC)               5V                                   ¾       680       1020     mA

            Operating Current                   3V                                   ¾       500       750      mA
IDD12       (Slow Mode, fM=8MHz)                      No load, fSYS=fSLOW=4MHz
            (Crystal OSC, RC OSC)               5V                                   ¾       1000      1500     mA

            Operating Current                   3V                                   ¾        8         16      mA
IDD13                                                 No load, WDT off
            (fSYS=LIRC internal RC OSC)
                                                5V                                   ¾       15         30      mA

            Standby Current (Sleep)             3V    No load, system HALT,          ¾        ¾         1       mA
ISTB1
            (fSYS, fSUB, fS, fWDT=off)                WDT off
                                                5V                                   ¾        ¾         2       mA

            Standby Current (Sleep) (fSYS,      3V    No load, system HALT,          ¾        2         4       mA
ISTB2
            fWDT=fSUB=LIRC internal RC OSC)           WDT on
                                                5V                                   ¾        4         6       mA
            Standby Current (Idle)              3V
                                                      No load, system HALT,          ¾        2         4       mA
ISTB3       (fSYS, fWDT=off; fS=fSUB=LIRC
                                                5V    WDT off                        ¾        4         6       mA
            internal RC OSC)
            Standby Current ( Idle)                                                  ¾       150       250      mA
                                                3V    No load, system HALT,
            (fSYS=on, fSYS=fM=4MHz,
ISTB4                                                 WDT off, SPI or I2C on,
            fWDT, fS (note 3)=fSUB=LIRC
                                                5V    PCLK on, PCLK=fSYS/8           ¾       350       550      mA
            internal RC OSC)
            Input Low Voltage for I/O Ports,
VIL1                                            ¾                  ¾                  0       ¾       0.3VDD     V
            TMR and INT
            Input High Voltage for I/O Ports,
VIH1                                            ¾                  ¾                0.7VDD    ¾        VDD       V
            TMR and INT
VIL2        Input Low Voltage (RES)             ¾                  ¾                  0       ¾       0.4VDD     V
VIH2        Input High Voltage (RES)            ¾                  ¾                0.9VDD    ¾        VDD       V

                                                ¾     Configuration option: 2.1V     1.98    2.1       2.22      V
VLVR        Low Voltage Reset Voltage           ¾     Configuration option: 3.15V    2.98    3.15      3.32      V

                                                ¾     Configuration option: 4.2V     3.98    4.2       4.42      V

                                                ¾     Configuration option: 2.2V     2.08    2.2       2.32      V
VLVD        Low Voltage Detector Voltage        ¾     Configuration option: 3.3V     3.12    3.3       3.50      V

                                                ¾     Configuration option: 4.4V     4.12    4.4       4.70      V




Rev. 1.00                                                  6                                        September 21, 2010
                                                                                             HT45R52/HT45R54

                                                        Test Conditions
 Symbol                Parameter                                                       Min.       Typ.      Max.     Unit
                                                VDD             Conditions

            I/O Port Sink Current -             3V                                      6         12         ¾       mA
IOL1                                                  VOL=0.1VDD
            except PD0                          5V                                     10         25         ¾       mA

                                                3V                                     -2         -4         ¾       mA
IOH1        I/O Port Source Current                   VOH=0.9VDD
                                                5V                                     -5         -8         ¾       mA

                                                3V                                     0.8        1.5        ¾       mA
IOL2        PD0 Sink Current                          VOL=0.1VDD
                                                5V                                     2.0        4.0        ¾       mA

            Pull-high Resistance for I/O        3V                                     20         60        100      kW
RPH                                                                 ¾
            Ports                               5V                                     10         30         50      kW
VAD         A/D Input Voltage                    ¾                  ¾                   0         ¾         VREF      V
            A/D Input Reference Voltage
VREF                                             ¾    AVDD=5V                          1.6        ¾       AVDD+0.1    V
            Range
                                                      AVDD=5V, VREF=AVDD,
DNL         ADC Differential Non-Linearity       ¾                                     -2         ¾          2       LSB
                                                      tAD=0.5ms
                                                      AVDD=5V, VREF=AVDD,
INL         ADC Integral Non-Linearity           ¾                                     -4         ¾          4       LSB
                                                      tAD=0.5ms

            Additional Power Consumption        3V                                     ¾          0.5        1.0     mA
IADC                                                                ¾
            if A/D Converter is Used            5V                                     ¾          1.0        2.0     mA

Note:   1. fS is the internal clock for the Buzzer, RTC Interrupt, Time Base Interrupt and the WDT.
        2. Both Timer/Event Counters are off. Timer filter is disabled for all test conditions.
        3. All peripherals are in OFF condition if not mentioned at IDD, ISTB tests.




Rev. 1.00                                                   7                                            September 21, 2010
                                                                                       HT45R52/HT45R54

A.C. Characteristics                                                                                        Ta=25°C

                                                        Test Conditions
 Symbol                 Parameter                                                 Min.   Typ.      Max.      Unit
                                                VDD             Conditions
                                                      2.2V~5.5V                   400     ¾        4000      kHz
             System Clock
 fSYS1                                          ¾     3.0V~5.5V                   400     ¾        8000      kHz
             (Crystal OSC, ERC OSC)
                                                      4.5V~5.5V                   400     ¾        12000     kHz
                                                                                  -2%    4000       +2%      kHz
 fSYS2       System Clock (HIRC OSC)            5V                  ¾             -2%    8000       +2%      kHz
                                                                                  -2%    12000      +2%      kHz
 fSYS3       System Clock (LIRC)                ¾     2.2V~5.5V                    29     32         36      kHz
 f4MRCOSC    4MHz External RC OSC               5V    External R=150kW            -2%    4000       +2%      kHz
 fERC        External RC OSC                    5V    OSC1 connect 150kW to VDD   3920   4000      4480      kHz
                                                      2.2V~5.5V                    0      ¾        4000      kHz
             Timer I/P Frequency
 fTIMER                                         ¾     3.0V~5.5V                    0      ¾        8000      kHz
             (TMR0/TMR1)
                                                      4.5V~5.5V                    0      ¾        12000     kHz
 fRC32K      32K RC Period (LIRC)               ¾     2.2V~5.5V                   28.1   31.25      34.4      ms
 tRES        External Reset Low Pulse Width     ¾                   ¾              1      ¾          ¾        ms
 tLVR        Low Voltage Reset Time             ¾                   ¾             0.1     0.4       0.6       ms
 tSST1       System Start-up Timer Period       ¾     Power-on                     ¾     1024        ¾       tSYS*
             System Start-up Timer Period for         Wake-up from Power Down
 tSST2                                          ¾                                  ¾     1024        ¾       tSYS*
             XTAL                                     Mode
             System Start-up Timer Period for         Wake-up from Power Down
 tSST3                                          ¾                                  ¾      1          2       tSYS*
             RC or External Clock                     Mode
 tINT        Interrupt Pulse Width              ¾                   ¾              1      ¾          ¾        ms
 tAD         A/D Clock Period                   ¾                   ¾             0.5     ¾          ¾        ms
 tADC        A/D Conversion Time                ¾                   ¾              ¾      16         ¾        tAD

Note:     *TSYS=1/fSYS1, 1/fSYS2 or 1/fSYS3


OP Amplifier Electrical Characteristics                                                                     Ta=25°C

                                                        Test Conditions
 Symbol                 Parameter                                                 Min.   Typ.      Max.      Unit
                                                VDD             Conditions
D.C. Electrical Characteristic
VDD          Operating Voltage                  ¾                   ¾             2.7     ¾         5.5       V
VOS          Input Offset Voltage               5V    By calibration              -5      ¾          5       mV
VCM          Common Mode Voltage Range          ¾                   ¾             VSS     ¾       VDD-1.4     V
PSRR         Power Supply Rejection Ratio       ¾                   ¾             60      ¾          ¾        dB
                                                      VDD=5V
CMRR         Common Mode Rejection Ratio        ¾                                 60      ¾          ¾        dB
                                                      VCM=0~VDD-1.4V
A.C. Electrical Characteristic
AOL          Open Loop Gain                     ¾                   ¾             60      80         ¾        dB
SR           Slew Rate+, Rate-                  ¾     No load                      ¾      1          ¾       V/ms
GBW          Gain Band Width                    ¾     RL=1MW, CL=100pF             ¾      ¾         100      kHz



Rev. 1.00                                                  8                                    September 21, 2010
                                                                                              HT45R52/HT45R54

Power-on Reset Characteristics
                                                              Test Conditions
 Symbol               Parameter                                                       Min.     Typ.      Max.    Unit
                                                      VDD                Conditions
            VDD Start Voltage to Ensure
VPOR                                                  ¾                      ¾         ¾        ¾        100      mV
            Power-on Reset
            VDD raising rate to Ensure
RRVDD                                                 ¾                      ¾        0.035     ¾         ¾      V/ms
            Power-on Reset
            Minimum Time for VDD Stays at
tPOR                                                  ¾                      ¾         1        ¾         ¾       ms
            VPOR to Ensure Power-on Reset




  V   D D




                        tP   O R   R R   V D D


                                          V   P O R
                                                            T im e




Rev. 1.00                                                            9                                September 21, 2010
                                                                                                                                                                HT45R52/HT45R54

System Architecture
A key factor in the high-performance features of the                                                        ternally generated non-overlapping clocks, T1~T4. The
Holtek range of microcontrollers is attributed to their in-                                                 Program Counter is incremented at the beginning of the
ternal system architecture. The range of devices take                                                       T1 clock during which time a new instruction is fetched.
advantage of the usual features found within RISC                                                           The remaining T2~T4 clocks carry out the decoding and
microcontrollers providing increased speed of operation                                                     execution functions. In this way, one T1~T4 clock cycle
and enhanced performance. The pipelining scheme is                                                          forms one instruction cycle. Although the fetching and
implemented in such a way that instruction fetching and                                                     execution of instructions takes place in consecutive in-
instruction execution are overlapped, hence instructions                                                    struction cycles, the pipelining structure of the
are effectively executed in one cycle, with the exception                                                   microcontroller ensures that instructions are effectively
of branch or call instructions. An 8-bit wide ALU is used                                                   executed in one instruction cycle. The exception to this
in practically all instruction set operations, which carries                                                are instructions where the contents of the Program
out arithmetic operations, logic operations, rotation, in-                                                  Counter are changed, such as subroutine calls or
crement, decrement, branch decisions, etc. The internal                                                     jumps, in which case the instruction will take one more
data path is simplified by moving data through the Accu-                                                    instruction cycle to execute.
mulator and the ALU. Certain internal registers are im-
                                                                                                            For instructions involving branches, such as jump or call
plemented in the Data Memory and can be directly or                                                         instructions, two machine cycles are required to com-
indirectly addressed. The simple addressing methods of
                                                                                                            plete instruction execution. An extra cycle is required as
these registers along with additional architectural fea-
                                                                                                            the program takes one cycle to first obtain the actual
tures ensure that a minimum of external components is
                                                                                                            jump or call address and then another cycle to actually
required to provide a functional I/O and A/D control sys-
                                                                                                            execute the branch. The requirement for this extra cycle
tem with maximum reliability and flexibility. This makes
                                                                                                            should be taken into account by programmers in timing
the device suitable for low-cost, high-volume production
                                                                                                            sensitive applications.
for controller applications.

Clocking and Pipelining
The main system clock, derived from either a Crys-
tal/Resonator or RC oscillator is subdivided into four in-



                     O s c illa to r C lo c k
                      ( S y s te m C lo c k )

                    P h a s e C lo c k T 1

                    P h a s e C lo c k T 2

                    P h a s e C lo c k T 3

                    P h a s e C lo c k T 4


                  P ro g ra m      C o u n te r                   P C                                     P C + 1                                     P C + 2


                                                     F e tc h In s t. (P C )
                                P ip e lin in g
                                                      E x e c u te In s t. (P C -1 )           F e tc h In s t. (P C + 1 )
                                                                                                E x e c u te In s t. (P C )               F e tc h In s t. (P C + 2 )
                                                                                                                                           E x e c u te In s t. (P C + 1 )

                                                                    System Clocking and Pipelining




              1                     M O V A ,[1 2 H ]                   F e tc h In s t. 1   E x e c u te In s t. 1
              2                     C A L L D E L A Y                                          F e tc h In s t. 2       E x e c u te In s t. 2
              3                     C P L [1 2 H ]                                                                        F e tc h In s t. 3       F lu s h P ip e lin e
              4                     :                                                                                                               F e tc h In s t. 6       E x e c u te In s t. 6
              5                     :                                                                                                                                          F e tc h In s t. 7
              6   D E L A Y :       N O P

                                                                                   Instruction Fetching



Rev. 1.00                                                                                          10                                                                           September 21, 2010
                                                                                               HT45R52/HT45R54

Program Counter                                                    The lower byte of the Program Counter, known as the
During program execution, the Program Counter is used              Program Counter Low register or PCL, is available for
to keep track of the address of the next instruction to be         program control and is a readable and writable register.
executed. It is automatically incremented by one each              By transferring data directly into this register, a short pro-
time an instruction is executed except for instructions,           gram jump can be executed directly, however, as only
such as ²JMP² or ²CALL² that demand a jump to a                    this low byte is available for manipulation, the jumps are
non-consecutive Program Memory address. It must be                 limited to the present page of memory, that is 256 loca-
noted that only the lower 8 bits, known as the Program             tions. When such program jumps are executed it should
Counter Low Register, are directly addressable.                    also be noted that a dummy cycle will be inserted.

When executing instructions requiring jumps to                     The lower byte of the Program Counter is fully accessi-
non-consecutive addresses such as a jump instruction,              ble under program control. Manipulating the PCL might
a subroutine call, interrupt or reset, etc., the                   cause program branching, so an extra cycle is needed
microcontroller manages program control by loading the             to pre-fetch. Further information on the PCL register can
required address into the Program Counter. For condi-              be found in the Special Function Register section.
tional skip instructions, once the condition has been
met, the next instruction, which has already been
fetched during the present instruction execution, is dis-
carded and a dummy cycle takes its place while the cor-
rect instruction is obtained.



                                                                     Program Counter Bits
                  Mode
                                       b11    b10     b9     b8       b7     b6      b5      b4     b3      b2     b1      b0
 Initial Reset                          0      0      0       0        0      0       0      0       0      0       0       0
 External Interrupt 0                   0      0      0       0        0      0       0      0       0      1       0       0
 External Interrupt 1                   0      0      0       0        0      0       0      0       1      0       0       0
 Timer/Event Counter 0 Overflow         0      0      0       0        0      0       0      0       1      1       0       0
 A/D Converter Interrupt                0      0      0       0        0      0       0      1       0      0       0       0
        2
 SPI/I C Interrupt                      0      0      0       0        0      0       0      1       0      1       0       0
 Multi-Function Interrupt               0      0      0       0        0      0       0      1       1      0       0       0
 Skip                                                                 Program Counter + 2
 Loading PCL                          PC11 PC10 PC9          PC8     @7      @6     @5      @4      @3     @2      @1     @0
 Jump, Call Branch                     #11    #10     #9     #8       #7     #6      #5      #4     #3      #2     #1      #0
 Return from Subroutine                S11    S10     S9     S8       S7     S6      S5     S4      S3      S2     S1      S0

                                                    Program Counter

Note:       PC11~PC8: Current Program Counter bits             @7~@0: PCL bits
            #11~#0: Instruction code address bits              S11~S0: Stack register bits
            For the HT45R54, the Program Counter is 12 bits wide, i.e. from b11~b0.
            For the HT45R52, the Program Counter is 11 bits wide, i.e. from b10~b0, therefore the b11 column in the ta-
            ble is not applicable.




Rev. 1.00                                                    11                                          September 21, 2010
                                                                                                                     HT45R52/HT45R54

Stack                                                                                    · Logic operations: AND, OR, XOR, ANDM, ORM,
                                                                                           XORM, CPL, CPLA
This is a special part of the memory which is used to
                                                                                         · Rotation RRA, RR, RRCA, RRC, RLA, RL, RLCA,
save the contents of the Program Counter only. The
stack has multiple levels depending upon the device                                        RLC
and is neither part of the data nor part of the program                                  · Increment and Decrement INCA, INC, DECA, DEC
space, and is neither readable nor writeable. The acti-                                  · Branch decision, JMP, SZ, SZA, SNZ, SIZ, SDZ,
vated level is indexed by the Stack Pointer, SP, and is                                    SIZA, SDZA, CALL, RET, RETI
neither readable nor writeable. At a subroutine call or in-
terrupt acknowledge signal, the contents of the Program                                  Program Memory
Counter are pushed onto the stack. At the end of a sub-
                                                                                         The Program Memory is the location where the user
routine or an interrupt routine, signaled by a return in-
                                                                                         code or program is stored. For these device the Pro-
struction, RET or RETI, the Program Counter is restored
                                                                                         gram Memory is an OTP type, which means it can be
to its previous value from the stack. After a device reset,
                                                                                         programmed only one time. By using the appropriate
the Stack Pointer will point to the top of the stack.
                                                                                         programming tools, this OTP memory device offer users
                                                       P ro g ra m   C o u n te r        the flexibility to conveniently debug and develop their
                                                                                         applications while also offering a means of field pro-
                                                                                         gramming.
          T o p o f S ta c k    S ta c k L e v e l 1

                                S ta c k L e v e l 2                                     Structure
   S ta c k                                                  P ro g ra m
                                S ta c k L e v e l 3
 P o in te r                                                  M e m o ry                 The Program Memory has a capacity of 2K´15 bits or
                                                                                         4K´15 bits. The Program Memory is addressed by the
    B o tto m    o f S ta c k   S ta c k L e v e l N
                                                                                         Program Counter and also contains data, table informa-
                                                                                         tion and interrupt entries. Table data, which can be
                                                                                         setup in any location within the Program Memory, is ad-
If the stack is full and an enabled interrupt takes place,                               dressed by a separate table pointer register.
the interrupt request flag will be recorded but the ac-
knowledge signal will be inhibited. When the Stack                                       Special Vectors
Pointer is decremented, by RET or RETI, the interrupt
                                                                                         Within the Program Memory, certain locations are re-
will be serviced. This feature prevents stack overflow al-
                                                                                         served for special usage such as reset and interrupts.
lowing the programmer to use the structure more easily.
However, when the stack is full, a CALL subroutine in-                                   · Location 000H
struction can still be executed which will result in a stack                               This vector is reserved for use by the device reset for
overflow. Precautions should be taken to avoid such                                        program initialisation. After a device reset is initiated, the
                                                                                           program will jump to this location and begin execution.
cases which might cause unpredictable program
branching.                                                                               · Location 004H
                                                                                           This vector is used by the external interrupt 0. If the
Note:           4 levels of stack are available for the HT45R52
                                                                                           external interrupt pin receives an active edge, the pro-
                and 8 levels of stack are available for the
                                                                                           gram will jump to this location and begin execution if
                HT45R54.                                                                   the external interrupt is enabled and the stack is not
                                                                                           full.
Arithmetic and Logic Unit - ALU
                                                                                         · Location 008H
The arithmetic-logic unit or ALU is a critical area of the
                                                                                           This vector is used by the external interrupt 1. If the
microcontroller that carries out arithmetic and logic oper-                                external interrupt pin receives an active edge, the pro-
ations of the instruction set. Connected to the main                                       gram will jump to this location and begin execution if
microcontroller data bus, the ALU receives related in-                                     the external interrupt is enabled and the stack is not
struction codes and performs the required arithmetic or                                    full.
logical operations after which the result will be placed in
                                                                                         · Location 00CH
the specified register. As these ALU calculation or oper-
                                                                                           This internal vector is used by the Timer/Event Coun-
ations may result in carry, borrow or other status                                         ter 0. If a Timer/Event Counter 0 overflow occurs, the
changes, the status register will be correspondingly up-                                   program will jump to this location and begin execution
dated to reflect these changes. The ALU supports the                                       if the timer/event counter interrupt is enabled and the
following functions:                                                                       stack is not full.
· Arithmetic operations: ADD, ADDM, ADC, ADCM,
  SUB, SUBM, SBC, SBCM, DAA




Rev. 1.00                                                                           12                                          September 21, 2010
                                                                                                                                            HT45R52/HT45R54

· Location 010H                                                                                 · Location 018H
 This internal vector is used by the A/D converter. If an                                         This internal vector is used by the Multi-function Inter-
 A/D converter conversion completion occurs, the pro-                                             rupt. The Multi-function Interrupt vector is shared by
 gram will jump to this location and begin execution if                                           several internal functions such as a Time Base over-
 the A/D converter interrupt is enabled and the stack is                                          flow, a RTC interrupt request flag is set or a Timer/
 not full.                                                                                        Event Counter 1 overflow. The program will jump to
                                                                                                  this location and begin execution if the relevant inter-
· Location 014H
                                                                                                  rupt is enabled and the stack is not full.
 This internal vector is used by the SPI/I2C interrupt.
 When either an SPI or I2C bus, dependent upon which
                                                                                                Look-up Table
 one is selected, requires data transfer, the program
 will jump to this location and begin execution if the                                          Any location within the Program Memory can be defined
 SPI/I2C interrupt is enabled and the stack is not full.                                        as a look-up table where programmers can store fixed
                                                                                                data. To use the look-up table, the table pointer must
                       H T 4 5 R 5 2                    H T 4 5 R 5 4
                                                                                                first be setup by placing the lower order address of the
   0 0 0 H
                     In itia lis a tio n               In itia lis a tio n                      look up data to be retrieved in the table pointer register,
                         V e c to r                        V e c to r                           TBLP. This register defines the lower 8-bit address of
   0 0 4 H
                    E x te rn a l IN T 0              E x te rn a l IN T 0                      the look-up table.
                  In te rru p t V e c to r          In te rru p t V e c to r
                                                                                                After setting up the table pointer, the table data can be
   0 0 8 H
                    E x te rn a l IN T 1              E x te rn a l IN T 1                      retrieved from the current Program Memory page or last
                  In te rru p t V e c to r          In te rru p t V e c to r
                                                                                                Program Memory page using the ²TABRDC[m]² or
   0 0 C H
                  T im e r C o u n te r 0           T im e r C o u n te r 0                     ²TABRDL [m]² instructions, respectively. When these in-
                   In te rru p t V e c to r          In te rru p t V e c to r
                                                                                                structions are executed, the lower order table byte from
   0 1 0 H
                    A /D C o n v e rte r             A /D C o n v e rte r                       the Program Memory will be transferred to the user de-
                  In te rru p t V e c to r          In te rru p t V e c to r
                                                                                                fined Data Memory register [m] as specified in the in-
   0 1 4 H
                         S P I/I2C                        S P I/I2C                             struction. The higher order table data byte from the
                  In te rru p t V e c to r          In te rru p t V e c to r
                                                                                                Program Memory will be transferred to the TBLH special
   0 1 8 H
                   M u lti_ F u n c tio n            M u lti_ F u n c tio n                     register. Any unused bits in this transferred higher order
                  In te rru p t V e c to r          In te rru p t V e c to r
                                                                                                byte will be read as ²0².
   0 1 C H
                                                                                                The following diagram illustrates the addressing/data
                                                                                                flow of the look-up table:
   7 0 0 H

   7 F F H                                                                                        P ro g ra m C o u n te r
    8 0 0 H                                                                                             H ig h B y te                               P ro g ra m
                                                                                                                                                     M e m o ry
   F F F H                                                                                               T B L P
                         1 5 b its                         1 5 b its

                   N o t Im p le m e n te d
                                                                                                                                      T B L H                     S p e c ifie d b y [m ]
                  Program Memory Structure
                                                                                                                   T a b le C o n te n ts H ig h B y te      T a b le C o n te n ts L o w    B y te




                                                                                           Table Location Bits
  Instruction
                                b11           b10           b9               b8       b7        b6          b5               b4            b3             b2               b1               b0
 TABRDC [m]                   PC11            PC10        PC9                PC8      @7        @6         @5                @4           @3              @2              @1                @0
 TABRDL [m]                       1            1             1                  1     @7        @6         @5                @4           @3              @2              @1                @0

                                                                                    Table Location

Note:         PC11~PC8: Current program counter bits              @7~@0: Table Pointer TBLP bits
              For the HT45R54, the Table address location is 12 bits, i.e. from b11~b0.
              For the HT45R52, the Table address location is 11 bits, i.e. from b10~b0.




Rev. 1.00                                                                                  13                                                                September 21, 2010
                                                                                             HT45R52/HT45R54

Table Program Example                                               Because the TBLH register is a read-only register and
The following example shows how the table pointer and               cannot be restored, care should be taken to ensure its
table data is defined and retrieved from the                        protection if both the main routine and Interrupt Service
microcontroller. This example uses raw table data lo-               Routine use table read instructions. If using the table
cated in the last page which is stored there using the              read instructions, the Interrupt Service Routines may
ORG statement. The value at this ORG statement is                   change the value of the TBLH and subsequently cause
²700H² which refers to the start address of the last page           errors if used again by the main routine. As a rule it is
within the 2K Program Memory of the HT45R52. The ta-                recommended that simultaneous use of the table read
                                                                    instructions should be avoided. However, in situations
ble pointer is setup here to have an initial value of ²06H².
                                                                    where simultaneous use cannot be avoided, the inter-
This will ensure that the first data read from the data ta-
                                                                    rupts should be disabled prior to the execution of any
ble will be at the Program Memory address ²706H² or 6
                                                                    main routine table-read instructions. Note that all table
locations after the start of the last page. Note that the
                                                                    related instructions require two instruction cycles to
value for the table pointer is referenced to the first ad-
                                                                    complete their operation.
dress of the present page if the ²TABRDC [m]² instruc-
tion is being used. The high byte of the table data which
in this case is equal to zero will be transferred to the
TBLH register automatically when the ²TABRDL [m]² in-
struction is executed.




Tempreg1 db           ?          ; temporary register #1
tempreg2 db           ?          ; temporary register #2
    :
    :
mov          a,06h               ; initialise table pointer - note that this address is referenced
mov          tblp,a              ; to the last page or present page
      :
      :
tabrdl       tempreg1            ;   transfers value in table referenced by table pointer
                                 ;   to tempregl
                                 ;   data at prog. memory address ²706H² transferred to
                                 ;   tempreg1 and TBLH
dec tblp                         ; reduce value of table pointer by one
tabrdl       tempreg2            ;   transfers value in table referenced by table pointer
                                 ;   to tempreg2
                                 ;   data at prog.memory address ²705H² transferred to
                                 ;   tempreg2 and TBLH
                                 ;   in this example the data ²1AH² is transferred to
                                 ;   tempreg1 and data ²0FH² to register tempreg2
      :
      :
org 700h                         ; sets initial address of last page
dc    00Ah, 00Bh, 00Ch, 00Dh, 00Eh, 00Fh, 01Ah, 01Bh
      :
      :




Rev. 1.00                                                      14                                      September 21, 2010
                                                                                               HT45R52/HT45R54

Data Memory
The Data Memory is a volatile area of 8-bit wide RAM                General Purpose Data Memory
internal memory and is the location where temporary in-             All microcontroller programs require an area of
formation is stored. Divided into two sections, the first of        read/write memory where temporary data can be stored
these is an area of RAM where special function registers            and retrieved for use later. It is this area of RAM memory
are located. These registers have fixed locations and               that is known as General Purpose Data Memory. This
are necessary for correct operation of the device. Many
                                                                    area of Data Memory is fully accessible by the user pro-
of these registers can be read from and written to di-
                                                                    gram for both read and write operations. By using the
rectly under program control, however, some remain
                                                                    ²SET [m].i² and ²CLR [m].i² instructions, individual bits
protected from user manipulation. The second area of
                                                                    can be set or reset under program control giving the
Data Memory is reserved for general purpose use. All
                                                                    user a large range of flexibility for bit manipulation in the
locations within this area are read and write accessible
                                                                    Data Memory. The HT45R54 has its Data Memory sub-
under program control. For the HT45R54, which has its
                                                                    divided into two banks.
Data Memory located in two banks, a Bank Pointer is
used to select the required bank.                                   Special Purpose Data Memory

Structure                                                           This area of Data Memory is where registers, necessary
                                                                    for the correct operation of the microcontroller, are
The Data Memory located in Bank 0 is subdivided into
                                                                    stored. Most of the registers are both read and write type
two sections, the Special Purpose Data Memory and the
                                                                    but some are protected and are read only, the details of
General Purpose Data Memory.
                                                                    which are located under the relevant Special Function
The start address of the Data Memory for all devices is             Register section. Note that for locations that are unused,
the address ²00H². Registers which are common to all                any read instruction to these addresses will return the
devices, such as ACC, PCL, etc., have the same Data                 value ²00H². In the HT45R54 the Special Function reg-
Memory address. Bank 1 only exists for the HT45R54                  isters are mapped into both banks and can therefore be
and contains only General Purpose Data Memory. As                   accessed from any bank location.
the Special Purpose Data Memory registers are
mapped into all bank areas, they can subsequently be                           Bank Number                     0          1
accessed from any bank location.                                                                   SA        00H          x
                                                                                      SPDM
                                                                       HT45R52                     EA        3FH          x
                                0 0 H
                                                                     - 192 Bytes                   SA        40H          x
  S p e c ia l P u r p o s e                                                          GPDM
   D a ta M e m o ry                                                                               EA        FFH          x
                                                                                                   SA        Common 00H
                               3 F H                                                  SPDM
                                4 0 H                                  HT45R54                     EA        Common 3FH
                                                                     - 384 Bytes                   SA        40H        40H
  G e n e ra l P u rp o s e                                                           GPDM
   D a ta M e m o ry                                                                               EA        FFH        FFH

                                          B a n k 0                                  Data Memory Content
                               F F H
                                                B a n k 1           Note:    SPDM: Special Purpose Data Memory
                                                                             GPDM: General Purpose Data Memory
                           Data Memory Structure
                                                                             SA: Start Address
                                                                             EA: End Address
                                                                             x: Not implemented




Rev. 1.00                                                      15                                         September 21, 2010
                                                                                                                                                                                                     HT45R52/HT45R54

                                                                               H T 4 5 R 5 2                               H T 4 5 R 5 4
                                                                                                                                                                          Special Function Registers
                           0 0 H                                                           IA       R 0                              IA R 0
                            0 1 H                                                            M    P 0                                 P 0
                                                                                                                                       M                                  To ensure successful operation of the microcontroller,
                             0 2 H                                                         IA      R 1                               IAR 1                                certain internal registers are implemented in the Data
                              0 3 H                                                        M     P 1                                 P 1
                                                                                                                                     M
                               0 4 H                                                                                               B P                                    Memory area. These registers ensure correct operation
                                0 5 H                                                A C C                                       A C C                                    of internal functions such as timers, interrupts, etc., as
                                 0 6 H                                                P C L                                       P C L                                   well as external functions such as I/O data control and
                                  0 7 H                                             T B L P                                     T B L P
                                                                                                                                                                          A/D converter operation. The location of these registers
                                   0 8 H                                           T B L H                                     T B L H
                                    0 9 H                                         R T C C                                     R T C C                                     within the Data Memory begins at the address 00H. Any
           0 A H                                                                S T A T U S                                 S T A T U S                                   unused Data Memory locations between these special
            0 B H                                                                 IN T C 0                                    IN T C 0                                    function registers and the point where the General Pur-
   0 C H
    0 D H                                                                                  T M R 0                                                  T M R 0
                                                                                                                                                                          pose Memory begins is reserved for future expansion
             0 E H                                                                       T M R 0 C                                     T M R 0 C                          purposes, attempting to read data from these locations
                       0 F H                                                                                                            T M R 1 H                         will return a value of 00H.
                                               1 0 H                                                                                        T M R 1 L
                                                1 1 H                                                                                 T M R 1 C
                                                 1 2 H                                        P A                                                             P A
                                                                                                                                                                          Indirect Addressing Registers - IAR0, IAR1
                                                  1 3 H                                    P A C                                                          P A C           The Indirect Addressing Registers, IAR0 and IAR1, al-
                                                   1 4 H                                       P B                                                             P B
                                                    1 5 H                                   P B C                                                          P B C          though having their locations in normal RAM register
                                                     1 6 H                                                                                                  P C           space, do not actually physically exist as normal regis-
                                                      1 7 H                                                                                             P C C             ters. The method of indirect addressing for RAM data
                                                       1 8 H                                     P D                                                         P D
                                                                                                                                                                          manipulation uses these Indirect Addressing Registers
                                                        1 9 H                                  P D C                                                     P D C
              1 A H                                                                  P       W M 0 L                              P W M 0 L                               and Memory Pointers, in contrast to direct memory ad-
               1 B H                                                             P         W M 0 H                            P W M 0 H                                   dressing, where the actual memory address is speci-
     1 C H                                                                           P        W M 1 L                              P W M 1 L                              fied. Actions on the IAR0 and IAR1 registers will result in
      1 D H                                                                      P          W M 1 H                              P W M 1 H
                1 E H                                                                    IN T C 1                                             IN T C 1                    no actual read or write operation to these registers but
                        1 F H                                                             M F IC                                                       M F IC             rather to the memory location specified by their corre-
                                     2 0 H                                                                                          P W M 2 L                             sponding Memory Pointers, MP0 or MP1. Acting as a
                                      2 1 H                                                                                    P W M 2 H
                                                                                                                                                                          pair, IAR0 and MP0 can together access data from Bank
                                       2 2 H                                                                                         P W M 3 L
                                        2 3 H                                                                                   P W M 3 H                                 0 while the IAR1 and MP1 register pair can access data
                                         2 4 H                                         A D           R L                                             A D R L              from any bank. As the Indirect Addressing Registers are
                                          2 5 H                                       A D           R H                                        A D R H                    not physically implemented, reading the Indirect Ad-
                                           2 6 H                                   A D           C R         0                           A D C R 0
                                            2 7 H                                   A D           C R        1                            A D C R 1                       dressing Registers indirectly will return a result of ²00H²
                                             2 8 H                                   A D           C R       2                             A D C R 2                      and writing to the registers indirectly will result in no op-
                                              2 9 H                             A N C                 S R        0         A N C S R 0                                    eration.
                 2 A H                                                           A N C                 S R       1          A N C S R 1
                  2 B H                                                                                                      A N C S R 2
       2 C H                                                                      O P                A C                                      O P A C                     Memory Pointers - MP0, MP1
        2 D H                                                                  C L K             M O D                    C L K M O D
                                                                                                                                                                          Two Memory Pointers, known as MP0 and MP1 are pro-
                   2 E H                                                         P A              W U                                        P A W U
                         2 F H                                                     P A             P U                                            P A P U                 vided. These Memory Pointers are physically imple-
                                                         3 0 H                      P B             P U                                            P B P U                mented in the Data Memory and can be manipulated in
                                                          3 1 H                                                                                 P C P U                   the same way as normal registers providing a conve-
                                                           3 2 H                  P D P U                                                        P D P U
                                                            3 3 H              IN T E D G E                               IN T E D G E
                                                                                                                                                                          nient way with which to address and track data. When
                                                             3 4 H                 M IS C                                                             M IS C              any operation to the relevant Indirect Addressing Regis-
                                                              3 5 H                                                                                                       ters is carried out, the actual address that the
                                                               3 6 H           S IM C                T L 0                S IM C                    T L 0                 microcontroller is directed to, is the address specified by
                                                                3 7 H           S IM C                T L 1                S IM C                    T L 1
                                                                 3 8 H            S IM              D R                      S IM                  D R                    the related Memory Pointer. MP0, together with Indirect
                                                                  3 9 H   S IM A R /S                IM C T L 2      S IM A R /S                    IM C T L 2            Addressing Register, IAR0, are used to access data
                    3 A H                                                                                                                                                 from Bank 0, while MP1 and IAR1 are used to access
                     3 B H
         3 C H
                                                                                                                                                                          data from all banks.
          3 D H
                      3 E H
                          3 F H

                                                                            : U n u s e d R e a d a s "0 0 "

                                                                          Special Purpose Data Memory




Rev. 1.00                                                                                                                                                            16                                         September 21, 2010
                                                                                                         HT45R52/HT45R54

The following example shows how to clear a section of four RAM locations already defined as locations adres1 to
adres4.
data .section ¢data¢
adres1      db ?
adres2      db ?
Adres3      db ?
adres4      db ?
block       db ?
code .section at 0 ¢code¢
org 00h
start:
    mov     a,04h                   ; setup size of block
    mov     block,a
    mov     a,offset adres1         ; Accumulator loaded with first RAM address
    mov     mp0,a                   ; setup memory pointer with first RAM address
loop:
    clr     IAR0                    ; clear the data at address defined by MP0
    inc     mp0                     ; increment memory pointer
    sdz     block                   ; check if last memory location has been cleared
    jmp     loop
continue:

The important point to note here is that in the example shown above, no reference is made to specific RAM addresses.




Bank Pointer - BP                                                where all intermediate results from the ALU are stored.
In the HT45R54, the Data Memory is subdivided into               Without the Accumulator it would be necessary to write
two banks. Selecting the required Data Memory area is            the result of each calculation or logical operation such
achieved using the Bank Pointer. If data in Bank 0 is to         as addition, subtraction, shift, etc., to the Data Memory
be accessed, then the BP register must be loaded with            resulting in higher programming and timing overheads.
the value 00H, while if data in Bank 1 is to be accessed,        Data transfer operations usually involve the temporary
then the BP register must be loaded with the value 01H,          storage function of the Accumulator; for example, when
and so on.                                                       transferring data between one user defined register and
                                                                 another, it is necessary to do this by passing the data
The Data Memory is initialised to Bank 0 after a reset,          through the Accumulator as no direct transfer between
except for the WDT time-out reset in the Power Down              two registers is permitted.
Mode, in which case, the Data Memory bank remains
unaffected. It should be noted that the Special Function         Program Counter Low Register - PCL
Data Memory is not affected by the bank selection,
                                                                 To provide additional program control functions, the low
which means that the Special Function Registers can be
                                                                 byte of the Program Counter is made accessible to pro-
accessed from within any bank. Directly addressing the
                                                                 grammers by locating it within the Special Purpose area
Data Memory will always result in Bank 0 being ac-
                                                                 of the Data Memory. By manipulating this register, direct
cessed irrespective of the value of the Bank Pointer. Ac-
                                                                 jumps to other program locations are easily imple-
cessing data from banks other than Bank 0 must be
                                                                 mented. Loading a value directly into this PCL register
implemented using Indirect addressing.
                                                                 will cause a jump to the specified Program Memory lo-
Accumulator - ACC                                                cation, however, as the register is only 8-bit wide, only
                                                                 jumps within the current Program Memory page are per-
The Accumulator is central to the operation of any               mitted. When such operations are used, note that a
microcontroller and is closely related with operations           dummy cycle will be inserted.
carried out by the ALU. The Accumulator is the place



                         b 7                                        b 0
                                                                  B P 0   B P R e g is te r

                                                                          B P 0     D a ta M e m o ry
                                                                             0       B a n k 0
                                                                               1      B a n k 1
                                                                          N o t u s e d , m u s t b e re s e t to "0 "

                                                    Bank Pointer



Rev. 1.00                                                   17                                                           September 21, 2010
                                                                                                                                 HT45R52/HT45R54

Look-up Table Registers - TBLP, TBLH                                    · OV is set if an operation results in a carry into the high-
                                                                              est-order bit but not a carry out of the highest-order bit,
These two special function registers are used to control
                                                                              or vice versa; otherwise OV is cleared.
operation of the look-up table which is stored in the Pro-
                                                                        · PDF is cleared by a system power-up or executing the
gram Memory. TBLP is the table pointer and indicates
                                                                              ²CLR WDT² instruction. PDF is set by executing the
the location where the table data is located. Its value
                                                                              ²HALT² instruction.
must be setup before any table read commands are ex-
                                                                        · TO is cleared by a system power-up or executing the
ecuted. Its value can be changed, for example using the
                                                                              ²CLR WDT² or ²HALT² instruction. TO is set by a
²INC² or ²DEC² instructions, allowing for easy table data
                                                                              WDT time-out.
pointing and reading. TBLH is the location where the
high order byte of the table data is stored after a table               In addition, on entering an interrupt sequence or execut-
read data instruction has been executed. Note that the                  ing a subroutine call, the status register will not be
lower order table data byte is transferred to a user de-                pushed onto the stack automatically. If the contents of
fined location.                                                         the status registers are important and if the subroutine
                                                                        can corrupt the status register, precautions must be
Status Register - STATUS                                                taken to correctly save it.
This 8-bit register contains the zero flag (Z), carry flag
                                                                        Interrupt Control Registers
(C), auxiliary carry flag (AC), overflow flag (OV), power
down flag (PDF), and watchdog time-out flag (TO).                       These 8-bit registers, INTC0, INTC1, MFIC and
These arithmetic/logical operation and system manage-                   INTEDGE, control the operation of the device interrupt
ment flags are used to record the status and operation of               functions. By setting various bits within these registers
the microcontroller.                                                    using standard bit manipulation instructions, the en-
                                                                        able/disable function of each interrupt can be independ-
With the exception of the TO and PDF flags, bits in the
                                                                        ently controlled. A master interrupt bit within the INTC0
status register can be altered by instructions like most
                                                                        register, the EMI bit, acts like a global enable/disable and
other registers. Any data written into the status register
                                                                        is used to set all of the interrupt enable bits on or off. This
will not change the TO or PDF flag. In addition, opera-
                                                                        bit is cleared when an interrupt routine is entered to dis-
tions related to the status register may give different re-
                                                                        able further interrupt and is set by executing the ²RETI²
sults due to the different instruction operations. The TO
                                                                        instruction. The INTEDGE register is used to select the
flag can be affected only by a system power-up, a WDT
                                                                        active edges for the two external interrupt pins INT0 and
time-out or by executing the ²CLR WDT² or ²HALT² in-
                                                                        INT1.
struction. The PDF flag is affected only by executing the
²HALT² or ²CLR WDT² instruction or during a system                      Timer/Event Counter Registers
power-up.
                                                                        The devices contain several internal 8-bit and 16-bit
The Z, OV, AC and C flags generally reflect the status of               Timer/Event Counters, the actual amount depends upon
the latest operations.                                                  which device is selected. The registers TMR0 and the
· C is set if an operation results in a carry during an ad-             register pair TMR1L/TMR1H are the locations where the
  dition operation or if a borrow does not take place dur-              timer values are located. These registers can also be
  ing a subtraction operation; otherwise C is cleared. C                preloaded with fixed data to allow different time intervals
  is also affected by a rotate through carry instruction.               to be setup. The associated control registers, TMR0C
· AC is set if an operation results in a carry out of the               and TMR1C contain the setup information for these
  low nibbles in addition, or no borrow from the high nib-              timers, which determines in what mode the timer is to be
  ble into the low nibble in subtraction; otherwise AC is               used as well as containing the timer on/off control
  cleared.
                                                                        function.
· Z is set if the result of an arithmetic or logical operation
  is zero; otherwise Z is cleared.

                         b 7                                            b 0
                                     T O   P D F   O V   Z       A C    C         S T A T U S R e g is te r

                                                                                      ith m e
                                                                                     A r                tic /L o g ic O p e r a tio n F la g s
                                                                                  C a   r r y fla   g
                                                                                   A u x ilia r y       c a r r y fla g
                                                                                      r o fla g
                                                                                    Z e
                                                                                  O v e r flo w          fla g

                                                                                     S y s te m M          a n      a g e m e n t F la g s
                                                                                  P o w e r d o w            n      fla g
                                                                                   W a tc h d o g           tim      e - o u t fla g
                                                                                    N o t im p le m            e   n te d , re a d a s "0 "
                                                         Status Register


Rev. 1.00                                                          18                                                                         September 21, 2010
                                                                                               HT45R52/HT45R54

Input/Output Ports and Control Registers                            Port A Wake-up Register - PAWU
Within the area of Special Function Registers, the I/O              All pins on Port A have a wake-up function enable a low
registers and their associated control registers play a             going edge on these pins to wake-up the device when it
prominent role. All I/O ports have a designated register            is in a power down mode. The pins on Port A that are
correspondingly labeled as PA, PB, PC and PD. These                 used to have a wake-up function are selected using this
labeled I/O registers are mapped to specific addresses              resistor.
within the Data Memory as shown in the Data Memory
table, which are used to transfer the appropriate output            Pull-High Resistors - PAPU, PBPU, PCPU, PDPU
or input data on that port. With each I/O port there is an          All I/O pins on Ports PA, PB, PC and PD, if setup as in-
associated control register labeled PAC, PBC, PCC and               puts, can be connected to an internal pull-high resistor.
PDC, also mapped to specific addresses with the Data                The pins which require a pull-high resistor to be con-
Memory. The control register specifies which pins of that           nected are selected using these registers.
port are set as inputs and which are set as outputs. To
setup a pin as an input, the corresponding bit of the con-          Register - CLKMOD
trol register must be set high, for an output it must be set
                                                                    The device operates using a dual clock system whose
low. During program initialization, it is important to first
                                                                    mode is controlled using this register. The register con-
setup the control registers to specify which pins are out-
                                                                    trols functions such as the clock source, the idle mode
puts and which are inputs before reading data from or
                                                                    enable and the division ratio for the slow clock.
writing data to the I/O ports. One flexible feature of these
registers is the ability to directly program single bits us-
                                                                    OPA Control Registers - OPAC
ing the ²SET [m].i² and ²CLR [m].i² instructions. The
ability to change I/O pins from output to input and vice            The device contains an integrated OPA. The correct op-
versa by manipulating specific bits of the I/O control reg-         eration of the OPA requires the use of an OPA control
isters during normal program operation is a useful fea-             register. Functions such as the OPA enable/disable and
ture of these devices.                                              OPA input offset voltage cancellation control are deter-
                                                                    mined using the OPA control register, OPAC.
Pulse Width Modulator Registers
                                                                    Miscellaneous Register - MISC
The devices contain multiple Pulse Width Modulator out-
puts each with their own related independent control reg-           The miscellaneous register is used to control two func-
ister pair, known as PWM0L/PWM0H, PWM1L/PWM1H,                      tions. The four lower bits are used for the Watchdog
PWM2L/PWM2H and PWM3L/PWM3H. The 12-bit con-                        Timer control, while the highest four bits are used to se-
tents of each register pair, which defines the duty cycle           lect open drain outputs for pins PA0~PA3.
value for the modulation cycle of the Pulse Width Modula-
tor, along with an enable bit are contained in these regis-         Input/Output Ports
ter pairs.
                                                                    Holtek microcontrollers offer considerable flexibility on
A/D Converter Registers - ADRL, ADRH, ADCR0,                        their I/O ports. With the input or output designation of ev-
ADCR1, ADCR2, ANCSR0, ANCSR1, ANCSR2                                ery pin fully under user program control, pull-high selec-
                                                                    tions for all ports and wake-up selections on certain
The device contains a multiple channel 12-bit A/D con-
                                                                    pins, the user is provided with an I/O structure to meet
verter. The correct operation of the A/D requires the use
                                                                    the needs of a wide range of application possibilities.
of two data registers and six control registers. The two
data registers, a high byte data register known as                  The device provides 18 or 30 bidirectional input/output
ADRH, and a low byte data register known as ADRL, are               lines labeled with port names PA, PB, PC and PD.
the register locations where the digital value is placed            These I/O ports are mapped to the RAM Data Memory
after the completion of an analog to digital conversion             with specific addresses as shown in the Special Pur-
cycle. Functions such as the A/D enable/disable, A/D                pose Data Memory table. All of these I/O ports can be
channel selection and A/D clock frequency are deter-                used for input and output operations. For input opera-
mined using the six control registers, ADCR0, ADCR1,                tion, these ports are non-latching, which means the in-
ADCR2, ANCSR0, ANCSR1 and ANCSR2.                                   puts must be ready at the T2 rising edge of instruction
                                                                    ²MOV A,[m]², where m denotes the port address. For
Serial Interface Registers                                          output operation, all the data is latched and remains un-
The device contains two serial interfaces, an SPI and an            changed until the output latch is rewritten.
I2C interface. The SIMCTL0, SIMCTL1, SIMCTL2 and
SIMAR are the control registers for the Serial Interface
function while the SIMDR is the data register for the Se-
rial Interface Data.



Rev. 1.00                                                      19                                        September 21, 2010
                                                                                                                                                                                                        HT45R52/HT45R54

               b 7                                                                                                                                             b 0
            O D E 3     O D E 2       O D E 1         O D E 0    W D T E N 3          W D T E N 2                             W D T E N 1                  W D T E N 0            M IS C     R e g is te r

                                                                                                                                                                                  W a tc h d o g T im e r E n a b le C o n tr o l
                                                                                                                                                                                   - d e s c r ib e d e ls e w h e r e

                                                                                                                                                                                  P A 0 O p e n D r a in C o n tr o l
                                                                                                                                                                                   1 : e n a b le
                                                                                                                                                                                    0 : d is a b le

                                                                                                                                                                                  P A 1 O p e n D r a in C o n tr o l
                                                                                                                                                                                   1 : e n a b le
                                                                                                                                                                                    0 : d is a b le

                                                                                                                                                                                  P A 2 O p e n D r a in C o n tr o l
                                                                                                                                                                                   1 : e n a b le
                                                                                                                                                                                    0 : d is a b le

                                                                                                                                                                                  P A 3 O p e n D r a in C o n tr o l
                                                                                                                                                                                   1 : e n a b le
                                                                                                                                                                                    0 : d is a b le

                                                                 PA0~PA3 Open Drain Control - MISC


                                                                                                                                                                                                  V   D D
                                                                                                                                          P u ll- H ig h
                                                                                     C o n tr o l B it                                     O p tio n                                             W e a k
                                                        D a ta B u s                               D                      Q                                                                       P u ll- u p

                                 W r ite C o n tr o l R e g is te r                                    C K        Q

                                                      C h ip R e s e t                                        S

                                                                                                                                                                                                                 I/O   p in
                                 R e a d C o n tr o l R e g is te r
                                                                                           D a ta B it
                                                                                            D      Q

                                     W r ite D a ta R e g is te r                                  C K                Q
                                                                                                              S
                                                                                                                              M
                                                                                                                                  U
                                    R e a d D a ta R e g is te r                                                                      X


                                         S y s te m      W a k e -u p                                                                                                                      P A o n ly
                                                                                                                                                     W a k e - u p S e le c t

                                                                          Generic Input/Output Structure

                                                                                                                                                               V   D D

                                                                                                        P u ll- H ig h
                                                                                                         R e g is te r
                                                                  C o n tr o l B it                       S e le c t                                                     W e a k
                                     D a ta B u s                   D         Q                                                                                           P u ll- u p

             W r ite C o n tr o l R e g is te r                     C K          Q
                                                                            S
                                  C h ip R e s e t
                                                                                                                                                                                                                A /D   In p u t P o rt
             R e a d C o n tr o l R e g is te r
                                                                    D a ta B it
                                                                     D      Q

                 W r ite D a ta R e g is te r
                                                                    C K          Q
                                                                            S
                                                                                       M
                                                                                           U
                                                                                               X
                R e a d D a ta R e g is te r
                                                            A N C S R 0               A n a lo g
                                                             A N C S R 1                In p u t
                                                              A N C S R 2            S e le c to r
                      T o A /D      C o n v e rte r


                                                                                                        A N C S R 0 , A N C S R 1 , A N C S R 2
                                                                                A/D Input/Output Structure


Rev. 1.00                                                                                                                     20                                                                                              September 21, 2010
                                                                                                                          HT45R52/HT45R54

                              b 7                          b 0
                          P X P U 7        P X P U 1   P X P U 0   P A P U , P B P U , P C P U , P D P U        R e g is te r

                                                                   P A .0 , P B .0 , P C .0 P u ll- h ig h
                                                                    1 : e n a b le
                                                                     0 : d is a b le

                                                                   P A .1 , P B .1 , P C .1 P u ll- h ig h , P D .1 P u ll- h ig h
                                                                    1 : e n a b le
                                                                     0 : d is a b le



                                                                   P A .7 , P B .7 , P C .7 P u ll- h ig h , P D .5 P u ll- h ig h
                                                                    1 : e n a b le
                                                                     0 : d is a b le
                                Pull-High Resistor Register - PAPU, PBPU, PCPU, PDPU


Pull-high Resistors                                                           When the corresponding bit of the control register is
Many product applications require pull-high resistors for                     written as a ²0², the I/O pin will be setup as a CMOS out-
their switch inputs usually requiring the use of an exter-                    put. If the pin is currently setup as an output, instructions
nal resistor. To eliminate the need for these external re-                    can still be used to read the output register. However, it
sistors, all I/O pins, when configured as an input have                       should be noted that the program will in fact only read
the capability of being connected to an internal pull-high                    the status of the output data latch and not the actual
resistor. These pull-high resistors are selected using                        logic status of the output pin.
registers PAPU, PBPU, PCPU and PDPU and are im-
                                                                              Pin-shared Functions
plemented using weak PMOS transistors.
                                                                              The flexibility of the microcontroller range is greatly en-
Port A Wake-up                                                                hanced by the use of pins that have more than one func-
The HALT instruction forces the microcontroller into a                        tion. Limited numbers of pins can force serious design
Power Down condition which preserves power, a fea-                            constraints on designers but by supplying pins with
ture that is important for battery and other low-power ap-                    multi-functions, many of these difficulties can be over-
plications. Various methods exist to wake-up the                              come. For some pins, the chosen function of the
microcontroller, one of which is to change the logic                          multi-function I/O pins is set by configuration options
condition on one of the Port A pins from high to low. After                   while for others the function is set by application pro-
a HALT instruction forces the microcontroller into enter-                     gram control.
ing a Power Down condition, the processor will remain                         · External Interrupt Inputs
in a low-power state until the logic condition of the se-                        The external interrupt pins INT0, INT1 are pin-shared
lected wake-up pin on Port A changes from high to low.                           with the I/O pins PA0, PA1. For applications not requir-
This function is especially suitable for applications that                       ing an external interrupt input, the pin-shared external
can be woken up via external switches. Each pin on Port                          interrupt pin can be used as a normal I/O pin, however
A can be selected individually to have this wake-up fea-                         to do this, the external interrupt enable bits in the
ture using the PAWU register.                                                    INTC0 register must be disabled.
                                                                              · External Timer Clock Input
Port A Open Drain Function                                                       The external timer pins TMR0 and TMR1 are
All I/O pins in the device have CMOS structures, how-                            pin-shared with I/O pins. To configure them to operate
ever Port A pins PA0~PA3 can also be setup as open                               as timer inputs, the corresponding control bits in the
                                                                                 timer control register must be correctly set and the pin
drain structures. This is implemented using the ODE0~
                                                                                 must also be setup as an input. Note that the original
ODE3 bits in the MISC register.
                                                                                 I/O function will remain even if the pin is setup to be
                                                                                 used as an external timer input.
I/O Port Control Registers
                                                                              · PFD Output
Each I/O port has its own control register known as PAC,
                                                                                 The device contains a PFD function whose single out-
PBC, PCC and PDC, to control the input/output configu-
                                                                                 put is pin-shared with I/O pin PA3. The output function
ration. With this control register, each CMOS output or                          of this pin is chosen via a configuration option and re-
input with or without pull-high resistor structures can be                       mains fixed after the device is programmed. Note that
reconfigured dynamically under software control. Each                            the corresponding bit of the port control register,
pin of the I/O ports is directly mapped to a bit in its asso-                    PAC.3, must setup the pin as an output to enable the
ciated port control register. For the I/O pin to function as                     PFD output. If the PAC port control register has setup
an input, the corresponding bit of the control register                          the pin as an input, then the pin will function as a nor-
must be written as a ²1². This will then allow the logic                         mal logic input with the usual pull-high selection, even
state of the input pin to be directly read by instructions.                      if the PFD configuration option has been selected.


Rev. 1.00                                                             21                                                             September 21, 2010
                                                                                                                 HT45R52/HT45R54

· PWM Outputs                                                       Programming Considerations
  The device contains several PWM outputs shared
                                                                    Within the user program, one of the first things to con-
  with pins PA4, PA5, PB6 and PB7. The PWM output
                                                                    sider is port initialisation. After a reset, all of the I/O data
  functions are chosen via registers. Note that the corre-
  sponding bit of the port control register, PAC and PBC,           and port control registers will be set high. This means
  must setup the pin as an output to enable the PWM                 that all I/O pins will default to an input state, the level of
  output. If the PAC and PBC port control register has              which depends on the other connected circuitry and
  setup the pin as an input, then the pin will function as a        whether pull-high selections have been chosen. If the
  normal logic input with the usual pull-high selection,            port control registers, PAC, PBC, PCC and PDC, are
  even if the PWM registers have enabled the PWM                    then programmed to setup some pins as outputs, these
  function.                                                         output pins will have an initial high output value unless
· A/D Inputs                                                        the associated port data registers, PA, PB, PC and PD,
  The device contains a multi-channel A/D converter. All            are first programmed. Selecting which pins are inputs
  of these analog inputs are pin-shared with I/O pins on            and which are outputs can be achieved byte-wide by
  Port A, Port B and Port C. If these pins are to be used           loading the correct values into the appropriate port con-
  as A/D inputs and not as normal I/O pins then the corre-          trol register or by programming individual bits in the port
  sponding bits in the A/D Converter Analog Channel Se-             control register using the ²SET [m].i² and ²CLR [m].i² in-
  lect Registers, ANCSR0, ANCSR1 and ANCSR2, must
                                                                    structions. Note that when using these bit control in-
  be properly set. There are no configuration options as-
                                                                    structions, a read-modify-write operation takes place.
  sociated with the A/D function. If used as I/O pins, then
  full pull-high resistor register remain, however if used          The microcontroller must first read in the data on the en-
  as A/D inputs then any pull-high resistor selections as-          tire port, modify it to the required new bit values and then
  sociated with these pins will be automatically discon-            rewrite this data back to the output ports.
  nected.
                                                                                            T 1   T 2      T 3        T 4    T 1     T 2          T 3        T 4
· OPA Inputs/Output                                                 S y s te m   C lo c k

  The device contains an integrated OPA. The OPA in-
                                                                           P o rt D a ta
  puts and output are pin-shared with I/O pins on
  PD3~PD5. If these pins are to be used as OPA in-
                                                                                                        W r ite to P o r t                 R e a d fro m   P o rt
  puts/output and not as normal I/O pins then the corre-
  sponding bits in the ADCR1 Register, must be                                                    Read/Write Timing
  properly set. There are no configuration options asso-
  ciated with the OPA function. If these shared pins are
                                                                    Port A has the additional capability of providing wake-up
  used as OPA inputs then any pull-high resistor selec-
  tions associated with these pins will be automatically            functions. When the device is in the Power Down Mode,
  disconnected.                                                     various methods are available to wake the device up.
                                                                    One of these is a high to low transition of any of the Port
I/O Pin Structures                                                  A pins. Single or multiple pins on Port A can be setup to
                                                                    have this function.
The accompanying diagrams illustrate the internal
structures of some I/O pin types. As the exact logical
construction of the I/O pin will differ from these draw-
ings, they are supplied as a guide only to assist with the
functional understanding of the I/O pins. The wide range
of pin-shared structures does not permit all types to be
shown.




Rev. 1.00                                                      22                                                                  September 21, 2010
                                                                                               HT45R52/HT45R54

Timer/Event Counters
The provision of timers form an important part of any               Timer Registers - TMR0, TMR1L/TMR1H
microcontroller, giving the designer a means of carrying
                                                                    The timer registers are special function registers located
out time related functions. The devices contain one 8-bit
                                                                    in the Special Purpose Data Memory and is the place
and 16-bit count-up timers. As each timer has three dif-
                                                                    where the actual timer value is stored. For the 8-bit
ferent operating modes, they can be configured to oper-
                                                                    Timer/Event Counters, these registers are known as
ate as a general timer, an external event counter or as a
                                                                    TMR0. For the 16-bit Timer/Event Counter, a pair of reg-
pulse width measurement device. The provision of a
                                                                    isters are required and are known as TMR1L/TMR1H.
prescaler to the clock circuitry of the 8-bit Timer/Event
                                                                    The value in the timer registers increases by one each
Counter also gives added range to this timer.
                                                                    time an internal clock pulse is received or an external
There are two types of registers related to the                     transition occurs on the external timer pin. The timer will
Timer/Event Counters. The first are the registers that              count from the initial value loaded by the preload regis-
contain the actual value of the Timer/Event Counter and             ter to the full count of FFH for the 8-bit timer or FFFFH
into which an initial value can be preloaded. Reading               for the 16-bit timer at which point the timer overflows and
from these registers retrieves the contents of the                  an internal interrupt signal is generated. The timer value
Timer/Event Counter. The second type of associated                  will then be reset with the initial preload register value
register is the Timer Control Register which defines the            and continue counting.
timer options and determines how the Timer/Event
                                                                    To achieve a maximum full range count of FFH for the
Counter is to be used. The Timer/Event Counters can
                                                                    8-bit timer or FFFFH for the 16-bit timer, the preload reg-
have the their clock configured to come from an internal
                                                                    isters must first be cleared to all zeros. It should be
clock source or from an external timer pin.
                                                                    noted that after power-on, the preload register will be in
          Device              HT45R52         HT45R54               an unknown condition. Note that if the Timer/Event
                                                                    Counter is switched off and data is written to its preload
 No. of 8-bit Timers               1               1
                                                                    registers, this data will be immediately written into the
                             Timer/Event     Timer/Event            actual timer registers. However, if the Timer/Event
 Timer Name
                              Counter 0       Counter 0
                                                                    Counter is enabled and counting, any new data written
 Timer Register Name            TMR0            TMR0                into the preload data registers during this period will re-
 Control Register Name         TMR0C           TMR0C                main in the preload registers and will only be written into
                                                                    the timer registers the next time an overflow occurs.
 No. of 16-bit Timers              0               1
                                                                    For the 16-bit Timer/Event Counter which has both low
                                             Timer/Event
 Timer Name                       ¾                                 byte and high byte timer registers, accessing these reg-
                                              Counter 1
                                                                    isters is carried out in a specific way. It must be noted
                                               TMR1L/
 Timer Register Name              ¾                                 when using instructions to preload data into the low byte
                                               TMR1H
                                                                    timer register, the data will only be placed in a low byte
 Control Register Name            ¾            TMR1C                buffer and not directly into the low byte timer register.
                                                                    The actual transfer of the data into the low byte timer
Configuring the Timer/Event Counter Input Clock                     register is only carried out when a write to its associated
Source                                                              high byte timer register, namely TMR1H, is executed.
                                                                    However, using instructions to preload data into the high
The internal timer¢s clock can originate from various
                                                                    byte timer register will result in the data being directly
sources. The system clock source is used when the
                                                                    written to the high byte timer register. At the same time
Timer/Event Counter is in the timer mode or in the pulse
                                                                    the data in the low byte buffer will be transferred into its
width measurement mode. For the 8-bit Timer/Event
                                                                    associated low byte timer register. For this reason, the
Counter this internal clock source is fSYS which is also di-
                                                                    low byte timer register should be written first when
vided by a prescaler, the division ratio of which is condi-
                                                                    preloading data into the 16-bit timer registers. It must
tioned by the Timer Control Register, TMR0C, bits
                                                                    also be noted that to read the contents of the low byte
T0PSC0~ T0PSC2. For the 16-bit Timer/Event Counter
                                                                    timer register, a read to the high byte timer register must
this internal clock source can be chosen from a combi-
                                                                    be executed first to latch the contents of the low byte
nation of internal clocks using a configuration option and
                                                                    timer register into its associated low byte buffer. After
the T1S bit in the TMR1C register.
                                                                    this has been done, the low byte timer register can be
An external clock source is used when the timer is in the           read in the normal way. Note that reading the low byte
event counting mode, the clock source being provided on             timer register will result in reading the previously latched
an external timer pin TMR0 or TMR1 depending upon                   contents of the low byte buffer and not the actual con-
which timer is used. Depending upon the condition of the            tents of the low byte timer register.
TnE bit, each high to low, or low to high transition on the
external timer pin will increment the counter by one.


Rev. 1.00                                                      23                                        September 21, 2010
                                                                                                                                                                                                                     HT45R52/HT45R54

                                                                                                                                                                                                                                    D a ta B u s


                                                                                                                       T 0 M 1       T 0 M 0                                                                                         R e lo a d
                                           T 0 P S C 2 ~ T 0 P S C 0                                                                                                                   P r e lo a d R e g is te r
                                                                  (1 /1 ~ 1 /1 2 8 )
                       fS       Y S                 7 - s ta g e P r e s c a le r                             T im e r /E v e n t C o u n te r
                                                                                                                   M o d e C o n tro l
                                                                                                                                                                                            T im e r /E v e n t                                         O v e r flo w
             T M R 0                                   F ilte r                                                                                                                                 C o u n te r                                             to In te rru p t
                F ilte r O n /O ff                                        T 0 E                                                                                              8 - b it T im e r /E v e n t C o u n te r                 ¸ 2                        P F D 0
                 C o n fig u r a tio n o p tio n                                                                                                      T 0 O N

                                                                                                         8-bit Timer/Event Counter Structure

                                                                                                                                                                                                                                                   D a ta B u s

                                                                                                                                                                                                            L o w B y te
                                                                                                                                                                                                               B u ffe r
                                               fS    Y S   /4                     M
                                                                                      U                             T 1 M 1           T 1 M 0
                            L IR C       O s c illa to r                                  X                                                                                                       1 6 - B it                                  R e lo a d
                                                                                                                                                                                        P r e lo a d R e g is te r
                                                     T 1 S                                                    T im e r /E v e n t C o u n te r
             C o n fig u r a tio n                                                                                 M o d e C o n tro l
                  O p tio n
                                                                                                                                                                                    H ig h B y te             L o w B y te                                 O v e r flo w
   T M R 1                                      F ilte r
                                                                                                                                                                                                                                                            to In te rru p t
                                                                                                                                                                              1 6 - b it T im e r /E v e n t C o u n te r
             F ilte r O n /O ff                                     T 1 E                                                                             T 1 O N
              C o n fig u r a tio n o p tio n                                                                                                                                                                                                ¸ 2                     P F D 1

                                                                                                        16-bit Timer/Event Counter Structure


 P F D 0                    M
                                U             P F D
 P F D 1                            X

             C o n fig u r a tio n
                  O p tio n

                                        PFD Clock Source

                  b 7                                                                                                                          b 0
               T 0 M 1 T 0 M 0                                  T 0 O N                       T 0 E   T 0 P S C 2      T 0 P S C 1      T 0 P S C 0       T M R 0 C            R e g is te r

                                                                                                                                                           T im e r p r e s c a le r r a te s e le                   c t            D iv is io n R a tio
                                                                                                                                                          T 0 P S C 2 T 0 P S C 1                 T 0 P               S C 0           T im e r R a te
                                                                                                                                                                0                 0                              0                             1 :1
                                                                                                                                                                  0                 0                            1                              1 :2
                                                                                                                                                                    0                 1                          0                               1 :4
                                                                                                                                                                      0                 1                        1                                1 :8
                                                                                                                                                                        1                 0                      0                          1 :1 6
                                                                                                                                                                          1                 0                    1                           1 :3 2
                                                                                                                                                                            1                 1                  0                            1 :6 4
                                                                                                                                                                              1                 1                1                         1 :1 2 8
                                                                                                                                                          E v e n t C            o u n te r a c tiv e e d g          e s e le c t
                                                                                                                                                           1 : c o u n       t o n fa llin g e d g e
                                                                                                                                                            0 : c o u n       t o n r is in g e d g e
                                                                                                                                                             P u ls e W           id th M e a s u r e m e n            t a c tiv e e d g e s e le c t
                                                                                                                                                              1 : s ta rt      c o u n tin g o n r is in g            e d g e , s to p o n fa llin g e d g e
                                                                                                                                                               0 : s ta rt      c o u n tin g o n fa llin g             e d g e , s to p o n r is in g e d g e
                                                                                                                                                          T im e r /E v e n t C o u n te r c o u n tin g e n a b le
                                                                                                                                                           1 : e n a b le
                                                                                                                                                            0 : d is a b le
                                                                                                                                                          N o t im p le m e n te d , r e a d a s " 0 "

                                                                                                                                                           O p e r a tin        g m o d e        s e le c t
                                                                                                                                                          T 0 M 1 T            0 M 0
                                                                                                                                                              0                  0       n o        m o d     e a v a ila b le
                                                                                                                                                                0                  1      e v    e n t c    o u n te r m o d e
                                                                                                                                                                  1                  0     tim     e r m     o d e
                                                                                                                                                                    1                  1   p u    ls e w       id th m e a s u r e m e n t m o d e
                                                                                               Timer/Event Counter Control Register - TMR0C


Rev. 1.00                                                                                                                                      24                                                                                        September 21, 2010
                                                                                                                                                               HT45R52/HT45R54

                     b 7                                                                b 0
                  T 1 M 1      T 1 M 0   T 1 S        T 1 O N   T 1 E                            T M R 1 C                  R e g is te r


                                                                                                 N o t im p le m e n te d , r e a d a s " 0 "

                                                                                                   E v          e n t C       o u n     te r a c tiv e e d g   e s e le c t
                                                                                                    1 :       c o u n     t o n        fa llin g e d g e
                                                                                                     0 :       c o u n     t o n       r is in g e d g e
                                                                                                 P u             ls e W        id th      M e a s u re m e n     t a c tiv e e d g e s e le c t
                                                                                                  1 :       s ta rt          c o u n     tin g o n r is in g    e d g e , s to p o n fa llin g e d g e
                                                                                                      0 :    s ta rt        c o u n      tin g o n fa llin g      e d g e , s to p o n r is in g e d g e

                                                                                                 T im e r /E v e n t C o u n te r c o u n tin g e n a b le
                                                                                                  1 : e n a b le
                                                                                                   0 : d is a b le

                                                                                                 T im e r c lo c k s o u r c e
                                                                                                  1 : L IR C o s c illa to r
                                                                                                   0 : fS Y S /4
                                                                                                 O p e r a tin g m o d e                       s e le c t
                                                                                                  T 1 M 1 T 1 M 0
                                                                                                      0         0       n o                      m o d     e a v a ila b le
                                                                                                        0         1      e v                  e n t c    o u n te r m o d e
                                                                                                          1         0     tim                   e r m     o d e
                                                                                                            1         1   p u                  ls e w       id th m e a s u r e m e n t m o d e
                                                            Timer/Event Counter Control Register - TMR1C

Timer Control Registers - TMR0C, TMR1C                                                        TnE. An additional TnS bit in the 16-bit Timer/Event
The flexible features of the Holtek microcontroller                                           Counter control register is used to determine the clock
Timer/Event Counters enable them to operate in three                                          source for the Timer/Event Counter.
different modes, the options of which are determined by
                                                                                              Configuring the Timer Mode
the contents of their respective control register.
                                                                                              In this mode, the Timer/Event Counter can be utilised to
It is the Timer Control Register together with its corre-
                                                                                              measure fixed time intervals, providing an internal inter-
sponding timer registers that control the full operation of
                                                                                              rupt signal each time the Timer/Event Counter over-
the Timer/Event Counters. Before the Timer/Event
                                                                                              flows. To operate in this mode, the Operating Mode
Counters can be used, it is essential that the appropriate
                                                                                              Select bit pair, TnM1/TnM0, in the Timer Control Regis-
Timer Control Register is fully programmed with the
                                                                                              ter must be set to the correct value as shown.
right data to ensure its correct operation, a process that
is normally carried out during program initialisation.                                        Control Register Operating Mode                                                                     Bit7 Bit6
                                                                                              Select Bits for the Timer Mode                                                                        1          0
To choose which of the three modes the timer is to oper-
ate in, either in the timer mode, the event counting mode                                     In this mode the internal clock, fSYS , is used as the inter-
or the pulse width measurement mode, bits 7 and 6 of                                          nal clock for 8-bit Timer/Event Counter 0 and the LIRC
the corresponding Timer Control Register, which are                                           or f SYS /4 is used as the internal clock for 16-bit
known as the bit pair TnM1/TnM0, must be set to the re-                                       Timer/Event Counter 1. However, the clock source, fSYS,
quired logic levels. The timer-on bit, which is bit 4 of the                                  for the 8-bit timer is further divided by a prescaler, the
Timer Control Register and known as TnON, depending                                           value of which is determined by the Prescaler Rate Se-
upon which timer is used, provides the basic on/off con-                                      lect bits T0PSC2~T0PSC0, which are bits 2~0 in the
trol of the respective timer. Setting the bit high allows the                                 Timer Control Register. After the other bits in the Timer
counter to run, clearing the bit stops the counter. For tim-                                  Control Register have been setup, the enable bit TnON,
ers that have prescalers, bits 0~2 of the Timer Control                                       which is bit 4 of the Timer Control Register, can be set
Register determine the division ratio of the input clock                                      high to enable the Timer/Event Counter to run. Each
prescaler. The prescaler bit settings have no effect if an                                    time an internal clock cycle occurs, the Timer/Event
external clock source is used. If the timer is in the event                                   Counter increments by one. When it is full and over-
count or pulse width measurement mode, the active                                             flows, an interrupt signal is generated and the
transition edge level type is selected by the logic level of                                  Timer/Event Counter will reload the value already
bit 3 of the Timer Control Register which is known as                                         loaded into the preload register and continue counting.
 P r e s c a le r O u tp u t



           In c re m e n t
                                                 T im e r + 1            T im e r + 2                                                                             T im e r + N                    T im e r + N + 1
  T im e r C o n tr o lle r

                                                                        Timer Mode Timing Chart


Rev. 1.00                                                                               25                                                                                       September 21, 2010
                                                                                                                     HT45R52/HT45R54

The interrupt can be disabled by ensuring that the                                 Timer Control Register place the Timer/Event Counter
Timer/Event Counter Interrupt Enable bit in the                                    in the Event Counting Mode, the second is to ensure
corresponding Interrupt Control Register, is reset to                              that the port control register configures the pin as an in-
zero.                                                                              put. It should be noted that in the event counting mode,
                                                                                   even if the microcontroller is in the Power Down Mode,
Configuring the Event Counter Mode                                                 the Timer/Event Counter will continue to record exter-
In this mode, a number of externally changing logic                                nally changing logic events on the timer input pin. As a
events, occurring on the external timer pin, can be re-                            result when the timer overflows it will generate a timer
corded by the Timer/Event Counter. To operate in this                              interrupt and corresponding wake-up source.
mode, the Operating Mode Select bit pair, TnM1/TnM0,
                                                                                   Configuring the Pulse Width Measurement Mode
in the Timer Control Register must be set to the correct
value as shown.                                                                    In this mode, the Timer/Event Counter can be utilised to
                                                                                   measure the width of external pulses applied to the ex-
Control Register Operating Mode                                 Bit7 Bit6
                                                                                   ternal timer pin. To operate in this mode, the Operating
Select Bits for the Event Counter Mode                           0    1
                                                                                   Mode Select bit pair, TnM1/TnM0, in the Timer Control
In this mode, the external timer pin, is used as the                               Register must be set to the correct value as shown.
Timer/Event Counter clock source, however it is not di-                            Control Register Operating Mode                    Bit7 Bit6
vided by the internal prescaler. After the other bits in the                       Select Bits for the Pulse Width
Timer Control Register have been setup, the enable bit                             Measurement Mode                                      1       1
TnON, which is bit 4 of the Timer Control Register, can
                                                                                   In this mode the internal clock, fSYS, is used as the inter-
be set high to enable the Timer/Event Counter to run. If
                                                                                   nal clock for the 8-bit Timer/Event Counter and LIRC or
the Active Edge Select bit, TnE, which is bit 3 of the
                                                                                   fSYS/4 is used as the internal clock for the 16-bit
Timer Control Register, is low, the Timer/Event Counter
                                                                                   Timer/Event Counter. However, the clock source, fSYS,
will increment each time the external timer pin receives
                                                                                   for the 8-bit timer is further divided by a prescaler, the
a low to high transition. If the Active Edge Select bit is
                                                                                   value of which is determined by the Prescaler Rate Se-
high, the counter will increment each time the external
                                                                                   lect bits T0PSC2~T0PSC0, which are bits 2~0 in the
timer pin receives a high to low transition. When it is full
                                                                                   Timer Control Register. After the other bits in the Timer
and overflows, an interrupt signal is generated and the
                                                                                   Control Register have been setup, the enable bit TnON,
Timer/Event Counter will reload the value already
                                                                                   which is bit 4 of the Timer Control Register, can be set
loaded into the preload register and continue counting.
                                                                                   high to enable the Timer/Event Counter, however it will
The interrupt can be disabled by ensuring that the
                                                                                   not actually start counting until an active edge is re-
Timer/Event Counter Interrupt Enable bit in the
                                                                                   ceived on the external timer pin.
corresponding Interrupt Control Register, is reset to
zero.                                                                              If the Active Edge Select bit TnE, which is bit 3 of the
                                                                                   Timer Control Register, is low, once a high to low transi-
As the external timer pin is shared with an I/O pin, to en-
                                                                                   tion has been received on the external timer pin, the
sure that the pin is configured to operate as an event
                                                                                   Timer/Event Counter will start counting until the external
counter input pin, two things have to happen. The first is
                                                                                   timer pin returns to its original high level. At this point the
to ensure that the Operating Mode Select bits in the


 E x te rn a l E v e n t


       In c re m e n t
 T im e r C o u n te r                T im e r + 1                                        T im e r + 2                            T im e r + 3


                                                          Event Counter Mode Timing Chart

              E x te rn a l T M R
                     P in In p u t

   T n O N      - w ith T n E = 0


        P r e s c a le r O u tp u t

                   In c re m e n t
                                                     T im e r                + 1        + 2              + 3   + 4
             T im e r C o u n te r

                                                     Pulse Width Measure Mode Timing Chart


Rev. 1.00                                                                   26                                            September 21, 2010
                                                                                                HT45R52/HT45R54

enable bit will be automatically reset to zero and the              Programmable Frequency Divider - PFD
Timer/Event Counter will stop counting. If the Active               The Programmable Frequency Divider provides a
Edge Select bit is high, the Timer/Event Counter will be-           means of producing a variable frequency output suitable
gin counting once a low to high transition has been re-             for applications requiring a precise frequency generator.
ceived on the external timer pin and stop counting when
the external timer pin returns to its original low level. As        The PFD output is pin-shared with the I/O pin PA3. The
before, the enable bit will be automatically reset to zero          PFD function is selected via configuration option, how-
and the Timer/Event Counter will stop counting. It is im-           ever, if not selected, the pin can operate as a normal I/O
portant to note that in the Pulse Width Measurement                 pin.
Mode, the enable bit is automatically reset to zero when            For the HT45R54, the clock source for the PFD circuit
the external control signal on the external timer pin re-           can originate from either Timer/Event Counter 0 or
turns to its original level, whereas in the other two               Timer/Event Counter 1 overflow signal selected via con-
modes the enable bit can only be reset to zero under                figuration option. The output frequency is controlled by
program control.                                                    loading the required values into the timer registers and
The residual value in the Timer/Event Counter, which                prescaler registers to give the required division ratio.
can now be read by the program, therefore represents                The timer will begin to count-up from this preload regis-
the length of the pulse received on the external timer              ter value until full, at which point an overflow signal is
pin. As the enable bit has now been reset, any further              generated, causing the PFD output to change state. The
transitions on the external timer pin will be ignored. Not          timer will then be automatically reloaded with the
until the enable bit is again set high by the program can           preload register value and continue counting-up.
the timer begin further pulse width measurements. In                For the PFD output to function, it is essential that the corre-
this way, single shot pulse measurements can be easily              sponding bit of the Port A control register PAC bit 3 is setup
Made.                                                               as an output. If setup as an input the PFD output will not
It should be noted that in this mode the Timer/Event                function, however, the pin can still be used as a normal in-
Counter is controlled by logical transitions on the exter-          put pin. The PFD output will only be activated if bit PA3 is
nal timer pin and not by the logic level. When the                  set to ²1². This output data bit is used as the on/off control
Timer/Event Counter is full and overflows, an interrupt             bit for the PFD output. Note that the PFD output will be low
signal is generated and the Timer/Event Counter will re-            if the PA3 output data bit is cleared to ²0².
load the value already loaded into the preload register             Using this method of frequency generation, and if a
and continue counting. The interrupt can be disabled by             crystal oscillator is used for the system clock, very pre-
ensuring that the Timer/Event Counter Interrupt Enable              cise values of frequency can be generated.
bit in the corresponding Interrupt Control Register, is re-
set to zero.                                                        Prescaler
As the external timer pin is shared with an I/O pin, to en-         Bits T0PSC0~T0PSC2 of the control register can be
sure that the pin is configured to operate as a pulse               used to define the pre-scaling stages of the internal
width measurement pin, two things have to happen. The               clock source of the Timer/Event Counter. The
first is to ensure that the Operating Mode Select bits in           Timer/Event Counter overflow signal can be used to
the Timer Control Register place the Timer/Event Coun-              generate signals for the PFD and Timer Interrupt.
ter in the Pulse Width Measurement Mode, the second
is to ensure that the port control register configures the
pin as an input.




                T im e r O v e r flo w


                       P F D   C lo c k


                         P A 3 D a ta



        P F D    O u tp u t a t P A 3

                                                   PFD Output Control




Rev. 1.00                                                      27                                          September 21, 2010
                                                                                                 HT45R52/HT45R54

I/O Interfacing                                                      small differences in measured values requiring program-
The Timer/Event Counter, when configured to run in the               mers to take this into account during programming. The
event counter or pulse width measurement mode, re-                   same applies if the timer is configured to be in the event
quire the use of external pins for correct operation. As             counting mode, which again is an external event and not
these pins are shared pins they must be configured cor-              synchronised with the internal system or timer clock.
rectly to ensure they are setup for use as Timer/Event               When the Timer/Event Counter is read, or if data is writ-
Counter inputs and not as a normal I/O pins. This is im-             ten to the preload register, the clock is inhibited to avoid
plemented by ensuring that the mode select bits in the               errors, however as this may result in a counting error, this
Timer/Event Counter control register, select either the              should be taken into account by the programmer. Care
event counter or pulse width measurement mode. Addi-                 must be taken to ensure that the timers are properly in-
tionally the Port Control Register must be set high to en-           itialised before using them for the first time. The associ-
sure that the pin is setup as an input. Any pull-high                ated timer enable bits in the interrupt control register must
resistor on these pins will remain valid even if the pin is          be properly set otherwise the internal interrupt associated
used as a Timer/Event Counter input.                                 with the timer will remain inactive. The edge select, timer
                                                                     mode and clock source control bits in timer control regis-
Timer/Event Counter Pins Internal Filter                             ter must also be correctly set to ensure the timer is prop-
The external Timer/Event Counter pins are connected to               erly configured for the required application. It is also
an internal filter to reduce the possibility of unwanted             important to ensure that an initial value is first loaded into
event counting events or inaccurate pulse width mea-                 the timer registers before the timer is switched on; this is
surements due to adverse noise or spikes on the exter-               because after power-on the initial values of the timer reg-
nal Timer/Event Counter input signal. As this internal               isters are unknown. After the timer has been initialised
filter circuit will consume a limited amount of power, a             the timer can be turned on and off by controlling the en-
configuration option is provided to switch off the filter            able bit in the timer control register. Note that setting the
function, an option which may be beneficial in power                 timer enable bit high to turn the timer on, should only be
sensitive applications, but in which the integrity of the in-        executed after the timer mode bits have been properly
put signal is high. Care must be taken when using the fil-           setup. Setting the timer enable bit high together with a
ter on/off configuration option as it will be applied not            mode bit modification, may lead to improper timer oper-
only to both external Timer/Event Counter pins but also              ation if executed as a single timer control register byte
to the external interrupt input pins. Individual                     write instruction.
Timer/Event Counter or external interrupt pins cannot                When the Timer/Event counter overflows, its corre-
be selected to have a filter on/off function.                        sponding interrupt request flag in the interrupt control
                                                                     register will be set. If the timer interrupt is enabled this
Programming Considerations                                           will in turn generate an interrupt signal. However irre-
When configured to run in the timer mode, the internal               spective of whether the interrupts are enabled or not, a
system clock is used as the timer clock source and is                Timer/Event counter overflow will also generate a
therefore synchronised with the overall operation of the             wake-up signal if the device is in a Power-down condi-
microcontroller. In this mode when the appropriate timer             tion. This situation may occur if the Timer/Event Counter
register is full, the microcontroller will generate an inter-        is in the Event Counting Mode and if the external signal
nal interrupt signal directing the program flow to the re-           continues to change state. In such a case, the
spective internal interrupt vector. For the pulse width              Timer/Event Counter will continue to count these exter-
measurement mode, the internal system clock is also                  nal events and if an overflow occurs the device will be
used as the timer clock source but the timer will only run           woken up from its Power-down condition. To prevent
when the correct logic condition appears on the external             such a wake-up from occurring, the timer interrupt re-
timer input pin. As this is an external event and not syn-           quest flag should first be set high before issuing the
chronized with the internal timer clock, the                         HALT instruction to enter the Power Down Mode.
microcontroller will only see this external event when the
next timer clock pulse arrives. As a result, there may be




Rev. 1.00                                                       28                                         September 21, 2010
                                                                                      HT45R52/HT45R54

Timer Program Example
This program example shows how the Timer/Event Counter registers are setup, along with how the interrupts are en-
abled and managed. Note how the Timer/Event Counter is turned on, by setting bit 4 of the Timer Control Register. The
Timer/Event Counter can be turned off in a similar way by clearing the same bit. This example program sets the
Timer/Event Counter to be in the timer mode, which uses the internal system clock as the clock source.


org 04h             ; external interrupt vector
reti
org 08h
reti
org 0CH             ; Timer/Event Counter 0 interrupt vector
jmp tmrint          ; jump here when the Timer/Event Counter 0 overflows
:
org 20h             ; main program
;internal Timer/Event Counter 0 interrupt routine
tmrint:
:
; Timer/Event Counter 0 main program placed here
:
reti
:
:

begin:
;setup Timer 0 registers
mov a,09bh           ; setup Timer 0 preload value
mov tmr0,a;
mov a,081h           ; setup Timer 0 control register
mov tmr0c,a          ; timer mode and prescaler set to /2
; setup interrupt register
mov a,009h           ; enable master interrupt and timer interrupt
mov int0,a
set tmr0c.4          ; start Timer/Event Counter 0 - note mode bits must be previously setup




Rev. 1.00                                                29                                     September 21, 2010
                                                                                             HT45R52/HT45R54

Pulse Width Modulator
The devices contains a series of Pulse Width Modula-              periods. However, in the 8+4 PWM mode, each PWM cy-
tion, PWM, outputs. Useful for such applications such as          cle is subdivided into sixteen individual sub-cycles known
motor speed control, the PWM function provides an out-            as modulation cycle 0 ~ modulation cycle 15, denoted as
put with a fixed frequency but with a duty cycle that can         ²i² in the table. Each one of these sixteen sub-cycles con-
be varied by setting particular values into the corre-            tains 256 clock cycles. In this mode, a modulation fre-
sponding PWM register.                                            quency increase of sixteen is achieved. The 12-bit PWM
                                                                  register value, which represents the overall duty cycle of
                        PWM     Output       Register
 Part No.   Channels                                              the PWM waveform, is divided into two groups. The first
                        Mode     Pins         Names
                                                                  group which consists of bit4~bit11 is denoted here as the
                                    PA4   PWM0H/PWM0L             DC value. The second group which consists of bit0~bit3
 HT45R52        2        8+4
                                    PA5   PWM1H/PWM1L             is known as the AC value. In the 8+4 PWM mode, the
                                    PA4                           duty cycle value of each of the two modulation sub-cycles
                                    PA5   PWM2H/PWM2L             is shown in the following table.
 HT45R54        4        8+4
                                    PB6   PWM3H/PWM3L
                                    PB7
                                                                        Parameter          AC (0~15)     DC (Duty Cycle)
                                                                                                                DC+1
                                                                                              i<AC
                                                                    Modulation cycle i                           256
PWM Overview
                                                                       (i=0~15)                                  DC
A register pair, located in the Data Memory is assigned                                       i³AC
                                                                                                                 256
to each Pulse Width Modulator output and are known as
the PWM registers. It is in each register pair that the                    8+4 Mode Modulation Cycle Values
12-bit value, which represents the overall duty cycle of
one modulation cycle of the output waveform, should be            The accompanying diagram illustrates the waveforms
placed. The PWM registers also contain the enable/dis-            associated with the 8+4 mode of PWM operation. It is
                                                                  important to note how the single PWM cycle is subdi-
able control bit for the PWM outputs. To increase the
                                                                  vided into 16 individual modulation cycles, numbered
PWM modulation frequency, each modulation cycle is
                                                                  0~15 and how the AC value is related to the PWM value.
modulated into sixteen individual modulation
sub-sections, known as the 8+4 mode. Note that it is              PWM Output Control
only necessary to write the required modulation value
                                                                  The four PWM0~PWM3 outputs are shared with pins
into the corresponding PWM register as the subdivision
                                                                  PA4~PA5, PB6~PB7. To operate as a PWM output and
of the waveform into its sub-modulation cycles is imple-
                                                                  not as an I/O pin, bit 0 of the relevant PWM register bit
mented automatically within the microcontroller hard-
                                                                  must be set high. A zero must also be written to the cor-
ware. The PWM clock source is the system clock fSYS.
                                                                  responding bit in the PAC and PBC port control register,
This method of dividing the original modulation cycle             to ensure that the PWM output pin is setup as an output.
into a further 16 sub-cycles enables the generation of            After these two initial steps have been carried out, and
higher PWM frequencies, which allow a wider range of              of course after the required PWM 12-bit value has been
applications to be served. As long as the periods of the          written into the PWM register pair register, writing a ²1²
generated PWM pulses are less than the time constants             to the corresponding PA and PB data register will enable
of the load, the PWM output will be suitable as such long
                                                                  the PWM data to appear on the pin. Writing a ²0² to the
time constant loads will average out the pulses of the
                                                                  bit will disable the PWM output function and force the
PWM output. The difference between what is known as
                                                                  output low. In this way, the Port A and Port B data output
the PWM cycle frequency and the PWM modulation fre-
                                                                  register bits, can also be used as an on/off control for the
quency should be understood. As the PWM clock is the
                                                                  PWM function. Note that if the enable bit in the PWM
system clock, fSYS, and as the PWM value is 12-bits
                                                                  register is set high to enable the PWM function, but a
wide, the overall PWM cycle frequency is fSYS/4096.
                                                                  ²1² has been written to its corresponding bit in the PAC
However, when in the 8+4 mode of operation, the PWM
                                                                  and PBC control register to configure the pin as an input,
modulation frequency will be fSYS/256.
                                                                  then the pin can still function as a normal input line, with
      PWM                                                         pull-high resistor selections.
                       PWM Cycle           PWM Cycle
   Modulation
                       Frequency             Duty
   Frequency
                                          (PWM register
     fSYS/256           fSYS/4096
                                           value)/4096

8+4 PWM Mode Modulation
Each full PWM cycle, as it is 12-bits wide, has 4096 clock

Rev. 1.00                                                    30                                        September 21, 2010
                                                                                                                                                                                                   HT45R52/HT45R54

PWM Programming Example
The following sample program shows how the PWM output is setup and controlled.
mov               a,64h                            ;   setup PWM0 value to 1600 decimal which is 640H
mov               pwm0h,a                          ;   setup PWM0H register value
clr               pwm0l                            ;   setup PWM0L register value
clr               pac.4                            ;   setup pin PA4 as an output
set               pwm0en                           ;   set the PWM0 enable bit
set               pa.4                             ;   Enable the PWM0 output
 :                 :
 :                 :
clr               pa.4                             ; PWM0 output disabled - PA4 will remain low




fS   Y S   /2

[P W M ] = 1 6 0 0

P W M
                              1 0 0 /2 5 6                                          1 0 0 /2 5 6                                1 0 0 /2 5 6                                 1 0 0 /2 5 6                              1 0 0 /2 5 6
[P W M ] = 1 6 0 1

P W M
                              1 0 1 /2 5 6                                          1 0 0 /2 5 6                                1 0 0 /2 5 6                                 1 0 0 /2 5 6                              1 0 1 /2 5 6
[P W M ] = 1 6 0 2

P W M
                              1 0 1 /2 5 6                                          1 0 1 /2 5 6                                1 0 0 /2 5 6                                 1 0 0 /2 5 6                              1 0 1 /2 5 6



[P W M ] = 1 6 1 5

P W M
                                1 0 1 /2 5 6                                        1 0 1 /2 5 6                                          1 0 1 /2 5 6                       1 0 0 /2 5 6                              1 0 1 /2 5 6

                   P W M     m o d u la tio n p e r io d : 2 5 6 /fS   Y S
                           M o d u la tio n c y c le 0                       M o d u la tio n c y c le 1                   M o d u la tio n c y c le 2                    M o d u la tio n c y c le 1 5             M o d u la tio n c y c le 0

                                                                                                   P W M   c y c le : 4 0 9 6 /fS   Y S



                                                                                                                  8+4 PWM Mode




                                  P W M 0 H ~ P W M 3 H                                                                                      P W M 0 L ~ P W M 3 L
                                H ig h B y te R e g is te r s                                                                              L o w B y te R e g is te r s

            b 7                                                                              b 0                b 7                                                                          b 0
           1 1       1 0          9            8        7        6              5             4                  3          2               1            0                                  E N    P W M    R e g is te r s

                                                                                                                                                                                                   P W M O n /O ff C o n tro l
                                                                                                                                                                                                    1 : P W M e n a b le
                                                                                                                                                                                                     0 : I/O p in e n a b le

                                                                                                                                                                                                   N o t im p le m e n te d , r e a d a s " 0 "

                                                                                                                                                                                                   P W M A C      V a lu e
                                                                                                                                                                                                    b its 0 ~ 3

                                                                                                                                                                                                   P W M D C V a lu e
                                                                                                                                                                                                    b its 4 ~ 1 1

                                                                                                            PWM Register Pairs




Rev. 1.00                                                                                                                           31                                                                            September 21, 2010
                                                                                                                                            HT45R52/HT45R54

Analog to Digital Converter
The need to interface to real world analog signals is a                                       The accompanying block diagram shows the overall in-
common requirement for many electronic systems.                                               ternal structure of the A/D converter, together with its as-
However, to properly process these signals by a                                               sociated registers.
microcontroller, they must first be converted into digital
signals by A/D converters. By integrating the A/D con-                                        A/D Converter Data Registers - ADRL, ADRH
version electronic circuitry into the microcontroller, the                                    The device, which has an internal 12-bit A/D converter,
need for external components is reduced significantly                                         requires two data registers, a high byte register, known
with the corresponding follow-on benefits of lower costs                                      as ADRH, and a low byte register, known as ADRL. After
and reduced component space requirements.                                                     the conversion process takes place, these registers can
                                                                                              be directly read by the microcontroller to obtain the digit-
A/D Overview
                                                                                              ised conversion value. If the ADRFS bit is ²0², only the
The devices contains either a 12 or 20-channel analog                                         high byte register, ADRH, utilises its full 8-bit contents.
to digital converter which can directly interface to exter-                                   The low byte register utilises only 4 bit of its 8-bit con-
nal analog signals, such as that from sensors or other                                        tents as it contains only the lowest bits of the 12-bit con-
control signals and convert these signals directly into ei-                                   verted value. If the ADRFS bit is ²1², only the low byte
ther a 12-bit digital value.                                                                  register, ADRL, utilises its full 8-bit contents. The high
                              Input            Conversion              Input                  byte register utilises only 4 bit of its 8-bit contents as it
  Part No.                                                                                    contains only the highest bits of the 12-bit converted
                            Channels              Bits                  Pins
                                                                                              value.
                                                                      PA0~PA7,
 HT45R52                          12                12
                                                                      PB0~PB3
                                                                      PA0~PA7,
 HT45R54                          20                12                PB0~PB7,
                                                                      PC0~PC3



 Register                                                ADRH                                                                                 ADRL
 Bit                        7              6   5     4            3      2       1            0          7       6                 5         4             3         2             1             0
 ADRFS=0                    D11 D10            D9    D8           D7     D6      D5           D4       D3        D2           D1           D0             ¾          ¾             ¾             ¾
 ADRFS=1                    ¾              ¾   ¾     ¾        D11 D10            D9           D8       D7        D6           D5           D4             D3         D2            D1            D0

Note: D0~D11 are the A/D conversion result data bis
                                                                         A/D Data Registers


                                                     P A C .0                                                           fS   Y S
                                                           b it
                                                                                                     A D C S 0
       P A 0 /A N 0                                                                                                     C lo c k
                                                                                                   A D C S 1                                A V
                                                                                                                       D iv id e r                D D
                                P A .0                                                              A D C S 2
                                    b it             P A C .1                                                                                                        V R E F
                                                           b it
                                                                                                                                                                     V R E F S b it
       P A 1 /A N 1

                                P A .1
                                    b it                                                             M U X                     A /D    C o n v e rte r                   A D R H         A D R L
                                                                                   O P A                                                                                    C o n v e r s io n
                                                     P A C .3                    O u tp u t
                                                           b it                                                                                                                 V a lu e

     P C 3 /A N 1 9                                                                                 A D C A I
                                                                                                       b it
                                P C .3                                                                                S T A R T        E O C B           A D O N B
                                    b it                                                                                  b it            b it               b it
    A N C S R 0 ~
     A N C S R 2

     I/O o r A /D
 C h a n n e l S e le c t
                                                                       A/D Converter Structure


Rev. 1.00                                                                             32                                                                        September 21, 2010
                                                                                                                                                                                        HT45R52/HT45R54

                                                                                                                                 A V      D D


                                                  P A C 0                                                S 3 0
                               A N 0

                                                                        P A 0                            S 3 1

                                                            A V   S S
                                                                                                                                           A V       S S



                               A N 1
                                                                                                         S 3 6
                                                                                                                                                                              A /D    C o n v e rte r
                             A N 1 9


                         O P V IN N                                                                                                                                  S 3 7
                                                                                S 3 2
                                                                                                                     -
                                                                                                                         O P A
                                          S 3 3                                         S 3 4                    +
                                                                                                                                       V O P A
                         O P V IN P
                                                                                                             S 3 5
                          O P O U T
                               N o te : F o r A N x , x is 1 1 fo r H T 4 5 R 5 2 a n d x is 1 9 fo r H T 4 5 R 5 4 .
                                                                        A/D Converter Block Diagram




         b 7                                                                                            b 0
     S T A R T E O C B     A D O N B A D R F S V R E F S                A D C S 2       A D C S 1   A D C S 0               A D C R 0 R e g is te r

                                                                                                                            A /D c o n v e r te r c lo c k s o u r c e
                                                                                                                             A D C S 2 A D C S 1 A D C S 0
                                                                                                                                  0               0               0                                            fS           Y S
                                                                                                                                    0               0               1                                          fS           Y S   /2
                                                                                                                                      0               1               0                                        fS           Y S   /3
                                                                                                                                        0               1               1                                      fS           Y S   /4
                                                                                                                                          1               0               0                                    fS           Y S   /5
                                                                                                                                            1               0               1                                  fS           Y S   /6
                                                                                                                                              1               1               0                                fS           Y S   /7
                                                                                                                                                1               1               1                              fS           Y S   /8
                                                                                                                            A /D            v o lta g e               r e fe r e n c e s e le         c t
                                                                                                                             1 : V       R E F fro                  m e x te rn a l a n a              lo g         in       p u t v o lta g e
                                                                                                                              0 : V       R E F fro                  m in te r n a l A V D              D a           s       re fe re n c e
                                                                                                                                  If       P D 3 C 1               , P D 3 C 0 = 0 0 b               o r 0          1       b , th e A /D v o lta g e
                                                                                                                                  re         fe re n c e               is a lw a y s fr o m              A V            D     D .

                                                                                                                            D a ta           fo   rm       a t       c o n tro l
                                                                                                                             1 : lo         w e      r 8      -b      it d a ta in    A D R      L
                                                                                                                                  h      ig h     e r       4 -    b it d a ta in        lo w      n ib b le o f A D R H
                                                                                                                              0 : h      ig h      e r       8 -    b it d a ta in      A D     R H
                                                                                                                                    lo     w e      r 4       -b      it d a ta in   h ig h       n ib b le o f A D R L

                                                                                                                            A /D m o d u le o n /o ff c o n tr o l
                                                                                                                             1 : A /D c o n v e rte r p o w e re d d o w n
                                                                                                                              0 : A /D c o n v e rte r o n

                                                                                                                             E n d o f A /D c o n v e r s io n fla g
                                                                                                                              1 : A /D c o n v e r s io n w a itin g o r in p r o g r e s s
                                                                                                                            0 : A /D c o n v e r s io n e n d e d

                                                                                                                            S ta r t th e A /D c o n v e r s io n
                                                                                                                             0 ® 1 ® 0 : S ta rt
                                                                                                                              0 ® 1 : R e s e t A /D c o n v e rte r a n d s e t E O C B to "1 "

                                                        A/D Converter Control Register - ADCR0




Rev. 1.00                                                                                           33                                                                                                                            September 21, 2010
                                                                                                                                                                                         HT45R52/HT45R54

A/D Converter Control Registers - ADCR0, ADCR1, ADCR2, ANCSR0, ANCSR1 and ANCSR2
To control the function and operation of the A/D converter, six control registers are required: ADCR0~ ADCR2 and
ANCSR0~ANCSR2. These 8-bit registers define functions such as the selection of which analog channel is connected
to the internal A/D converter, which pins are used as analog inputs and which are used as normal I/Os, the A/D clock
source as well as controlling the start function and monitoring the A/D converter end of conversion status.

     Register                                  Function                                                                                                   Notes
   ANCSR0                         Channel Select                                    AN0~AN7
                                                                                    AN8~AN11 for both devices
   ANCSR1                         Channel Select
                                                                                    AN12~AN15 for HT45R54 only
   ANCSR2                         Channel Select                                    AN16~AN19 - HT45R54 only
   ADCR0                          A/D control register 0                            Clock Select, A/D ref. select, On/Off, Data format, Start, EOCB bit
   ADCR1                          A/D control register 1                            OPA reference select, A/D input select, pin configuration
   ADCR2                          A/D control register 2                            Analog switch control


    b 7                                                                                b 0
 P D 5 C    P D 4 C   P D 3 C 1 P D 3 C 0       A D C A I O P A V R 2 O P A V R 1 O P A V R 0           A D C R 1 R e g is te r

                                                                                                        O P A + in p u t r e fe r e n c e v o lta g e ( V O                               P A )
                                                                                                         O P A V R 2 O P A V R 1 O P A V R 0
                                                                                                              0               0               0               A                            V S S
                                                                                                                0               0               1               0                          .1 A         V        D D
                                                                                                                  0               1               0               0                        .2 A         V        D D
                                                                                                                    0               1               1               0                      .3 A         V        D D
                                                                                                                      1               0               0               0                    .4 A         V        D D
                                                                                                                        1               0               1               0                  .5 A         V        D D
                                                                                                                          1               1               0               0                .6 A         V        D D
                                                                                                                            1               1               1               0              .7 A         V        D D

                                                                                                        A /D c o n v e r te r in p u t
                                                                                                         1 : fro m O P A o u tp u t
                                                                                                          0 : fro m A N 0 ~ A N 1 1 o r A N 1 9

                                                                                                        P D 3 /O P V IN P /V R E F p in                          c o n fig u r a tio n
                                                                                                          P D 3 C 1     P D 3 C 0
                                                                                                              0             0        P                        D 3        I/O         p in
                                                                                                                0             1        O                        P A       O P      V IN P in p u t p in
                                                                                                                  1             0        A                     D C          V R   E F in p u t p in
                                                                                                                    1             1        O                     P A       O P      V IN P in p u t p in a n d A D C                                        V R E F in p u t p in
                                                                                                        P D 4 /O P V IN N p in c o n fig u r a tio n
                                                                                                         1 : O P A O P V IN N in p u t p in
                                                                                                          0 : P D 4 I/O p in

                                                                                                        P D 5 /O P O U T p in c o n fig u r a tio n
                                                                                                         1 : O P A O P O U T p in
                                                                                                          0 : P D 5 I/O p in
                                                               A/D Converter Control Register - ADCR1

      b 7                                                                               b 0
                      A S 3 5 C    A S 3 4 C    A S 3 3 C   A S 3 2 C   A S 3 1 C   A S 3 0 C   A D C R 2 R e g is te r

                                                                                                A n a lo g s w itc h e s S 3           0 /S 3 1 o p e n o r c lo s e d
                                                                                                 A S 3 1 C    A S 3 0 C
                                                                                                     0            0          A         n a lo      g S w           itc   h S 3      0 o p      e n          a n      d A      n a      lo    g S      w itc      h S      3 1      o p      e n
                                                                                                       0            1          A        n a lo      g S w          itc    h S 3      0 c lo       s e          a n      d A      n a    lo      g S      w itc      h S      3 1      o p     e n
                                                                                                         1            0          A       n a lo      g S w         itc     h S 3      0 o p     e n          a n      d A      n a     lo     g S      w itc      h S      3 1      c lo       s e
                                                                                                           1            1          A      n a lo      g S w        itc      h S 3      0 o p     e n          a n      d A      n a    lo      g S      w itc      h S      3 1      o p     e n
                                                                                                A n a lo g S w itc h S 3 2
                                                                                                 1 : c lo s e d
                                                                                                  0 : o p e n

                                                                                                A n a lo g S w itc h S 3 3
                                                                                                 1 : c lo s e d
                                                                                                  0 : o p e n

                                                                                                A n a lo g S w itc h S 3 4
                                                                                                 1 : c lo s e d
                                                                                                  0 : o p e n

                                                                                                A n a lo g S w itc h S 3 5
                                                                                                 1 : c lo s e d
                                                                                                  0 : o p e n

                                                                                                N o t im p le m e n te d , r e a d a s " 0 "

                                                               A/D Converter Control Register - ADCR2


Rev. 1.00                                                                                          34                                                                                                                            September 21, 2010
                                                                                                                                                         HT45R52/HT45R54

The A/D analog input channel select registers,                                                               Using the A/D with the internal OPA
ANCSR0~ANCSR2, are used to configure the A/D con-                                                            The devices contains an internal OPA which can be
verter analog inputs, to determine if the pins are used as                                                   used together with the A/D converter. The input to the
A/D inputs or normal I/Os. The ANCSR2 register only                                                          A/D converter circuit can be chosen to come from OPA,
exists in the HT45R54 device. Note that the PA~PC and                                                        using the ADCAI bit in the ADCR1 register. Internal ana-
PAC~PCC registers are also used to setup the A/D con-                                                        log switches in the devices determine how the OPA is
verter channel input pins.                                                                                   configured and used. Internal registers are used to con-
                                                                                                             trol these analog switches, the details of which are de-
A/D Input Pin Setup
                                                                                                             scribed in the accompanying register diagrams.
Pins are selected to be an A/D input using bits the
ANCSR0~ANCSR2 registers. Once this happens the                                                               A/D Operation
normal I/O function and any pull-high resistor selections                                                    The ANCSR0~ANCSR2 registers are used to deter-
will be disabled automatically. This also causes the I/O                                                     mine which pins on Port A to Port C are used as analog
Data registers, PA, PB, PC, and Port Control Registers,                                                      inputs for the A/D converter and which pins are to be
PAC, PBC and PCC, to lose their original I/O control                                                         used as normal I/O pins. As the device contains only
function. The Port Control Registers can now be used to                                                      one actual analog to digital converter circuit, the Port
select which A/D input is connected to the internal A/D                                                      Control registers, PAC~PCC, determine which of indi-
converter, while the I/O data registers are used to deter-                                                   vidual analog inputs is to be routed to the converter.
mine if the selected I/O pins are connected to ground or
not. Care must be taken when programming these reg-                                                          The START bit in the ADCR0 register is used to start
isters to ensure that several A/D input pins are not con-                                                    and reset the A/D converter. When the device changes
nected together. The ADCAI bit in the ADCR1 register is                                                      this bit from low to high and then low again, an analog to
used to select whether the analog input pins or the OPA                                                      digital conversion cycle will be initiated. When the
is connected to the A/D converter.                                                                           START bit is brought from low to high but not low again,
                                                                                                             the EOCB bit in the ADCR0 register will be set high and
A/D Power Supply and Reference Pins                                                                          the analog to digital converter will be reset. It is the
                                                                                                             START bit that is used to control the overall on/off opera-
The A/D converter has its own power supply pins, AVDD
                                                                                                             tion of the internal analog to digital converter.
and AVSS as well as a separate VREF reference pin.
The analog input values must not be allowed to exceed                                                        The EOCB bit in the ADCR0 register is used to indicate
the value of VREF. The ADONB bit in the ADCR0 regis-                                                         when the analog to digital conversion process is com-
ter is used to control the overall on/off function of the A/D                                                plete. This bit will be automatically set to ²0² by the de-
converter. Setting this bit high will disable the internal                                                   vice after a conversion cycle has ended. In addition, the
A/D converter circuitry thus reducing power consump-                                                         corresponding A/D interrupt request flag will be set in
tion. Once the A/D converter is disabled, the A/D con-                                                       the interrupt control register, and if the interrupts are en-
verter will have no power consumption irrespective of                                                        abled, the program will jump to the associated A/D inter-
what voltage levels exist on the analog input lines. The                                                     nal interrupt address for processing. If the A/D internal
A/D reference voltage can be chosen to come from ei-                                                         interrupt is disabled, the microcontroller can be used to
ther AVDD or the external reference VREF pin using the                                                       poll the EOCB bit register to check whether it has been
VREFS bit in the ADCR0 register.                                                                             cleared as an alternative method of detecting the end of
                                                                                                             an A/D conversion cycle.
                                                                   P D 4
                                               P D 4 C
                                                    b it
                                                                                                   P D 5 C      b it
                           O P V IN N                                                                   P D 5
                                                                                       -
                                                                                                                                      P D 5 /O P O U T
                                                                                           O P A
                                                                                   +
                                                           S 3 2

                            F ro m    A /D
                                                           S 3 4
                                                                                                     S 3 5
                                                                                                                                                          V R E F S b it
            P D 3 /O P V IN P /V R E F                                                                                 V O P A
                                                                           P D 3                                                 A V D D
                                                                                                                                                          T o A /D C o n v e rte r
                                                                                                                                                           R e fe r e n c e V o lta g e

                                 P D 3 C 0
                                  P D 3 C 1
                                       b itS
                                                                               OPA Structure


Rev. 1.00                                                                                           35                                                                 September 21, 2010
                                                                                                  HT45R52/HT45R54

The clock source for the A/D converter, which originates              · Step 2
from the system clock fSYS, is first divided by a division ra-          Enable the A/D by clearing the ADONB to zero.
tio, the value of which is determined by the                          · Step 3
ADCS0~ADCS2 bits in the ADCR0 register. There are                       Select which pins are to be used as analog inputs by
some limitations on the maximum A/D clock source                        correctly programming the bits in the ANCSR2,
speed that can be selected. As the minimum value of per-                ANCSR1 and ANCSR0 registers.
missible A/D clock period, tAD, is 0.5us, care must be                · Step 4
taken for system clock speeds in excess of 4MHz. For                    Select which analog input pin is to be connected to the
system clock speeds in excess of 4MHz, the ADCS2,                       A/D converter by programming the PAC~PCC port
ADCS1 and ADCS0 bits should not be set to 000. Doing                    control registers. The data registers PA~PC must be
so will give A/D clock periods that are less than the mini-             set to ²1² to disconnect the ADC input pins from AVSS.
mum A/D clock period which may result in inaccurate A/D
                                                                      · Step 5
conversion values. Refer to the accompanying table for
                                                                        If the interrupts are to be used, the interrupt control reg-
examples, where values marked with an asterisk * show
                                                                        isters must be correctly configured to ensure the A/D
where special care must be taken, as the values may be                  converter interrupt function is active. The master inter-
less than the specified minimum A/D Clock Period.                       rupt control bit, EMI, in the INTC0 interrupt control reg-
Controlling the on/off function of the A/D converter cir-               ister must be set to ²1², the A/D converter interrupt bit,
cuitry is implemented using the ADONB bit in the                        EADI, in the INTC1 register must also be set to ²1².
ADCR0 register. The ADONB bit must cleared to zero to                 · Step 6
enable the A/D converter to be enabled. Setting the                     The analog to digital conversion process can now be
ADONB bit high will disable the A/D converter, and re-                  initialised by setting the START bit in the ADCR0 reg-
duce its power consumption accordingly.                                 ister from ²0² to ²1² and then to ²0² again. Note that
                         A/D Clock Period (tAD)                         this bit should have been originally set to ²0².

                ADCS2, ADCS2, ADCS2, ADCS2,                           · Step 7

     fSYS       ADCS1, ADCS1, ADCS1, ADCS1,                             To check when the analog to digital conversion pro-
                ADCS0= ADCS0= ADCS0= ADCS0=                             cess is complete, the EOCB bit in the ADCR0 register
                  000     001      010      101                         can be polled. The conversion process is complete
                 (fSYS) (fSYS/2) (fSYS/3) (fSYS/6)                      when this bit goes low. When this occurs the A/D data
                                                                        registers ADRL and ADRH can be read to obtain the
    1MHz          1ms         2ms        3ms         6ms
                                                                        conversion value. As an alternative method if the in-
    2MHz         500ns        1ms       1.5ms        3ms                terrupts are enabled and the stack is not full, the pro-
    4MHz        250ns*      500ns       750ns       1.5ms               gram can wait for an A/D interrupt to occur.

    8MHz        125ns*      250ns*      375ns*      750ns             Note:    When checking for the end of the conversion
                                                                               process, if the method of polling the EOCB bit in
   12MHz         83ns*      167ns*      250ns*      500ns
                                                                               the ADCR0 register is used, the interrupt en-
              A/D Clock Period Examples                                        able step above can be omitted.
                                                                      The accompanying diagram shows graphically the vari-
A/D Interrupt
                                                                      ous stages involved in an analog to digital conversion
The A/D converter has its own interrupt and independ-                 process and its associated timing.
ent interrupt vector. When an end of conversion occurs,
                                                                      The setting up and operation of the A/D converter func-
if the interrupts are enabled and the stack is not full, the
                                                                      tion is fully under the control of the application program as
program will jump to this vector location. If it is not de-
                                                                      there are no configuration options associated with the
sired to use the A/D interrupt, then polling the EOCB bit
                                                                      A/D converter. After an A/D conversion process has been
is another way of determining when the A/D conversion
                                                                      initiated by the application program, the microcontroller
process has finished.
                                                                      internal hardware will begin to carry out the conversion,
Summary of A/D Conversion Steps                                       during which time the program can continue with other
                                                                      functions. The time taken for the A/D conversion is 16tAD
The following summarises the individual steps that
                                                                      where tAD is equal to the A/D clock period.
should be executed in order to implement an A/D con-
version process.
· Step 1
  Select the required A/D conversion clock by correctly
  programming bits ADCS2, ADCS1 and ADCS0 in the
  ADCR0 register.




Rev. 1.00                                                        36                                         September 21, 2010
                                                                                                                                                                                                                                          HT45R52/HT45R54

Programming Considerations                                                                                                                                                         A/D Transfer Function
The ADONB bit in the ADCR0 register can also be used                                                                                                                               As the device contain a 12-bit A/D converter, its
to power down the A/D function. If the shared function                                                                                                                             full-scale converted digitised value is equal to FFFH.
analog input lines are selected to be I/O lines then care                                                                                                                          Since the full-scale analog input value is equal to the
must be taken with the voltage level on these pins. If the                                                                                                                         VDD voltage, this gives a single bit analog input value of
input voltages are not within the specified range of the                                                                                                                           VDD/4096. The diagram show the ideal transfer function
I/O logic voltage levels, then there may be increased                                                                                                                              between the analog input value and the digitised output
current consumed by these I/O pins. Care must also be                                                                                                                              value for the A/D converter.
taken when programming the port control registers
                                                                                                                                                                                   Except for the digitised zero value, the subsequent digit-
PAC~PCC to ensure that no analog input channels are
                                                                                                                                                                                   ised values will change at a point 0.5 LSB below where
connected together.
                                                                                                                                                                                   they would change without the offset, and the last full
                                                                                                                                                                                   scale digitised value will change at a point 1.5 LSB be-
                                                                                                                                                                                   low the VDD level.




         A D O N B

                                                                 tO     N 2 S T

 A D C   m o d u le
               O N                                                o n                                                                                                                                                                     o ff               o n   o ff
                                                                                     A /D      s a m p lin g tim e                                   A /D      s a m p lin g tim e
                                                                                       tA   D C S                                                      tA   D C S



         S T A R T



           E O C B


 A /D C h a n n e l
  S e le c t                       A N n                                                      A N n                                                            A N n                                                      A N n                                      A N n

                                                                              S ta rt o f A /D                                             S ta rt o f A /D                                                 S ta rt o f A /D
                                                                               c o n v e r s io n                                           c o n v e r s io n                                               c o n v e r s io n
                                                          R e s e t A /D                                                    R e s e t A /D                                                   R e s e t A /D
                                                           c o n v e rte r                                                   c o n v e rte r                                                  c o n v e rte r
                                                                                                          E n d o f A /D                                                   E n d o f A /D
                                  S e le c t a n a lo g                                                    c o n v e r s io n                                               c o n v e r s io n
                                   c h a n n e l
                                                                                                   tA D C                                                          tA D C
                                                                                  A /D      c o n v e r s io n tim e                               A /D     c o n v e r s io n tim e

                      N o te :   A N n is A /D      c h a n n e l s e le c t b y s o ftw a r e .

                                                                                                                                    A/D Conversion Timing




                                                                                                                                                                                                                        1 .5 L S B
                                                                                                    F F F H

                                                                                                    F F E H

                                                                                                    F F D H
                                           A /D C o n v e r s io n
                                            R e s u lt
                                                                                                                                    0 .5 L S B
                                                                                                      0 3 H

                                                                                                      0 2 H

                                                                                                      0 1 H

                                                                                                                                                                                                                                                  V D D
                                                                                                                                                                                                                                          (              )
                                                                                                               0                1              2                     3                    4 0 9 3 4 0 9 4               4 0 9 5 4 0 9 6          4 0 9 6
                                                                                                                                                                    A n a lo g In p u t V o lta g e
                                                                                                                            Ideal A/D Transfer Function




Rev. 1.00                                                                                                                                                                37                                                                                  September 21, 2010
                                                                                              HT45R52/HT45R54

Operational Amplifier - OPA
The devices contain a single operational amplifier, oth-            A reference voltage which is a division ratio of the AVDD
erwise known as the OPA. The OPA is controlled using                voltage can be supplied to the OPA input. The actual
internal registers.                                                 supplied voltage is selected using the OPAVR0~
                                                                    OPAVR2 bits in the ADCR1 register.
OPA Operation
The internal OPA can be used as a stand alone opera-                OPA Input Offset Cancellation
tional amplifier or in conjunction with the A/D converter. A        Bits in the OPAC register can be used to reduce the OPA
range of internal analog switches allows users to config-           offset voltage to a minimum value. The OPA is first en-
ure the OPA in a number of different configurations.                abled and setup in the input offset cancellation mode by
These analog switches are setup using internal registers.           setting the AOFM bit. Then either the inverting or the
                                                                    non-inverting OPA input is chosen as the reference input
The OPAC register is used to control the on/off function
                                                                    using the ARS bit. Now the AOFn bits can be incre-
of the OPA function and also to control the offset
                                                                    mented or decremented until the OPA output bit
cancellation. The OPAEN bit in this register is used to
                                                                    changes state. At this point the OPA is adjusted to its
enable or disable the OPA. If the OPAEN bit is cleared to
                                                                    minimum offset value. Note that it is the output bit,
zero, the OPA is disabled and also powered off to re-
duce power consumption. The other bits in this register             OPAOP, in the OPAC register that is monitored for a
are used to setup the offset cancellation function.                 change of state and not the physical OPA output pin.
                                                                    The input offset cancellation process can be summa-
OPVINN and OPVINP are the OPA inverting and non-in-
                                                                    rised as follows:
verting input pins while the OPOUT pin is the OPA out-
put pin. As the OPA pins are shared with other pin                  1. Set the OPAEN bit high to enable the OPA.
functions, they must be selected using bits in the                  2. Set the AOFM bit high to enable the offset cancella-
ADCR1 register.
                                                                    tion mode.
If the OPVINP or VREF functions are active, then the in-            3. Set the ARS bit high or low to select which input pin is
ternal registers related to pin PD3 cannot be used. The
                                                                    to be used as the reference voltage.
normal I/O function and any pull-high resistor connec-
tion will be disabled automatically. Software instructions          4. Adjust bits AOF0~AOF3 and monitor the OPAOP bit
determine whether the PD3 I/O function, OPVINP or                   until it changes state.
VREF function is to be used.                                        5. Clear the AOFM bit to zero ro resume normal OPA op-
                                                                    eration.




            Pin                  PD3C1               PD3C0                  PD3              OPVINP              VREF
                                     0                  0                  Active            Disable            Disable
                                     0                  1                 Disable             Active            Disable
   PD3/OPVINP/VREF
                                     1                  0                 Disable            Disable             Active
                                     1                  1                 Disable             Active             Active

        Bit Name                                                       Description
                             PD4/OPVINN pin configuration
            PD4C             1: OPA OPVINN input
                             0: PD4 I/O
                             PD5/OPOUT pin configuration
            PD5C             1: OPA OPOUT
                             0: PD5 I/O

Note: PD4C and PD5C are in the ADRC1 register.




Rev. 1.00                                                      38                                        September 21, 2010
                                                                                                                                                      HT45R52/HT45R54

            b 7                                                                              b 0
         O P A E N        O P A O P   A O F M   A R S    A O F 3   A O F 2    A O F 1    A O F 0         O P A C              R e g is te r

                                                                                                         O ffs e t v o lta g e c a n c e lla tio n c o n tr o l b its

                                                                                                         O ffs e t v o lta g e c a n c e lla tio n r e fe r e n c e s e le c tio n
                                                                                                          1 : S e le c t O P V IN P a s th e r e fe r e n c e in p u t
                                                                                                           0 : S e le c t O P V IN N a s th e r e fe r e n c e in p u t

                                                                                                         O P A m o d e s e le c tio n
                                                                                                          1 : In p u t o ffs e t v o lta g e c a n c e lla tio n m o d e
                                                                                                           0 : N o rm a l O P A m o d e

                                                                                                         O ffs e t v o lta g e c a n c e lla tio n m o d e o u tp u t r e a d b it
                                                                                                          r e a d o n ly b it

                                                                                                         O P A       e n         a b le /d is a b le
                                                                                                          1 : O P       A      e n a b le d
                                                                                                           0 : O P        A     o ff to r e d u c e M C U p o w e r c o n s u m p tio n .
                                                                                                               O P    O       U T m u s t b e in a flo a tin g s ta te

                                                                             OPAC Register



Serial Interface Function
The device contains a Serial Interface Function, which                                             The communication is full duplex and operates as a
includes both the four line SPI interface and the two line                                         slave/master type, where the MCU can be either master
I2C interface types, to allow an easy method of commu-                                             or slave. Although the SPI interface specification can
nication with external peripheral hardware. Having rela-                                           control multiple slave devices from a single master,
tively simple communication protocols, these serial                                                here, as only a single select pin, SCS, is provided only
interface types allow the microcontroller to interface to                                          one slave device can be connected to the SPI bus.
external SPI or I2C based hardware such as sensors,                                                · SPI Interface Operation
Flash or EEPROM memory, etc. The SIM interface pins                                                  The SPI interface is a full duplex synchronous serial
are pin-shared with other I/O pins therefore the SIM in-                                             data link. It is a four line interface with pin names SDI,
terface function must first be selected using a configura-                                           SDO, SCK and SCS. Pins SDI and SDO are the Serial
tion option. As both interface types share the same pins                                             Data Input and Serial Data Output lines, SCK is the
and registers, the choice of whether the SPI or I2C type                                             Serial Clock line and SCS is the Slave Select line. As
                                                                                                     the SPI interface pins are pin-shared with normal I/O
is used is made using a bit in an internal register.
                                                                                                     pins and with the I2C function pins, the SPI interface
SPI Interface                                                                                        must first be enabled by selecting the SIM enable con-
                                                                                                     figuration option and setting the correct bits in the
The SPI interface is often used to communicate with ex-                                              SIMCTL0/SIMCTL2 register. After the SPI configura-
ternal peripheral devices such as sensors, Flash or                                                  tion option has been configured it can also be addi-
EEPROM memory devices etc. Originally developed by                                                   tionally disabled or enabled using the SIMEN bit in the
Motorola, the four line SPI interface is a synchronous                                               SIMCTL0 register. Communication between devices
serial data interface that has a relatively simple commu-                                            connected to the SPI interface is carried out in a
nication protocol simplifying the programming require-                                               slave/master mode with all data transfer initiations be-
                                                                                                     ing implemented by the master. The Master also con-
ments when communicating with external hardware
                                                                                                     trols the clock signal. As the device only contains a
devices.
                                                                                                     single SCS pin only one slave device can be utilised.
                  S P I M a s te r              S P I S la v e
                           S C K                S C K
                                                                                                     The SPI function in this device offers the following fea-
                                                                                                     tures:
                          S D O                 S D I
                                                                                                     ¨   Full duplex synchronous data transfer
                            S D I               S D O                                                ¨   Both Master and Slave modes
                           S C S                S C S                                                ¨   LSB first or MSB first data transmission modes
                                                                                                     ¨   Transmission complete flag
             SPI Master/Slave Connection
                                                                                                     ¨   Rising or falling active clock edge
                                                                                                     ¨   WCOL and CSEN bit enabled or disable select




Rev. 1.00                                                                               39                                                                            September 21, 2010
                                                                                                                                                                HT45R52/HT45R54

 The status of the SPI interface pins is determined by a                                                       SPI Registers
 number of factors such as whether the device is in the
                                                                                                               There are three internal registers which control the over-
 master or slave mode and upon the condition of cer-
                                                                                                               all operation of the SPI interface. These are the SIMDR
 tain control bits such as CSEN, SIMEN and SCS. In
 the table I, Z represents an input floating condition.                                                        data register and two control registers SIMCTL0 and
 There are several configuration options associated                                                            SIMCTL2. Note that the SIMCTL1 register is only used
 with the SPI interface. One of these is to enable the                                                         by the I2C interface.
 SIM function which selects the SIM pins rather than
                                                                                                               The SIMDRregister is used to store the data being trans-
 normal I/O pins. Note that if the configuration option
                                                                                                               mitted and received. The same register is used by both
 does not select the SIM function then the SIMEN bit in
 the SIMCTL0 register will have no effect. Another two                                                         the SPI and I2C functions. Before the microcontroller
 SIM configuration options determine if the CSEN and                                                           writes data to the SPI bus, the actual data to be transmit-
 WCOL bits are to be used.                                                                                     ted must be placed in the SIMDR register. After the data
                                                                                                               is received from the SPI bus, the microcontroller can read
  Configuration Option                                          Function                                       it from the SIMDRregister. Any transmission or reception
 SIM Function                                 SIM interface or I/O pins                                        of data from the SPI bus must be made via the SIMDR
                                                                                                               register.
 SPI CSEN bit                                 Enable/Disable
 SPI WCOL bit                                 Enable/Disable

         SPI Interface Configuration Options



                                                            Master - SIMEN=1                                                                        Slave - SIMEN=1
            Master/Salve
   Pin                                                                                                                                                         CSEN=1               CSEN=1
             SIMEN=0                                      CSEN=0                          CSEN=1                        CSEN=0
                                                                                                                                                               SCS=0                 SCS=1
  SCS              Z                                        Z                                L                                   Z                              I, Z                   I, Z
  SDO              Z                                        O                               O                                    O                                O                     Z
   SDI             Z                                       I, Z                             I, Z                               I, Z                             I, Z                    Z
                                                   H: CKPOL=0                       H: CKPOL=0
  SCK              Z                                                                                                           I, Z                             I, Z                    Z
                                                   L: CKPOL=1                       L: CKPOL=1

Note:    ²Z² floating, ²H² output high, ²L² output low, ²I² Input, ²O²output level, ²I,Z² input floating (no pull-high)
                                                                                 SPI Interface Pin Status



                                                                                                               D a ta B u s


                                                                                 S IM D R


                                                                                                                                            S D I P in
                                                                           T x /R x S h ift R e g is te r
                                                                                                                                            S D O       P in


                           C K E N b it                                  C lo c k                                             E n a b le /D is a b le
                                                                  E d g e /P o la r ity
                         C K P O L b it                                C o n tro l                  B u s y                    C o n fig u r a tio n
                                                                                                   S ta tu s                                                    W C O L F la g
                                                                                                                                    O p tio n
                    S C K P in

                                    fS       Y S/4                                                                                                              T R F F la g
                               fS Y      S   /1 6
                               fS Y                                      C lo c k
                                          S /3 2
                                                                  S o u r c e S e le c t
                             3 2 K          R C
                                  P      F D 0

                    S C S P in

                           C S E N                 b it           C o n fig u r a tio n
                                                                       O p tio n

                                                                E n a b le /D is a b le
                                                                                      SPI Block Diagram


Rev. 1.00                                                                                           40                                                                         September 21, 2010
                                                                                                                                                                                                                           HT45R52/HT45R54

   b 7                                                                                     b 0
 S IM 2   S IM 1   S IM 0   P C K E N   P C K P S C 1 P C K P S C 0 S IM E N                           S IM C T L 0 R e g is te r

                                                                                                           N o t im p le m e n te d , r e a d a s " 0 "

                                                                                                           S P I / I2 C O n / O f f c o n t r o l
                                                                                                            1 : e n a b le
                                                                                                             0 : d is a b le

                                                                                                           P e r ip h e r a l C lo c k C o n tr o l - d e s c r ib e d e ls e w h e r e

                                                                                                           S P I/I2 C                   M a s te r /S la v e a n d                                    C lo c k C o n tr o l
                                                                                                            S IM 2                       S IM 1              S IM 0
                                                                                                                0                            0                   0               m                     a s       te   r,   fS Y   S   /4
                                                                                                                  0                            0                   1               m                    a s      te   r,   fS Y   S  /1 6
                                                                                                                    0                            1                   0               m                   a s     te   r,   fS Y   S  /6 4
                                                                                                                      0                            1                   1               m                  a s    te   r,   3 2    K R C
                                                                                                                        1                            0                   0               m                 a s   te   r,    P F    D 0
                                                                                                                          1                            0                   1               S          la v       e
                                                                                                                            1                            1                   0               I2   C      m o d e
                                                                                                                              1                            1                   1             N        o t u s e d

                                                              SPI/I2C Control Register - SIMCTL0


                                b 7                                                                                               b 0
                              H C F     H A A S     H B B      H T X    T X A K    S R W          R C IN                R X A K                       S IM C T L 1 R e g is te r

                                                                                                                                                      R e c e iv e a c k n o w le d g e fla g
                                                                                                                                                       1 : n o t a c k n o w le d g e d
                                                                                                                                                        0 : a c k n o w le d g e d
                                                                                                                                                      I2 C r u n n in g n o t u s in g in te r n a l c lo c k .
                                                                                                                                                      1 : I2 C r u n n in g n o t u s in g in te r n a l c lo c k
                                                                                                                                                       0 : I2 C r u n n in g u s in g in te r n a l c lo c k

                                                                                                                                                      M a s te r d a ta r e a d /w r ite r e q u e s t fla g
                                                                                                                                                       1 : re q u e s t d a ta re a d
                                                                                                                                                        0 : r e q u e s t d a ta w r ite

                                                                                                                                                      T r a n s m it a c k n o w le d g e fla g
                                                                                                                                                       1 : d o n 't a c k n o w le d g e
                                                                                                                                                        0 : a c k n o w le d g e

                                                                                                                                                      T r a n s m it/R e c e iv e m o d e
                                                                                                                                                       1 : tr a n s m it m o d e
                                                                                                                                                        0 : r e c e iv e m o d e
                                                                                                                                                        2
                                                                                                                                                      I C b u s b u s y fla g
                                                                                                                                                       1 : b u s y
                                                                                                                                                        0 : n o t b u s y

                                                                                                                                                      C a llin g a d d r e s s m a tc h e d fla g
                                                                                                                                                       1 : m a tc h e d
                                                                                                                                                        0 : n o t m a tc h e d

                                                                                                                                                      D a ta tr a n s fe r fla g
                                                                                                                                                       1 : tr a n s fe r c o m p le te
                                                                                                                                                        0 : tr a n s fe r n o t c o m p le te

                                                                I2C Control Register - SIMCTL1


                               b 7                                                                                           b 0
                                                  C K P O L   C K E G   M L S     C S E N        W C O L                  T R F                     S IM C T L 2 R e g is te r

                                                                                                                                                     T r a n s m it/R e c e iv e c o m p le te fla g
                                                                                                                                                      1 : fin is h e d
                                                                                                                                                       0 : in p r o g r e s s
                                                                                                                                                     W r ite c o llis io n fla g
                                                                                                                                                      1 : c o llis io n
                                                                                                                                                       0 : n o c o llis io n

                                                                                                                                                     S C S p in e n a b le
                                                                                                                                                      1 : e n a b le
                                                                                                                                                       0 : S C S flo a tin g

                                                                                                                                                     D a ta s h ift o r d e r
                                                                                                                                                      1 : M S B
                                                                                                                                                       0 : L S B

                                                                                                                                                     S P I C lo c k E d g e S e le c t
                                                                                                                                                      1 : s e e te x t
                                                                                                                                                       0 : s e e te x t

                                                                                                                                                     S P I C lo c k P o la r ity
                                                                                                                                                      1 : s e e te x t
                                                                                                                                                       0 : s e e te x t

                                                                                                                                                     N o t im p le m e n te d , r e a d a s " 0 "

                                                               SPI Control Register - SIMCTL2


Rev. 1.00                                                                                        41                                                                                                                                         September 21, 2010
                                                                                               HT45R52/HT45R54

  Bit       7    6     5     4      3     2     1      0                                        SPI Master/Slave Clock
                                                                       SIM0    SIM1     SIM2
                                                                                                Control and I2C Enable
 Label SD7 SD6 SD5 SD4 SD3 SD2 SD1 SD0
                                                                         0       0        0    SPI Master, fSYS/4
 R/W     R/W R/W R/W R/W R/W R/W R/W R/W
                                                                         0       0        1    SPI Master, fSYS/16
 POR        X   X      X     X      X     X     X      X
                                                                         0       1        0    SPI Master, fSYS/64
There are also two control registers for the SPI inter-                  0       1        1    SPI Master, fSUB
face, SIMCTL0 and SIMCTL2. Note that the SIMCTL2
                                                                                               SPI Master Timer/Event
register also has the name SIMAR which is used by the                    1       0        0
                                                                                               Counter 0 output/2
I2C function. The SIMCTL1 register is not used by the
SPI function, only by the I 2 C function. Register                       1       0        1    SPI Slave
SIMCTL0 is used to control the enable/disable function                   1       1        0    I2C mode
and to set the data transmission clock frequency. Al-
                                                                         1       1        0    Not used
though not connected with the SPI function, the
SIMCTL0 register is also used to control the Peripheral
Clock prescaler. Register SIMCTL2 is used for other                 SPI Control Register - SIMCTL2
control functions such as LSB/MSB selection, write colli-           The SIMCTL2 register is also used by the I2C interface
sion flag etc.                                                      but has the name SIMAR.
The following gives further explanation of each                     · TRF
SIMCTL1 register bit:                                                The TRF bit is the Transmit/Receive Complete flag and
                                                                     is set high automatically when an SPI data transmis-
· SIMIDLE
                                                                     sion is completed, but must be cleared by the applica-
  The SIMIDLE bit is used to select if the SPI interface             tion program. It can be used to generate an interrupt.
  continues running when the device is in the IDLE
  mode. Setting the bit high allows the SPI interface to            · WCOL
  maintain operation when the device is in the Idle                  The WCOL bit is used to detect if a data collision has
  mode. Clearing the bit to zero disables any SPI opera-             occurred. If this bit is high it means that data has been
  tions when in the Idle mode.                                       attempted to be written to the SIMDR register during a
  This SPI/I2C idle mode control bit is located at                   data transfer operation. This writing operation will be
  CLKMOD register bit4.                                              ignored if data is being transferred. The bit can be
                                                                     cleared by the application program. Note that using
· SIMEN
                                                                     the WCOL bit can be disabled or enabled via configu-
  The bit is the overall on/off control for the SPI inter-           ration option.
  face. When the SIMEN bit is cleared to zero to disable
  the SPI interface, the SDI, SDO, SCK and SCS lines                · CSEN
  will be in a floating condition and the SPI operating              The CSEN bit is used as an on/off control for the SCS
  current will be reduced to a minimum value. When the               pin. If this bit is low then the SCS pin will be disabled
  bit is high the SPI interface is enabled. The SIMconfig-           and placed into a floating condition. If the bit is high
  uration option must have first enabled the SIM inter-              the SCS pin will be enabled and used as a select pin.
  face for this bit to be effective. Note that when the              Note that using the CSEN bit can be disabled or en-
  SIMEN bit changes from low to high the contents of                 abled via configuration option.
  the SPI control registers will be in an unknown condi-
                                                                    · MLS
  tion and should therefore be first initialised by the ap-
                                                                      This is the data shift select bit and is used to select
  plication program.
                                                                      how the data is transferred, either MSB or LSB first.
· SIM0~SIM2                                                           Setting the bit high will select MSB first and low for
  These bits setup the overall operating mode of the SIM              LSB first.
  function. As well as selecting if the I2C or SPI function,
  they are used to control the SPI Master/Slave selec-              · CKEG and CKPOL
  tion and the SPI Master clock frequency. The SPI                   These two bits are used to setup the way that the
  clock is a function of the system clock but can also be            clock signal outputs and inputs data on the SPI bus.
  chosen to be sourced from the Timer/Event Counter. If              These two bits must be configured before data trans-
  the SPI Slave Mode is selected then the clock will be              fer is executed otherwise an erroneous clock edge
  supplied by an external Master device.                             may be generated. The CKPOL bit determines the
                                                                     base condition of the clock line, if the bit is high then
                                                                     the SCK line will be low when the clock is inactive.




Rev. 1.00                                                      42                                      September 21, 2010
                                                                                                                                                            HT45R52/HT45R54

                                                                           S IM E N = 1 , C S E N = 0 ( E x te r n a l P u ll- H ig h )
            S C S                                                          S IM E N , C S E N = 1


            S C K (C K P O L = 1 , C K E G = 0 )


            S C K (C K P O L = 0 , C K E G = 0 )


            S C K (C K P O L = 1 , C K E G = 1 )


            S C K (C K P O L = 0 , C K E G = 1 )


            S D O   (C K E G = 0 )                                            D 7 /D 0    D 6 /D 1    D 5 /D 2    D 4 /D 3       D 3 /D 4       D 2 /D 5       D 1 /D 6       D 0 /D 7


            S D O   (C K E G = 1 )                                            D 7 /D 0    D 6 /D 1    D 5 /D 2    D 4 /D 3       D 3 /D 4       D 2 /D 5       D 1 /D 6       D 0 /D 7


            S D I D a ta C a p tu re
                                                                      W r ite to S IM D R

                                                                     SPI Master Mode Timing




                    S C S



                    S C K (C K P O L = 1 )


                    S C K (C K P O L = 0 )


                    S D O                                               D 7 /D 0     D 6 /D 1    D 5 /D 2    D 4 /D 3        D 3 /D 4       D 2 /D 5       D 1 /D 6       D 0 /D 7


                    S D I D a ta C a p tu re
                                                          W r ite to S IM D R
                                                           ( S D O n o t c h a n g e u n til fir s t S C K e d g e )

                                                             SPI Slave Mode Timing (CKEG=0)




                    S C S


                    S C K (C K P O L = 1 )


                    S C K (C K P O L = 0 )


                    S D O                                               D 7 /D 0     D 6 /D 1    D 5 /D 2    D 4 /D 3        D 3 /D 4       D 2 /D 5       D 1 /D 6       D 0 /D 7


                    S D I D a ta C a p tu re
                                               W r ite to S IM D R
                                                ( S D O c h a n g e a s s o o n a s w r itin g o c c u r ; S D O = flo a tin g if S C S = 1 )

                                                   N o te : F o r S P I s la v e m o d e , if S IM E N = 1 a n d C S E N = 0 , S P I is a lw a y s e n a b le d
                                                             a n d ig n o r e th e S C S le v e l.

                                                             SPI Slave Mode Timing (CKEG=1)




Rev. 1.00                                                                                   43                                                                                   September 21, 2010
                                                                                                                HT45R52/HT45R54

                                                                                                                           A


                                    S P I tra n s fe r
                                                                                                                    W r ite D a ta
                                                                                     C le a r W C O L
                                                                                                                   in to S IM D R



                 M a s te r           m a s te r o r       S la v e
                                         s la v e                                                           Y
                                                                                                                    W C O L = 1 ?


       S IM [2 :0 ]= 0 0 0 ,
                                                          S IM [2 :0 ]= 1 0 1                                                    N
  0 0 1 ,0 1 0 ,0 1 1 o r 1 0 0



                                                                                                        N         T r a n s m is s io n
                                                                                                                   c o m p le te d ?
                                       c o n fig u r e                                                               (T R F = 1 ? )
                                  C S E N a n d M L S

                                                                                                                                         Y

                                                                                                                    R e a d D a ta
                                      S IM E N = 1
                                                                                                                   fro m S IM D R



                                             A                                                                      C le a r T R F




                                                                                                                     T ra n s fe r           N
                                                                                                                    F in is h e d ?


                                                                                                                                     Y

                                                                                                                         E N D


                                                         SPI Transfer Control Flowchart




Rev. 1.00                                                                       44                                      September 21, 2010
                                                                                                     HT45R52/HT45R54

  When the CKPOL bit is low then the SCK line will be                     · I2C Interface Operation
  high when the clock is inactive. The CKEG bit deter-                      The I2C serial interface is a two line interface, a serial
  mines active clock edge type which depends upon the                       data line, SDA, and serial clock line, SCL. As many
  condition of CKPOL.                                                       devices may be connected together on the same bus,
                                                                            their outputs are both open drain types. For this rea-
  CKPOL         CKEG                            SCK Clock Signal            son it is necessary that external pull-high resistors are
                                                 High Base Level            connected to these outputs. Note that no chip select
      0            0
                                                Active Rising Edge          line exists, as each device on the I2C bus is identified
                                             High Base Level                by a unique address which will be transmitted and re-
      0            1                                                        ceived on the I2C bus.
                                            Active Falling Edge
                                                                            When two devices communicate with each other on
                                             Low Base Level
      1            0                                                        the bidirectional I2C bus, one is known as the master
                                            Active Falling Edge
                                                                            device and one as the slave device. Both master and
                                                 Low Base Level             slave can transmit and receive data, however, it is the
      1            1
                                                Active Rising Edge          master device that has overall control of the bus. For
                                                                            these devices, which only operates in slave mode,
SPI Communication                                                           there are two methods of transferring data on the I2C
                                                                            bus, the slave transmit mode and the slave receive
After the SPI interface is enabled by setting the SIMEN                     mode.
bit high, then in the Master Mode, when data is written to                  There are several configuration options associated
the SIMDR register, transmission/reception will begin si-                   with the I2C interface. One of these is to enable the
multaneously. When the data transfer is complete, the                       function which selects the SIM pins rather than normal
TRF flag will be set automatically, but must be cleared                     I/O pins. Note that if the configuration option does not
using the application program. In the Slave Mode, when                      select the SIM function then the SIMEN bit in the
                                                                            SIMCTL0 register will have no effect. A configuration
the clock signal from the master has been received, any
                                                                            option exists to allow a clock other than the system
data in the SIMDR register will be transmitted and any
                                                                            clock to drive the I2C interface. Another configuration
data on the SDI pin will be shifted into the SIMDR regis-                   option determines the debounce time of the I2C inter-
ter. The master should output an SCS signal to enable                       face. This uses the internal clock to in effect add a
the slave device before a clock signal is provided and                      debounce time to the external clock to reduce the pos-
slave data transfers should be enabled/disabled be-                         sibility of glitches on the clock line causing erroneous
fore/after an SCS signal is received.                                       operation. The debounce time, if selected, can be
The SPI will continue to function even after a HALT in-                     chosen to be either 1 or 2 system clocks.
struction has been executed.                                                         SIM                      Function

I2C Interface                                                                 SIM function        SIM interface or I/O pins
     2                                                                        2                   I2C runs without internal clock
The I C interface is used to communicate with external                        I C clock
                                                                                                  Disable/Enable
peripheral devices such as sensors, EEPROM memory
etc. Originally developed by Philips, it is a two line low                                        No debounce, 1 system clock;
                                                                              I2C debounce
                                                                                                  2 system clocks
speed serial interface for synchronous serial data trans-
fer. The advantage of only two lines for communication,                            I2C Interface Configuration Options
relatively simple communication protocol and the ability
                                                                          · I2C Registers
to accommodate multiple devices on the same bus has                         There are three control registers associated with the
made it an extremely popular interface type for many                        I2C bus, SIMCTL0, SIMCTL1 and SIMAR and one
applications.                                                               data register, SIMDR. The SIMDR register, which is
                         S T A R T s ig n a l
                                                                            shown in the above SPI section, is used to store the
                           fro m M a s te r                                 data being transmitted and received on the I2C bus.
                                                                            Before the microcontroller writes data to the I2C bus,
                      S e n d s la v e a d d r e s s                        the actual data to be transmitted must be placed in the
                  a n d R /W b it fr o m M a s te r                         SIMDR register. After the data is received from the I2C
                                                                            bus, the microcontroller can read it from the SIMDR
                         A c k n o w le d g e                               register. Any transmission or reception of data from
                            fr o m s la v e
                                                                            the I2C bus must be made via the SIMDR register.
                                                                            Note that the SIMAR register also has the name
                        S e n d d a ta b y te
                           fro m M a s te r                                 SIMCTL2 which is used by the SPI function. Bits
                                                                            SIMIDLE , SIMEN and bits SIM0~SIM2 in register
                         A c k n o w le d g e                               SIMCTL0 are used by the I2C interface. The SIMCTL0
                            fr o m s la v e                                 register is shown in the above SPI section.

                          S T O P s ig n a l
                           fro m M a s te r




Rev. 1.00                                                            45                                        September 21, 2010
                                                                                                                                                          HT45R52/HT45R54

                                                                                                                                                        D a ta B u s


                                                                             I2C     D a ta R e g is te r        S la v e A d d r e s s R e g is te r
                                                                                      (S IM D R )                           (S IM A R )


                                                                                                                             A d d re s s          A d d re s s M a tc h
                                  H T X B it                                                                              C o m p a ra to r         H A A S B it                  I2C   In te rru p t
                                               D ir e c tio n C o n tr o l

   S C L P in
                                       D a ta in L S B
  S D A P in                                                                       S h ift R e g is te r
                                            D a ta O u t M S B                                                  R e a d /w r ite S la v e
                      M                                                                                                                                 S R W   B it
                          U
                              X         E n a b le /D is a b le A c k n o w le d g e
                                                                                                                8 - b it D a ta C o m p le te           H C F B it
                                                                             T r a n s m it/R e c e iv e
                                                                                   C o n tr o l U n it          D e te c t S ta rt o r S to p
                                                                                                                                                        H B B B it

                                                                                        I2C Block Diagram



  ¨   SIMIDLE                                                                                                         transmitted address and slave address match, that
      The SIMIDLE bit is used to select if the I2C interface                                                          is when the HAAS bit is set high, the device will
      continues running when the device is in the IDLE                                                                check the SRW bit to determine whether it should
      mode. Setting the bit high allows the I2C interface to                                                          be in transmit mode or receive mode. If the SRW bit
      maintain operation when the device is in the Idle                                                               is high, the master is requesting to read data from
      mode. Clearing the bit to zero disables any I2C op-                                                             the bus, so the device should be in transmit mode.
      erations when in the Idle mode.                                                                                 When the SRW bit is zero, the master will write data
      This SPI/I2C idle mode control bit is located at                                                                to the bus, therefore the device should be in receive
      CLKMOD register bit4.                                                                                           mode to read this data.
  ¨   SIMEN                                                                                                       ¨   TXAK
      The SIMEN bit is the overall on/off control for the I2C                                                         The TXAK flag is the transmit acknowledge flag. Af-
      interface. When the SIMEN bit is cleared to zero to                                                             ter the receipt of 8-bits of data, this bit will be trans-
      disable the I2C interface, the SDA and SCL lines will                                                           mitted to the bus on the 9th clock. To continue
      be in a floating condition and the I2C operating cur-                                                           receiving more data, this bit has to be reset to zero
      rent will be reduced to a minimum value. When the                                                               before further data is received.
      bit is high the I2C interface is enabled. The SIMcon-                                                       ¨   HTX
      figuration option must have first enabled the SIMin-                                                            The HTX flag is the transmit/receive mode bit. This
      terface for this bit to be effective. Note that when the                                                        flag should be set high to set the transmit mode and
      SIMEN bit changes from low to high the contents of                                                              low for the receive mode.
      the I2C control registers will be in an unknown con-
                                                                                                                  ¨   HBB
      dition and should therefore be first initialised by the
                                                                                                                      The HBB flag is the I2C busy flag. This flag will be
      application program
                                                                                                                      high when the I2C bus is busy which will occur when
  ¨   SIM0~SIM2                                                                                                       a START signal is detected. The flag will be reset to
      These bits setup the overall operating mode of the                                                              zero when the bus is free which will occur when a
      SIM function. To select the I2C function, bits SIM2~                                                            STOP signal is detected.
      SIM0 should be set to the value 110.
                                                                                                                  ¨   HASS
  ¨   RXAK                                                                                                            The HASS flag is the address match flag. This flag
      The RXAK flag is the receive acknowledge flag.                                                                  is used to determine if the slave device address is
      When the RXAK bit has been reset to zero it means                                                               the same as the master transmit address. If the ad-
      that a correct acknowledge signal has been re-                                                                  dresses match then this bit will be high, if there is no
      ceived at the 9th clock, after 8 bits of data have                                                              match then the flag will be low.
      been transmitted. When in the transmit mode, the
                                                                                                                  ¨   HCF
      transmitter checks the RXAK bit to determine if the
      receiver wishes to receive the next byte. The trans-                                                            The HCF flag is the data transfer flag. This flag will
      mitter will therefore continue sending out data until                                                           be zero when data is being transferred. Upon com-
      the RXAK bit is set high. When this occurs, the                                                                 pletion of an 8-bit data transfer the flag will go high
      transmitter will release the SDA line to allow the                                                              and an interrupt will be generated.
      master to send a STOP signal to release the bus.                                                                The I2C module can run without using internal clock,
                                                                                                                      and generate an interrupt only when an address
  ¨   SRW                                                                                                             match occurs if the SIM interrupt is enabled, which
      The SRW bit is the Slave Read/Write bit. This bit de-                                                           can be used in sleep mode, idle (slow) mode, nor-
      termines whether the master device wishes to                                                                    mal (slow) mode. This bit should be set to high to
      transmit or receive data from the I2C bus. When the                                                             set the I2C running NOT using internal clock and low


Rev. 1.00                                                                                                  46                                                              September 21, 2010
                                                                                                                                     HT45R52/HT45R54

    for I2C running using internal clock. If RNIC is ²1²                                                                               S ta rt
    and MCU is in halt, slave-receiver can work well but
    slave-transmitter doesn¢t work since it needs sys-
    tem clock.                                                                                                                      W r ite S la v e
                                                                                                                              A d d re s s to S IM A R

I2C Control Register - SIMAR
The SIMARregister is also used by the SPI interface but                                                                      S E T S IM [2 :0 ]= 1 1 0
                                                                                                                                  S E T S IM E N
has the name SIMCTL2.
The SIMARregister is the location where the 7-bit slave
                                                                                                            D is a b le               I2C B u s             E n a b le
address of the microcontroller is stored. Bits 1~7 of the                                                                          In te rru p t= ?

SIMAR register define the microcontroller slave ad-                                                  C L R E H I                                                    S E T E H I
dress. Bit 0 is not defined. When a master device, which                                     P o ll H IF to d e c id e
                                                                                       w h e n to g o to I2C B u s IS R                                      W a it fo r In te r r u p t
is connected to the I2C bus, sends out an address,
which matches the slave address in the SIMARregister,
the microcontroller slave device will be selected. Note                                    G o to M a in P r o g r a m                                     G o to M a in P r o g r a m

that the SIMAR register is the same register as
SIMCTL2 which is used by the SPI interface.                                                             I2C Bus Initialisation Flow Chart

I2C Bus Communication                                                            Step 3

Communication on the I2C bus requires four separate                              Set the EHI bit of the interrupt control register to enable
steps, a START signal, a slave device address transmis-                          the I2C bus interrupt.
sion, a data transmission and finally a STOP signal.                             · Start Signal
When a START signal is placed on the I2C bus, all de-                                  The START signal can only be generated by the mas-
vices on the bus will receive this signal and be notified of                           ter device connected to the I2C bus and not by the
the imminent arrival of data on the bus. The first seven                               microcontroller, which is only a slave device. This
bits of the data will be the slave address with the first bit                          START signal will be detected by all devices con-
being the MSB. If the address of the microcontroller                                   nected to the I2C bus. When detected, this indicates
matches that of the transmitted address, the HAAS bit in                               that the I2C bus is busy and therefore the HBB bit will
                                                                                       be set. A START condition occurs when a high to low
the SIMCTL1 register will be set and an I2C interrupt will
                                                                                       transition on the SDA line takes place when the SCL
be generated. After entering the interrupt service rou-
                                                                                       line remains high.
tine, the microcontroller slave device must first check
                                                                                 · Slave Address
the condition of the HAAS bit to determine whether the
                                                                                       The transmission of a START signal by the master will
interrupt source originates from an address match or
                                                                                       be detected by all devices on the I2C bus. To deter-
from the completion of an 8-bit data transfer. During a                                mine which slave device the master wishes to com-
data transfer, note that after the 7-bit slave address has                             municate with, the address of the slave device will be
been transmitted, the following bit, which is the 8th bit, is                          sent out immediately following the START signal. All
the read/write bit whose value will be placed in the SRW                               slave devices, after receiving this 7-bit address data,
bit. This bit will be checked by the microcontroller to de-                            will compare it with their own 7-bit slave address. If the
termine whether to go into transmit or receive mode. Be-                               address sent out by the master matches the internal
fore any transfer of data to or from the I2C bus, the                                  address of the microcontroller slave device, then an
microcontroller must initialise the bus, the following are                             internal I2C bus interrupt signal will be generated. The
                                                                                       next bit following the address, which is the 8th bit, de-
steps to achieve this:
                                                                                       fines the read/write status and will be saved to the
Step 1                                                                                 SRW bit of the SIMCTL1 register. The device will then
                                                                                       transmit an acknowledge bit, which is a low level, as
Write the slave address of the microcontroller to the I2C
                                                                                       the 9th bit. The microcontroller slave device will also
bus address register SIMAR.
                                                                                       set the status flag HAAS when the addresses match.
Step 2                                                                                 As an I2C bus interrupt can come from two sources,
                                                                                       when the program enters the interrupt subroutine, the
Set the SIMEN bit in the SIMCTL0 register to ²1² to en-                                HAAS bit should be examined to see whether the in-
able the I2C bus.                                                                      terrupt source has come from a matching slave ad-
                                                                                       dress or from the completion of a data byte transfer.
                        b 7                                                                    b 0
                      S A 6   S A 5   S A 4       S A 3   S A 2   S A 1        S A 0                        S IM A R      R e g is te r

                                                                                                            N o t im p le m e n te d , r e a d a s " 0 "

                                                                                                            I2C     d e v ic e s la v e a d d r e s s
                                              I C Slave Address Register - SIMAR
                                              2




Rev. 1.00                                                                 47                                                                             September 21, 2010
                                                                                                                                                                                                                HT45R52/HT45R54

                               S ta rt                                                          S la v e A d d r e s s                                                        S R W                A C K
            S C L



                                                             1             0                      1                  1           0                  1           0                      1            0
            S D A




                                                                                                                  D a ta                                                            A C K                       S to p
            S C L



                                               1                     0                  0             1                    0              1             0                 0

            S D A
            S = S          ta rt (1           b it)
             S A =        S la v e         A d d r e s s ( 7 b its )
              S R =         S R W        b it ( 1 b it)
               M = S          la v e d      e v ic e s e n d a c k n o w le d g e b it ( 1 b it)
                D = D        a ta (8           b its )
                 A = A     C K (R         X A K b it fo r tr a n s m itte r , T X A K b it fo r r e c e iv e r 1 b it)
                  P = S     to p (1          b it)

                 S          S A          S R          M          D             A            D             A                          S        S A       S R         M           D             A         D   A                            P

                                                                                   2
                                                                                   I C Communication Timing Diagram




                                                                                                                                         S ta rt




                                                                                            N o                                  H A A S = 1                                               Y e s
                                                                                                                                      ?

                                     N o                             H T X = 1                            Y e s                                                                Y e s               S R W = 1                 N o
                                                                         ?                                                                                                                              ?

                     R e a d fro m                                                                                                                                                                                         C L R H T X
                                                                                                                                                              S E T H T X
                       S IM D R                                                                                                                                                                                           C L R T X A K



                                                                                                                                                               W r ite to                                                D u m m y R e a d
                          R E T I                                                                                                                               S IM D R                                                  F ro m S IM D R

                                                                                       Y e s                  R X A K = 1
                                                                                                                   ?
                                                                                                                                                                        R E T I                                                R E T I
                                                                                                                           N o

                                          C L R H T X                                                         W r ite to
                                         C L R T X A K                                                         S IM D R



                                    D u m m y R e a d
                                                                                                                  R E T I
                                     fro m S IM D R




                                                   R E T I


                                                                                                      I2C Bus ISR Flow Chart




Rev. 1.00                                                                                                                        48                                                                                                September 21, 2010
                                                                                                                           HT45R52/HT45R54

   When a slave address is matched, the device must be                      If the transmitter does not receive an acknowledge bit
   placed in either the transmit mode and then write data                   signal from the receiver, then it will release the SDA
   to the SIMDR register, or in the receive mode where it                   line and the master will send out a STOP signal to re-
   must implement a dummy read from the SIMDR regis-                        lease control of the I2C bus. The corresponding data
   ter to release the SCL line.                                             will be stored in the SIMDR register. If setup as a
· SRW Bit                                                                   transmitter, the microcontroller slave device must first
   The SRW bit in the SIMCTL1 register defines whether                      write the data to be transmitted into the SIMDR regis-
   the microcontroller slave device wishes to read data                     ter. If setup as a receiver, the microcontroller slave de-
   from the I2C bus or write data to the I2C bus. The                       vice must read the transmitted data from the SIMDR
   microcontroller should examine this bit to determine if                  register.
   it is to be a transmitter or a receiver. If the SRW bit is             · Receive Acknowledge Bit
   set to ²1² then this indicates that the master wishes to                 When the receiver wishes to continue to receive the
   re a d da t a f r o m t he I 2 C bus , t her e f o r e t h e             next data byte, it must generate an acknowledge bit,
   microcontroller slave device must be setup to send                       known as TXAK, on the 9th clock. The microcontroller
   data to the I2C bus as a transmitter. If the SRW bit is                  slave device, which is setup as a transmitter will check
   ²0² then this indicates that the master wishes to send                   the RXAK bit in the SIMCTL1 register to determine if it
   data to the I2C bus, therefore the microcontroller slave                 is to send another data byte, if not then it will release
   device must be setup to read data from the I2C bus as                    the SDA line and await the receipt of a STOP signal
   a receiver.                                                              from the master.
· Acknowledge Bit
   After the master has transmitted a calling address,                    Peripheral Clock Output
   any slave device on the I2C bus, whose own internal
   address matches the calling address, must generate                     The Peripheral Clock Output allows the device to supply
   an acknowledge signal. This acknowledge signal will                    external hardware with a clock signal synchronised to
   inform the master that a slave device has accepted its                 the microcontroller clock.
   calling address. If no acknowledge signal is received
   by the master then a STOP signal must be transmitted                   Peripheral Clock Operation
   by the master to end the communication. When the                       As the peripheral clock output pin, PCLK, the required
   HAAS bit is high, the addresses have matched and
                                                                          pin function is chosen via PCKEN in SIMCTL0 register.
   the microcontroller slave device must check the SRW
                                                                          The Peripheral Clock function is controlled using the
   bit to determine if it is to be a transmitter or a receiver.
   If the SRW bit is high, the microcontroller slave device               SIMCTL0 register. The clock source for the Peripheral
   should be setup to be a transmitter so the HTX bit in                  Clock Output can originate from either the Timer/Event
   the SIMCTL1 register should be set to ²1² if the SRW                   Counter 0 divided by two or a divided ratio of the internal
   bit is low then the microcontroller slave device should                fSYS clock. The PCKEN bit in the SIMCTL0 register is the
   be setup as a receiver and the HTX bit in the SIMCTL1                  overall on/off control, setting the bit high enables the Pe-
   register should be set to ²0².                                         ripheral Clock, clearing it disables it. The required divi-
· Data Byte                                                               sion ratio of the system clock is selected using the
   The transmitted data is 8-bits wide and is transmitted                 PCKPSC0 and PCKPSC1 bits in the same register. If
   after the slave device has acknowledged receipt of its                 the system enters the Sleep Mode this will disable the
   slave address. The order of serial bit transmission is                 Peripheral Clock output.
   the MSB first and the LSB last. After receipt of 8-bits of
   data, the receiver must transmit an acknowledge sig-                                            P C K P S C 0    P C K P S C 1   P C K E N
   nal, level ²0², before it can receive the next data byte.

 S C L
                                                                                       fS   Y S              ¸ 1 , 4 , 8                         P C L K
                                                                                                                                                             P C L K
                                                                                                                                                S e le c t
                                                                                    P F D 0
 S D A


                                                                           S le e p M o d e
         S ta r t b it         D a ta       D a ta     S to p b it
                             s ta b le       a llo w
                                         c h a n g e                                              Peripheral Clock Block Diagram
                         Data Timing Diagram




Rev. 1.00                                                            49                                                                September 21, 2010
                                                                                                                                              HT45R52/HT45R54

            b 7                                                                                             b 0
          S IM 2   S IM 1   S IM 0           P C K E N    P C K P S C 1 P C K P S C 0 S IM E N                       S IM C T L 0 R e g is te r

                                                                                                                     N o t im p le m e n t e d , r e a d a s '0 "

                                                                                                                     S P I/I2C O n /O ff c o n tr o l
                                                                                                                      1 : e n a b le
                                                                                                                       0 : d is a b le

                                                                                                                      P C K c lo c k s e le c t
                                                                                                                     P C K P S C 1 P C K P S C 0              C lo c k         S o u rc e
                                                                                                                            0                   0                 fS Y   S
                                                                                                                              0                   1               fS Y   S     /4
                                                                                                                                1                   0             fS Y   S     /8
                                                                                                                                  1                   1           P F        D 0

                                                                                                                     P e r ip h e r a l c lo c k e n a b le
                                                                                                                      1 : c lo c k a n d o u tp u t e n a b le
                                                                                                                       0 : c lo c k a n d o u tp u t d is a b le

                                                                                                                     S P I M a s te r /S la v e a n d c lo c k c o n tr o l
                                                                                                                      - d e s c r ib e d e ls e w h o s e

                                                    Peripheral Clock Output Control - SIMCTL0




Buzzer
Operating in a similar way to the Programmable Fre-                                               LIRC oscillator or the System oscillator/4, the choice of
quency Divider, the Buzzer function provides a means of                                           which is determined by the fS clock source configuration
producing a variable frequency output, suitable for ap-                                           option. Note that the buzzer frequency is controlled by
plications such as Piezo-buzzer driving or other external                                         configuration options, which select both the source
circuits that require a precise frequency generator. The                                          clock for the internal clock fS and the internal division ra-
BZ and BZ pins form a complementary pair, and are                                                 tio. There are no internal registers associated with the
pin-shared with I/O pins, PB0 and PB1. A configuration                                            buzzer frequency.
option is used to select from one of three buzzer options.                                        If the configuration options have selected both pins PB0
The first option is for both pins PB0 and PB1 to be used                                          and PB1 to function as a BZ and BZ complementary pair
as normal I/Os, the second option is for both pins to be
                                                                                                  of buzzer outputs, then for correct buzzer operation it is
configured as BZ and BZ buzzer pins, the third option
                                                                                                  essential that both pins must be setup as outputs by set-
selects only the PB0 pin to be used as a BZ buzzer pin                                            ting bits PBC0 and PBC1 of the PBC port control regis-
with the PB1 pin retaining its normal I/O pin function.                                           ter to zero. The PB0 data bit in the PB data register must
Note that the BZ pin is the inverse of the BZ pin which to-                                       also be set high to enable the buzzer outputs, if set low,
gether generate a differential output which can supply                                            both pins PB0 and PB1 will remain low. In this way the
more power to connected interfaces such as buzzers.                                               single bit PB0 of the PB register can be used as an
The buzzer is driven by the internal clock source, , which                                        on/off control for both the BZ and BZ buzzer pin outputs.
then passes through a divider, the division ratio of which                                        Note that the PB1 data bit in the PB register has no con-
is selected by configuration options to provide a range of                                        trol over the BZ buzzer pin PB1.
buzzer frequencies from fS/22 to fS/29. The clock source
that generates fS, which in turn controls the buzzer fre-
quency, can originate from two different sources, the




                                                      fS S o u rc e                                                          B Z
                             fS   Y S   /4                                 fS      C o n fig u r a tio n O p tio n
                                                   C o n fig u r a tio n
                              L IR C                                                   D iv id e b y 2 2 ~ 2 9
                                                        O p tio n                                                            B Z


                                                                                Buzzer Function




Rev. 1.00                                                                                 50                                                                       September 21, 2010
                                                                                                      HT45R52/HT45R54

PB0/PB1 Pin Function Control

     PBC Register                        PBC Register          PB Data Register        PB Data Register               Output
        PBC0                                PBC1                    PB0                     PB1                      Function
                                                                                                                      PB0=BZ
             0                                         0              1                         x
                                                                                                                      PB1=BZ
                                                                                                                     PB0=²0²
             0                                         0              0                         x
                                                                                                                     PB1=²0²
                                                                                                                    PB0=BZ
             0                                         1              1                         x
                                                                                                                  PB1=input line
                                                                                                                    PB0=²0²
             0                                         1              0                         x
                                                                                                                  PB1=input line
                                                                                                                  PB0=input line
             1                                         0               x                        D
                                                                                                                     PB1=D
                                                                                                                  PB0=input line
             1                                         1               x                        x
                                                                                                                  PB1=input line

²x² stands for don¢t care
²D² stands for Data ²0² or ²1²



If configuration options have selected that only the PB0                   Note that no matter what configuration option is chosen
pin is to function as a BZ buzzer pin, then the PB1 pin                    for the buzzer, if the port control register has setup the
can be used as a normal I/O pin. For the PB0 pin to func-                  pin to function as an input, then this will override the con-
tion as a BZ buzzer pin, PB0 must be setup as an output                    figuration option selection and force the pin to always
by setting bit PBC0 of the PBC port control register to                    behave as an input pin. This arrangement enables the
zero. The PB0 data bit in the PB data register must also                   pin to be used as both a buzzer pin and as an input pin,
be set high to enable the buzzer output, if set low pin                    so regardless of the configuration option chosen; the ac-
PB0 will remain low. In this way the PB0 bit can be used                   tual function of the pin can be changed dynamically by
as an on/off control for the BZ buzzer pin PB0. If the                     the application program by programming the appropri-
PBC0 bit of the PBC port control register is set high,                     ate port control register bit.
then pin PB0 can still be used as an input even though
the configuration option has configured it as a BZ buzzer
output.



                  In te r n a l C lo c k S o u r c e



                                     P B 0 D a ta



                        B Z O u tp u t a t P B 0



                                     P B 1 D a ta



                        B Z O u tp u t a t P B 1


                                                           Buzzer Output Pin Control

Note:    The above drawing shows the situation where both pins PB0 and PB1 are selected by configuration option to
         be BZ and BZ buzzer pin outputs. The Port Control Register of both pins must have already been setup as out-
         put. The data setup on pin PB1 has no effect on the buzzer outputs.




Rev. 1.00                                                             51                                         September 21, 2010
                                                                                                HT45R52/HT45R54

Interrupts
Interrupts are an important part of any microcontroller             immediately serviced, the request flag will still be re-
system. When an external event or an internal function              corded. If an interrupt requires immediate servicing
such as a Timer/Event Counter or an A/D converter re-               while the program is already in another interrupt service
quires microcontroller attention, their corresponding in-           routine, the EMI bit should be set after entering the rou-
terrupt will enforce a temporary suspension of the main             tine, to allow interrupt nesting. If the stack is full, the in-
program allowing the microcontroller to direct attention            terrupt request will not be acknowledged, even if the
to their respective needs. The device contains several              related interrupt is enabled, until the Stack Pointer is
external interrupt and internal interrupts functions. The           decremented. If immediate service is desired, the stack
external interrupts are controlled by the action of the ex-         must be prevented from becoming full.
ternal INT0 and INT1 pins, while the internal interrupts
are controlled by the Timer/Event Counter overflows,                Interrupt Priority
the Time Base interrupt, the RTC interrupt, the SPI/I2C             Interrupts, occurring in the interval between the rising
interrupt and the the A/D converter interrupt.                      edges of two consecutive T2 pulses, will be serviced on
                                                                    the latter of the two T2 pulses, if the corresponding inter-
Interrupt Registers                                                 rupts are enabled. In case of simultaneous requests,
Overall interrupt control, which means interrupt enabling           the following table shows the priority that is applied.
and request flag setting, is controlled by the INTC0,
INTC1 and MFIC registers, which are located in the                            Interrupt Source               Priority    Vector
Data Memory. By controlling the appropriate enable bits              External Interrupt 0                        1         04H
in these registers each individual interrupt can be en-              External Interrupt 1                        2         08H
abled or disabled. Also when an interrupt occurs, the                Timer/Event Counter 0 Overflow              3        0CH
corresponding request flag will be set by the
                                                                     A/D Converter Interrupt                     4         10H
microcontroller. The global enable flag if cleared to zero                2
will disable all interrupts.                                         SPI/I C Interrupt                           5         14H
                                                                     Multi-function Interrupt                    6         18H
Interrupt Operation
                                                                    The RTC interrupt, Time Base interrupt and Timer/Event
A Timer/Event Counter overflow, Time Base, RTC over-
                                                                    Counter 1 interrupt all share the same interrupt vector
flow, SPI/I2C data transfer complete, an end of A/D con-
                                                                    which is 18H. Each of these interrupts have their own
version or the external interrupt line being triggered will
                                                                    own individual interrupt flag but also share the same
all generate an interrupt request by setting their corre-
                                                                    MFF interrupt flag. The MFF flag will be cleared by hard-
sponding request flag. When this happens and if their
                                                                    ware once the Multi-function interrupt is serviced, how-
appropriate interrupt enable bit is set, the Program
                                                                    ever the individual interrupts that have triggered the
Counter, which stores the address of the next instruction
                                                                    Multi-function interrupt need to be cleared by the appli-
to be executed, will be transferred onto the stack. The
                                                                    cation program.
Program Counter will then be loaded with a new ad-
dress which will be the value of the corresponding inter-           External Interrupt
rupt vector. The microcontroller will then fetch its next
                                                                    For an external interrupt to occur, the global interrupt
instruction from this interrupt vector. The instruction at
                                                                    enable bit, EMI, and external interrupt enable bits, EEI0
this vector will usually be a JMP statement which will
                                                                    and EEI1, must first be set. Additionally the correct
jump to another section of program which is known as
                                                                    interrupt edge type must be selected using the
the interrupt service routine. Here is located the code to
                                                                    INTEDGE register to enable the external interrupt
control the appropriate interrupt. The interrupt service
                                                                    function and to choose the trigger edge type. An actual
routine must be terminated with a RETI statement,
                                                                    external interrupt will take place when the external
which retrieves the original Program Counter address
                                                                    interrupt request flag, EIF0 or EIF1, is set, a situation
from the stack and allows the microcontroller to continue
                                                                    that will occur when a transition, whose type is chosen
with normal execution at the point where the interrupt
                                                                    by the edge select bit, appears on the INT0 or INT1 pin.
occurred.
                                                                    The external interrupt pins are pin-shared with the I/O
The various interrupt enable bits, together with their as-          pins PA0 and PA1 and can only be configured as
sociated request flags, are shown in the accompanying               external interrupt pins if their corresponding external
diagram with their order of priority.                               interrupt enable bit in the INTC0 register has been set.
Once an interrupt subroutine is serviced, all the other in-         The pin must also be setup as an input by setting the
terrupts will be blocked, as the EMI bit will be cleared au-        corresponding PAC.0 and PAC.1 bits in the port control
tomatically. This will prevent any further interrupt nesting        register. When the interrupt is enabled, the stack is not
from occurring. However, if other interrupt requests oc-            full and the correct transition type appears on the
cur during this interval, although the interrupt will not be        external interrupt pin, a subroutine call to the external


Rev. 1.00                                                      52                                          September 21, 2010
                                                                                                                                                          HT45R52/HT45R54

                  b 7                                                                         b 0
                           T 0 F      E IF 1      E IF 0   E T 0 I E E I1   E E I0           E M I      IN T C 0 R e g is te


                                                                                                        M a s te r in te r r u p t g lo b a l e n a b le
                                                                                                         1 : g lo b a l e n a b le
                                                                                                          0 : g lo b a l d is a b le

                                                                                                        E x te r n a l in te r r u p t 0 e n a b le
                                                                                                         1 : e n a b le
                                                                                                          0 : d is a b le

                                                                                                        E x te r n a l in te r r u p t 1 e n a b le
                                                                                                         1 : e n a b le
                                                                                                          0 : d is a b le

                                                                                                        T im e r /E v e n t C o u n te r 0 in te r r u p t e n a b le
                                                                                                         1 : e n a b le
                                                                                                          0 : d is a b le

                                                                                                        E x te r n a l in te r r u p t 0 r e q u e s t fla g
                                                                                                         1 : a c tiv e
                                                                                                          0 : in a c tiv e

                                                                                                        E x te r n a l in te r r u p t 1 r e q u e s t fla g
                                                                                                         1 : a c tiv e
                                                                                                          0 : in a c tiv e

                                                                                                        T im e r /E v e n t C o u n te r 0 in te r r u p t r e q u e s t fla g
                                                                                                         1 : a c tiv e
                                                                                                          0 : in a c tiv e

                                                                                                        N o t im p le m e n te d , r e a d a s " 0 "

                                                            Interrupt Control Register - INTC0




            b 7                                                                        b 0
                        M F F      S IM F      A D F            E M F I E S IM       E A D I         IN T C 1 R e g is te r

                                                                                                     A /D c o n v e r te r in te r r u p t e n a b le
                                                                                                      1 : e n a b le
                                                                                                       0 : d is a b le

                                                                                                     S P I/I2 C in te r r u p t e n a b le
                                                                                                      1 : e n a b le
                                                                                                       0 : d is a b le

                                                                                                     M u lti- fu n c tio n in te r r u p t e n a b le
                                                                                                      1 : e n a b le
                                                                                                       0 : d is a b le

                                                                                                     N o t im p le m e n te d , r e a d a s " 0 "

                                                                                                     A /D c o n v e r te r in te r r u p t r e q u e s t fla g
                                                                                                      1 : a c tiv e
                                                                                                       0 : in a c tiv e

                                                                                                     S P I/I2 C in te r r u p t r e q u e s t fla g
                                                                                                      1 : a c tiv e
                                                                                                       0 : in a c tiv e

                                                                                                       M u lti- fu n c tio n in te r r u p t r e q u e s t fla g
                                                                                                     1 : a c tiv e
                                                                                                      0 : in a c tiv e

                                                                                                     N o t im p le m e n te d , r e a d a s " 0 "

                                                            Interrupt Control Register - INTC1




Rev. 1.00                                                                                      53                                                                       September 21, 2010
                                                                                                                                             HT45R52/HT45R54

                  b 7                                                                b 0
                                    R T F       T B F                 E R T I E T B I               M F IC    R e g is te r

                                                                                                    T im e B a s e in te r r u p t e n a b le
                                                                                                     1 : e n a b le
                                                                                                      0 : d is a b le

                                                                                                    R e a l T im e C lo c k in te r r u p t e n a b le
                                                                                                     1 : e n a b le
                                                                                                      0 : d is a b le

                                                                                                    N o t im p le m e n te d , r e a d a s " 0 "

                                                                                                    T im e B a s e in te r r u p t r e q u e s t fla g
                                                                                                     1 : a c tiv e
                                                                                                      0 : in a c tiv e

                                                                                                      R e a l T im e C lo c k in te r r u p t r e q u e s t fla g
                                                                                                    1 : a c tiv e
                                                                                                     0 : in a c tiv e

                                                                                                    N o t im p le m e n te d , r e a d a s " 0 "

                                               HT45R52 Interrupt Control Register - MFIC




            b 7                                                           b 0
                    T 1 F   R T F      T B F            E T 1 I E R T I E T B I            M F IC     R e g is te r

                                                                                           T im e B a s e in te r r u p t e n a b le
                                                                                            1 : e n a b le
                                                                                             0 : d is a b le

                                                                                           R e a l T im e C lo c k in te r r u p t e n a b le
                                                                                            1 : e n a b le
                                                                                             0 : d is a b le

                                                                                           T im e r /E v e n t C o u n te r 1 in te r r u p t e n a b le
                                                                                            1 : e n a b le
                                                                                             0 : d is a b le

                                                                                           N o t im p le m e n te d , r e a d a s " 0 "
                                                                                           T im e B a s e in te r r u p t r e q u e s t fla g
                                                                                            1 : a c tiv e
                                                                                             0 : in a c tiv e

                                                                                           R e a l T im e C lo c k in te r r u p t r e q u e s t fla g
                                                                                            1 : a c tiv e
                                                                                             0 : in a c tiv e

                                                                                           T im e r /E v e n t C o u n te r 1 in te r r u p t r e q u e s t fla g
                                                                                            1 : a c tiv e
                                                                                             0 : in a c tiv e

                                                                                           N o t im p le m e n te d , r e a d a s " 0 "

                                               HT45R54 Interrupt Control Register - MFIC




Rev. 1.00                                                                       54                                                                             September 21, 2010
                                                                                                                                                   HT45R52/HT45R54

                    A u to m a tic a lly C le a r e d b y IS R      e x c e p t
                                 fo r T B F , R T F a n d T 1 F                              A u to m a tic a lly D is a b le d b y IS R
                      M a n u a lly S e t o r C le a r e d b y S o ftw a r e                     C a n b e E n a b le d M a n u a lly


                                                                                                                                       P r io r ity
                                     E x te rn a l In te rru p t                  E E I0                   E M I                          H ig h
                                    R e q u e s t F la g E IF 0


                                     E x te rn a l In te rru p t                  E E I1
                                    R e q u e s t F la g E IF 1

                                 T im e r /E v e n t C o u n te r 0               E T 0 I
                             In te r r u p t R e q u e s t F la g T 0 F
                                                                                                                                                                 In te rru p t
                                                                                                                                                                   P o llin g
                                          A /D C o n v e rte r                    E A D I
                             In te r r u p t R e q u e s t F la g A D F

                                              S P I/I2C                           E S IM
                            In te r r u p t R e q u e s t F la g S IM F


                                          M u lti- fu n c tio n                   E M F I
                             In te r r u p t R e q u e s t F la g M F F                                                                   L o w




                                  T im e r /E v e n t C o u n te r 1              E T 1 I
                              In te r r u p t R e q u e s t F la g T 1 F

                  H T 4 5 R 5 4 o n ly

                                        R e a l T im e C lo c k                   E R T I
                             In te r r u p t R e q u e s t F la g R T F


                                            T im e B a s e                        E T B I
                             In te r r u p t R e q u e s t F la g T B F

                                                                           Interrupt Structure




            b 7                                                                                  b 0
                                                     IN T 1 S 1 IN T 1 S 0 IN T 0 S 1 IN T 0 S 0         IN T E D G E R e g is te r

                                                                                                         IN T 0 E d g e S e   le c t
                                                                                                         IN T 0 S 1      IN   T 0 S 0
                                                                                                              0                 0                  d is a b le
                                                                                                                0                 1                 r is in g e d g e tr ig g e r
                                                                                                                  1                 0                fa llin g e d g e tr ig g e r
                                                                                                                    1                 1              d u a l e d g e tr ig g e r
                                                                                                         IN T 1 E D g e S e le c t
                                                                                                         IN T 1 S 1     IN T 1 S 0
                                                                                                              0              0                     d is a b le
                                                                                                                0              1                    r is in g e d g e tr ig g e r
                                                                                                                  1              0                   fa llin g e d g e tr ig g e r
                                                                                                                    1              1                 d u a l e d g e tr ig g e r
                                                                                                         N o t im p le m e n te d , r e a d a s " 0 "

                                                     Interrupt Active Edge Register - INTEDGE




Rev. 1.00                                                                                   55                                                                      September 21, 2010
                                                                                                            HT45R52/HT45R54

interrupt vector at location 04H or 08H, will take place.                        Timer Event Counter 0 have its own individual interrupt
When the interrupt is serviced, the external interrupt                           vectors, however the interrupt vector for Timer/Event
request flags, EIF0 or EIF1, will be automatically reset                         Counter 1 is contained within the Multi-function Inter-
and the EMI bit will be automatically cleared to disable                         rupt. For a Timer/Event Counter 1 interrupt to occur, the
other interrupts. Note that any pull-high resistor                               global interrupt enable bit, EMI, Timer/Event Counter 1
selections on this pin will remain valid even if the pin is                      interrupt enable bit, ET1I, and Multi-function interrupt
used as an external interrupt input.                                             enable bit, EMFI, must first be set. An actual external
                                                                                 peripheral interrupt will take place when the Timer/Event
The INTEDGE register is used to select the type of active
                                                                                 Counter 1 request flag, T1F, is set, a situation that will
edge that will trigger the external interrupt. A choice of ei-
                                                                                 occur when the Timer/Event Counter 1 overflows. When
ther rising and falling edge types can be chosen along
                                                                                 the interrupt is enabled, the stack is not full and the
with an option to allow both edge types to trigger an exter-
                                                                                 Timer/Event Counter 1 overflows, a subroutine call to
nal interrupt. Note that the INTEDGE register can also be
                                                                                 the Multi-function interrupt vector at location 18H, will
used to disable the external interrupt function.
                                                                                 take place. When the Timer/Event 1 interrupt is ser-
                       F ilte r O n /O ff                        M C U           viced, the EMI bit will be cleared to disable other inter-
                        C o n fig u r a tio n O p tio n
                                                                                 rupts, however only the MFF interrupt request flag will
                                                                                 be reset. As the T1F flag will not be automatically reset,
            IN T C 0         F ilte r               E x te rn a l IN T .0
                                                                                 it has to be cleared by the application program.
            IN T C 1         F ilte r               E x te rn a l IN T .1
                                                                                 A/D Interrupt
                                                                                 For an A/D interrupt to occur, the global interrupt enable
The external interrupt pins are connected to an internal                         bit, EMI, and the corresponding interrupt enable bit,
filter to reduce the possibility of unwanted external inter-                     EADI must be first set. An actual A/D interrupt will take
rupts due to adverse noise or spikes on the external in-                         place when the A/D interrupt request flag, ADF, is set, a
terrupt input signal. As this internal filter circuit will                       situation that will occur when the A/D conversion pro-
consume a limited amount of power, a configuration op-                           cess has finished. When the interrupt is enabled, the
tion is provided to switch off the filter function, an option                    stack is not full and the A/D conversion process has
which may be beneficial in power sensitive applications,                         ended, a subroutine call to the A/D interrupt vector at lo-
but in which the integrity of the input signal is high. Care                     cation 10H, will take place. When the interrupt is ser-
must be taken when using the filter on/off configuration                         viced, the ADC request flag, ADF will be automatically
option as it will be applied not only to both the external                       reset and the EMI bit will be automatically cleared to dis-
interrupt pins but also to the Timer/Event Counter exter-                        able other interrupts.
nal input pins. Individual external interrupt or
Timer/Event Counter pins cannot be selected to have a                            SPI/I2C Interface Interrupt
filter on/off function.                                                          For an /I2C interrupt to occur, the global interrupt enable
                                                                                 bit, EMI, and the corresponding interrupt enable bit,
Timer/Event Counter Interrupt                                                    ESIM must be first set. An actual SPI/I2C interrupt will
For a Timer/Event Counter 0 interrupt to occur, the                              take place when the SPlcd reset function interface re-
global interrupt enable bit, EMI, and the corresponding                          quest flag, SIMF, is set, a situation that will occur when a
timer interrupt enable bit, ET0I must first be set. An ac-                       byte of data has been transmitted or received by the
tual Timer/Event Counter interrupt will take place when                          SPI/I2C interface or when an I2C address match occurs.
the Timer/Event Counter request flag, T0F is set, a situ-                        When the interrupt is enabled, the stack is not full and a
ation that will occur when the Timer/Event Counter over-                         byte of data has been transmitted or received by the
flows. When the interrupt is enabled, the stack is not full                      SPI/I2C interface or an I2C address match occurs, a sub-
and a Timer/Event Counter overflow occurs, a subrou-                             routine call to the SPI/I2C interrupt vector at location
tine call to the timer interrupt vector at location 0CH, will                    14H, will take place. When the interrupt is serviced, the
take place. When the interrupt is serviced, the timer in-                        SPI/I2C request flag, SIMF will be automatically reset
terrupt request flag, T0F, will be automatically reset and                       and the EMI bit will be automatically cleared to disable
the EMI bit will be automatically cleared to disable other                       other interrupts.
interrupts.




Rev. 1.00                                                                   56                                        September 21, 2010
                                                                                                                                                                                      HT45R52/HT45R54

Multi-function Interrupt                                                                              time clock, because the RTC interrupt clock source is
An additional interrupt known as the Multi-function inter-                                            from the internal LIRC OSC.
rupt is provided. Unlike the other interrupts, this interrupt                                         For a RTC interrupt to be generated, the global interrupt
has no independent source, but rather is formed from                                                  enable bit, EMI, RTC interrupt enable bit, ERTI, and
three other existing interrupt sources, namely the Time                                               Multi-function interrupt enable bit, EMFI, must first be
Base interrupt, RTC interrupt and the Timer 1 overflow                                                set. An actual RTC interrupt will take place when the
interrupt.                                                                                            RTC interrupt request flag, RTF, is set. When the inter-
For a Multi-function interrupt to occur, the global interrupt                                         rupt is enabled, the stack is not full and the RTC inter-
enable bit, EMI, and the Multi-function interrupt enable                                              rupt request flag is set, a subroutine call to the
bit, EMFI, must first be set. An actual Multi-function inter-                                         Multi-function interrupt vector at location18H, will take
rupt will take place when the Multi-function interrupt re-                                            place. When the RTC interrupt is serviced, the EMI bit
quest flag, MFF, is set. When the interrupt is enabled and                                            will be cleared to disable other interrupts, however only
the stack is not full, and either one of the interrupts con-                                          the MFF interrupt request flag will be reset. As the RTF
tained within the Multi-function interrupt occurs, a subrou-                                          flag will not be automatically reset, it has to be cleared
tine call to the Multi-function interrupt vector at location                                          by the application program.
018H will take place. When the interrupt is serviced, the                                             Similar in operation to the Time Base interrupt, the pur-
Multi-Function request flag, MFF, will be automatically re-                                           pose of the RTC interrupt is also to provide an interrupt
set and the EMI bit will be automatically cleared to disable                                          signal at fixed time periods. The RTC interrupt clock
other interrupts. However, it must be noted that the re-                                              source originates from the internal clock source fS. This
quest flags from the original source of the Multi-function                                            fS input clock first passes through a divider, the division
interrupt, namely the Time-Base interrupt, RTC interrupt                                              ratio of which is selected by programming the appropri-
or Timer 1 overflow interrupt will not be automatically re-                                           ate bits in the RTCC register to obtain longer RTC inter-
set and must be manually reset by the application pro-                                                rupt periods whose value ranges from 28/fS~215/fS. The
gram.                                                                                                 clock source that generates fS, which in turn controls the
                                                                                                      RTC interrupt period, can originate from two different
RTC Interrupt                                                                                         sources, the LIRC oscillator or the System oscillator/4,
The RTC interrupt is contained within the Multi-function                                              the choice of which is determine by the fS clock source
interrupt. The RTC interrupt can not be used as the real                                              configuration option.




                                         fS   Y S   /4      fS S o u rc e                             D iv id e b y 2 8 ~ 2                    1 5
                                                                                         fS                                                                                   R T C In te rru p t
                                                         C o n fig u r a tio n                          S e t b y R T C C
                          L IR C   O s c illa to r                                                                                                                             2 12/fS ~ 2 15/fS
                                                              O p tio n                                     R e g is te r


                                                                                                      R T 2       R T 1           R T 0
                                                                                 RTC Interrupt


                    b 7                                                                                         b 0
                                        L V D O                L V D C           R T 2        R T 1           R T 0       R T C C                        R e g is te r

                                                                                                                           R T C                     In te r r u p t P e r io d
                                                                                                                          R T 2                         R T 1              R T 0               P e                       r io d
                                                                                                                             0                             0                 0                  2 8                      /fS
                                                                                                                               0                             0                 1                 2 9                     /fS
                                                                                                                                 0                             1                 0                2 1        0
                                                                                                                                                                                                                           /fS
                                                                                                                                   0                             1                 1               2 1         1
                                                                                                                                                                                                                           /fS
                                                                                                                                     1                             0                 0              2 1          2
                                                                                                                                                                                                                           /fS
                                                                                                                                       1                             0                 1             2 1           3
                                                                                                                                                                                                                           /fS
                                                                                                                                         1                             1                 0            2 1            4
                                                                                                                                                                                                                           /fS
                                                                                                                                           1                             1                 1           2 1             5
                                                                                                                                                                                                                           /fS
                                                                                                                          L o w V o lta g e D e te c to r C o n tr o l
                                                                                                                           1 : e n a b le
                                                                                                                            0 : d is a b le

                                                                                                                          N o t im p le m e n te d , r e a d a s " 0 "

                                                                                                                          L o w V o lta g e D e te c to r O u tp u t
                                                                                                                           1 : lo w v o lta g e d e te c te d
                                                                                                                            0 : n o r m a l v o lta g e

                                                                                                                          N o t im p le m e n te d , r e a d a s " 0 "

                                                             RTC Control Register - RTCC


Rev. 1.00                                                                                     57                                                                                                                        September 21, 2010
                                                                                                                               HT45R52/HT45R54

Note that the RTC interrupt period is controlled by both                                    Essentially operating as a programmable timer, when
configuration options and an internal register RTCC. A                                      the Time Base overflows it will set a Time Base interrupt
configuration option selects the source clock for the in-                                   flag which will in turn generate an Interrupt request via
ternal clock fS, and the RTCC register bits RT2, RT1 and                                    the Multi-function Interrupt vector.
RT0 select the division ratio. Note that the actual divi-
sion ratio can be programmed from 28 to 215.                                                Programming Considerations
                                                                                            By disabling the interrupt enable bits, a requested inter-
Time Base Interrupt
                                                                                            rupt can be prevented from being serviced, however,
The Time Base Interrupt is contained within the                                             once an interrupt request flag is set, it will remain in this
Multi-function Interrupt.                                                                   condition in the INTC0, INTC1 and MFIC registers until
For a Time Base Interrupt to be generated, the global in-                                   the corresponding interrupt is serviced or until the re-
terrupt enable bit, EMI,Time Base Interrupt enable bit,                                     quest flag is cleared by the application program.
ETBI, and Multi-function interrupt enable bit, EMFI,                                        It is recommended that programs do not use the ²CALL
must first be set. An actual Time Base Interrupt will take                                  subroutine² instruction within the interrupt subroutine.
place when the Time Base Interrupt request flag, TBF, is                                    Interrupts often occur in an unpredictable manner or
set, a situation that will occur when the Time Base over-                                   need to be serviced immediately in some applications. If
flows. When the interrupt is enabled, the stack is not full                                 only one stack is left and the interrupt is not well con-
and the Time Base overflows, a subroutine call to the                                       trolled, the original control sequence will be damaged
Multi-function interrupt vector at location18H, will take                                   once a ²CALL subroutine² is executed in the interrupt
place. When the Time Base Interrupt is serviced, the                                        subroutine.
EMI bit will be cleared to disable other interrupts, how-
                                                                                            All of these interrupts have the capability of waking up
ever only the MFF interrupt request flag will be reset. As
                                                                                            the processor when in the Power Down Mode.
the TBF flag will not be automatically reset, it has to be
cleared by the application program.                                                         Only the Program Counter is pushed onto the stack. If
                                                                                            the contents of the status or other registers are altered
The purpose of the Time Base function is to provide an
                                                                                            by the interrupt service program, which may corrupt the
interrupt signal at fixed time periods. The Time Base in-
                                                                                            desired control sequence, then the contents should be
terrupt clock source originates from the Time Base inter-
                                                                                            saved in advance.
rupt clock source originates from the internal clock
source fS. This fS input clock first passes through a di-
vider, the division ratio of which is selected by configura-
tion options to provide longer Time Base interrupt
periods. The Time Base interrupt time-out period ranges
from 212/fS~215/fS. The clock source that generates fS,
which in turn controls the Time Base interrupt period,
can originate from two different sources, the LIRC inter-
nal oscillator or the System oscillator/4, the choice of
which is determine by the fS clock source configuration
option.




                                  fS   Y S   /4      fS S o u rc e
                                                                            fS   C o n fig u r a tio n O p tio n   T im e B a s e In te r r u p t
                                                  C o n fig u r a tio n
                   L IR C   O s c illa to r                                         D iv id e b y 2 1 2 ~ 2 1 5     2 12/fS ~ 2 15/fS
                                                       O p tio n

                                                                          Time Base Interrupt




Rev. 1.00                                                                           58                                                          September 21, 2010
                                                                                                                  HT45R52/HT45R54

Reset and Initialisation                                             inhibited. After the RES line reaches a certain voltage
A reset function is a fundamental part of any                        value, the reset delay time tRSTD is invoked to provide
                                                                     an extra delay time after which the microcontroller will
microcontroller ensuring that the device can be set to
                                                                     begin normal operation. The abbreviation SST in the
some predetermined condition irrespective of outside
                                                                     figures stands for System Start-up Timer.
parameters. The most important reset condition is after
power is first applied to the microcontroller. In this case,                       V D D
                                                                                                                                           0 .9 V      D D
internal circuitry will ensure that the microcontroller, af-                        R E S
ter a short delay, will be in a well defined state and ready                                                                                  tR   S T D

to execute the first program instruction. After this                  S S T T im e - o u t
power-on reset, certain important internal registers will
                                                                          C h ip R e s e t
be set to defined states before the program com-
mences. One of these registers is the Program Counter,                                Power-On Reset Timing Chart
which will be reset to zero forcing the microcontroller to
                                                                     For most applications a resistor connected between
begin program execution from the lowest Program
                                                                     VDD and the RES pin and a capacitor connected be-
Memory address.                                                      tween VSS and the RES pin will provide a suitable ex-
In addition to the power-on reset, situations may arise              ternal reset circuit. Any wiring connected to the RES
where it is necessary to forcefully apply a reset condition          pin should be kept as short as possible to minimise
when the microcontroller is running. One example of this             any stray noise interference.
                                                                     For applications that operate within an environment
is where after power has been applied and the
                                                                     where more noise is present the Enhanced Reset Cir-
microcontroller is already running, the RES line is force-
                                                                     cuit shown is recommended.
fully pulled low. In such a case, known as a normal oper-
                                                                                                            V   D D
ation reset, some of the microcontroller registers remain
                                                                                      0 .0 1 m F * *
unchanged allowing the microcontroller to proceed with                                                                                     V D D
normal operation after the reset line is allowed to return
high. Another type of reset is when the Watchdog Timer                      1 N 4 1 4 8 *
                                                                                                                      1 0 k W ~
overflows and resets the microcontroller. All types of re-                                                             1 0 0 k W
set operations result in different register conditions be-
ing setup.                                                                                                                                 P D 0 /R E S
                                                                                                                            3 0 0 W *
Another reset exists in the form of a Low Voltage Reset,                                     0 .1 ~ 1 m F
LVR, where a full reset, similar to the RES reset is imple-
mented in situations where the power supply voltage                                                                                        V S S
falls below a certain threshold.
                                                                    Note:       ²*² It is recommended that this component is
Reset Functions                                                                 added for added ESD protection
There are five ways in which a microcontroller reset can                        ²**² It is recommended that this component is
occur, through events occurring both internally and ex-                         added in environments where power line noise
ternally:                                                                       is significant
· Power-on Reset                                                                                External RES Circuit
  The most fundamental and unavoidable reset is the
  one that occurs after power is first applied to the                More information regarding external reset circuits is
  microcontroller. As well as ensuring that the Program              located in Application Note HA0075E on the Holtek
  Memory begins execution from the first memory ad-                  website.
  dress, a power-on reset also ensures that certain
                                                                    · RES Pin Reset
  other registers are preset to known conditions. All the
                                                                     This type of reset occurs when the microcontroller is
  I/O port and port control registers will power up in a
                                                                     already running and the RES pin is forcefully pulled
  high condition ensuring that all pins will be first set to
                                                                     low by external hardware such as an external switch.
  inputs.
                                                                     In this case as in the case of other reset, the Program
  Although the microcontroller has an internal RC reset
                                                                     Counter will reset to zero and program execution initi-
  function, if the VDD power supply rise time is not fast
                                                                     ated from this point.
  enough or does not stabilise quickly at power-on, the
  internal reset function may be incapable of providing                                                                                    0 .9 V          D D
                                                                                  R E S                 0 .4 V        D D
  proper reset operation. For this reason it is recom-
  mended that an external RC network is connected to                                                                                          tR    S T D

  the RES pin, whose additional time delay will ensure              S S T T im e - o u t
  that the RES pin remains low for an extended period
  to allow the power supply to stabilise. During this time              C h ip R e s e t
  delay, normal operation of the microcontroller will be                                     RES Reset Timing Chart


Rev. 1.00                                                      59                                                                       September 21, 2010
                                                                                               HT45R52/HT45R54

· Low Voltage Reset - LVR                                            Reset Initial Conditions
 The microcontroller contains a low voltage reset circuit
                                                                     The different types of reset described affect the reset
 in order to monitor the supply voltage of the device,
                                                                     flags in different ways. These flags, known as PDF and
 which is selected via a configuration option. If the supply
 voltage of the device drops to within a range of                    TO are located in the status register and are controlled
 0.9V~VLVR such as might occur when changing the bat-                by various microcontroller operations, such as the
 tery, the LVR will automatically reset the device inter-            Power Down function or Watchdog Timer. The reset
 nally. The LVR includes the following specifications: For           flags are shown in the table:
 a valid LVR signal, a low voltage, i.e., a voltage in the
 range between 0.9V~VLVR must exist for greater than the              TO PDF                 RESET Conditions
 value tLVR specified in the A.C. characteristics. If the low          0     0     RES reset during power-on
 voltage state does not exceed 1ms, the LVR will ignore it
 and will not perform a reset function. One of a range of              u     u     RES or LVR reset during normal operation
 specified voltage values for VLVR can be selected using               1     u     WDT time-out reset during normal operation
 configuration options. The VLVR value will be selected as
 a pair in conjunction with a Low Voltage Detect value.                1     1     WDT time-out reset during Power Down

               L V R                                                 Note: ²u² stands for unchanged
                              tR        S T D
 S S T T im e - o u t                                                The following table indicates the way in which the vari-
                                                                     ous components of the microcontroller are affected after
     C h ip R e s e t                                                a power-on reset occurs.
                Low Voltage Reset Timing Chart                                Item               Condition After RESET
                                                                      Program Counter         Reset to zero
· Watchdog Time-out Reset during Normal Operation
 The Watchdog time-out Reset during normal opera-                     Interrupts              All interrupts will be disabled
 tion is the same as a hardware RES pin reset except                                          Clear after reset, WDT begins
 that the Watchdog time-out flag TO will be set to ²1².               WDT
                                                                                              counting
 W D T T im e - o u t                                                 Timer/Event Counter Timer Counter will be turned off
                             tR        S T D
                                                                                              The Timer Counter Prescaler
  S S T T im e - o u t                                                Prescaler
                                                                                              will be cleared
      C h ip R e s e t                                                Input/Output Ports      I/O ports will be setup as inputs
  WDT Time-out Reset during Normal Operation                                                  Stack Pointer will point to the
                                                                      Stack Pointer
                Timing Chart                                                                  top of the stack

· Watchdog Time-out Reset during Power Down
 The Watchdog time-out Reset during Power Down is
 a little different from other kinds of reset. Most of the
 conditions remain unchanged except that the Pro-
 gram Counter and the Stack Pointer will be cleared to
 ²0² and the TO flag will be set to ²1². Refer to the A.C.
 Characteristics for tSST details.

 W D T T im e - o u t
                                  tS    S T

  S S T T im e - o u t

        WDT Time-out Reset during Power Down
                    Timing Chart




Rev. 1.00                                                       60                                        September 21, 2010
                                                                                           HT45R52/HT45R54

The different kinds of resets all affect the internal registers of the microcontroller in different ways. To ensure reliable
continuation of normal program execution after a reset occurs, it is important to know what condition the microcontroller
is in after a particular reset occurs. The following table describes how each type of reset affects each of the
microcontroller internal registers. Note that where more than one package type exists the table will reflect the situation
for the larger package type.

HT45R52

                              Reset                  RES Reset              WDT Time-out              WDT Time-out
       Register
                            (Power-on)           (Normal Operation)       (Normal Operation)            (HALT)
 MP0                       xxxx xxxx                uuuu uuuu                uuuu uuuu                uuuu uuuu
 MP1                       xxxx xxxx                uuuu uuuu                uuuu uuuu                uuuu uuuu
 ACC                       xxxx xxxx                uuuu uuuu                uuuu uuuu                uuuu uuuu
 PCL                      0000 0000                 0000 0000                0000 0000                0000 0000
 TBLP                      xxxx xxxx                uuuu uuuu                uuuu uuuu                uuuu uuuu
 TBLH                      -xxx xxxx                -uuu uuuu                -uuu uuuu                -uuu uuuu
 RTCC                     --00 0111                 --00 0111                --00 0111                --uu uuuu
 STATUS                    --00 xxxx                --uu uuuu                --1u uuuu                --11 uuuu
 INTC0                    -000 0000                 -000 0000                -000 0000                -uuu uuuu
 TMR0                     0000 0000                 0000 0000                0000 0000                uuuu uuuu
 TMR0C                    00-0 1000                 00-0 1000                00-0 1000                uu-u uuuu
 PA                       1111 1111                 1111 1111                1111 1111                uuuu uuuu
 PAC                      1111 1111                 1111 1111                1111 1111                uuuu uuuu
 PB                       ---- 1111                 ---- 1111                ---- 1111                ---- uuuu
 PBC                      ---- 1111                 ---- 1111                ---- 1111                ---- uuuu
 PD                       --11 1111                 --11 1111                --11 1111                --uu uuuu
 PDC                      --11 1111                 --11 1111                --11 1111                --uu uuuu
 PWM0L                    0000 ---0                 0000 ---0                0000 ---0                uuuu ---u
 PWM0H                    0000 0000                 0000 0000                0000 0000                uuuu uuuu
 PWM1L                    0000 ---0                 0000 ---0                0000 ---0                uuuu ---u
 PWM1H                    0000 0000                 0000 0000                0000 0000                uuuu uuuu
 INTC1                    -000 -000                 -000 -000                -000 -000                -uuu -uuu
 MFIC                     --00 --00                 --00 --00                --00 --00                --uu --uu
 ADRL (ADRFS=0)            xxxx ----                 xxxx ----               xxxx ----                uuuu ----
 ADRL (ADRFS=1)            xxxx xxxx                 xxxx xxxx               xxxx xxxx                uuuu uuuu
 ADRH (ADRFS=0)            xxxx xxxx                 xxxx xxxx               xxxx xxxx                uuuu uuuu
 ADRH (ADRFS=1)            ---- xxxx                ---- xxxx                ---- xxxx                ---- uuuu
 ADCR0                    0110 0000                 0110 0000                0110 0000                uuuu uuuu
 ADCR1                    0000 0000                 0000 0000                0000 0000                uuuu uuuu
 ADCR2                    --00 0000                 --00 0000                --00 0000                --uu uuuu
 ANCSR0                   0000 0000                 0000 0000                0000 0000                uuuu uuuu
 ANCSR1                   ---- 0000                 ---- 0000                ---- 0000                ---- -uuu
 OPAC                     0x00 0000                 0x00 0000                0x00 0000                uuuu uuuu



Rev. 1.00                                                   61                                        September 21, 2010
                                                                                      HT45R52/HT45R54

                             Reset                RES Reset           WDT Time-out         WDT Time-out
        Register
                           (Power-on)         (Normal Operation)    (Normal Operation)       (HALT)
 CLKMOD                  0000 1111              0000 1111              0000 1111          uuuu uuuu
 PAWU                    0000 0000              0000 0000              0000 0000          uuuu uuuu
 PAPU                    0000 0000              0000 0000              0000 0000          uuuu uuuu
 PBPU                    ---- 0000              ---- 0000              ---- 0000          ---- uuuu
 PDPU                    --00 000-              --00 000-              --00 000-          --uu uuu-
 INTEDGE                 ---- 0000              ---- 0000              ---- 0000          ---- uuuu
 MISC                    0000 1010              0000 1010              0000 1010          uuuu uuuu
 SIMCTL0                 111- -000              111- -000              111- -000          uuu- -uuu
 SIMCTL1                 1000 00-1              1000 00-1              1000 00-1          uuuu uu-u
 SIMDR                   xxxx xxxx               xxxx xxxx             xxxx xxxx          uuuu uuuu
 SIMAR/SIMCTL2           0000 0000              0000 0000              0000 0000          uuuu uuuu

Note:    ²u² stands for unchanged
         ²x² stands for unknown
         ²-² stands for unimplemented
         If PD0/RES is selected to RES function, the PD.0 and PDC.0 are always ²0².




Rev. 1.00                                              62                                 September 21, 2010
                                                                  HT45R52/HT45R54

HT45R54

                     Reset          RES Reset          WDT Time-out       WDT Time-out
       Register
                   (Power-on)   (Normal Operation)   (Normal Operation)     (HALT)
 MP0              xxxx xxxx       uuuu uuuu            uuuu uuuu          uuuu uuuu
 MP1              xxxx xxxx       uuuu uuuu            uuuu uuuu          uuuu uuuu
 BP               0000 0000       0000 0000            0000 0000          uuuu uuuu
 ACC              xxxx xxxx       uuuu uuuu            uuuu uuuu          uuuu uuuu
 PCL              0000 0000       0000 0000            0000 0000          0000 0000
 TBLP             xxxx xxxx       uuuu uuuu            uuuu uuuu          uuuu uuuu
 TBLH             -xxx xxxx       -uuu uuuu            -uuu uuuu          -uuu uuuu
 RTCC             --00 0111       --00 0111            --00 0111          --uu uuuu
 STATUS           --00 xxxx       --uu uuuu            --1u uuuu          --11 uuuu
 INTC0            -000 0000       -000 0000            -000 0000          -uuu uuuu
 TMR0             0000 0000       0000 0000            0000 0000          uuuu uuuu
 TMR0C            00-0 1000       00-0 1000            00-0 1000          uu-u uuuu
 TMR1H            0000 0000       0000 0000            0000 0000          uuuu uuuu
 TMR1L            0000 0000       0000 0000            0000 0000          uuuu uuuu
 TMR1C            0000 1---       0000 1---            0000 1---          uuuu u---
 PA               1111 1111       1111 1111            1111 1111          uuuu uuuu
 PAC              1111 1111       1111 1111            1111 1111          uuuu uuuu
 PB               1111 1111       1111 1111            1111 1111          uuuu uuuu
 PBC              1111 1111       1111 1111            1111 1111          uuuu uuuu
 PC               1111 1111       1111 1111            1111 1111          uuuu uuuu
 PCC              1111 1111       1111 1111            1111 1111          uuuu uuuu
 PD               --11 1111       --11 1111            --11 1111          --uu uuuu
 PDC              --11 1111       --11 1111            --11 1111          --uu uuuu
 PWM0L            0000 ---0       0000 ---0            0000 ---0          uuuu ---u
 PWM0H            0000 0000       0000 0000            0000 0000          uuuu uuuu
 PWM1L            0000 ---0       0000 ---0            0000 ---0          uuuu ---u
 PWM1H            0000 0000       0000 0000            0000 0000          uuuu uuuu
 INTC1            -000 -000       -000 -000            -000 -000          -uuu -uuu
 MFIC             -000 -000       -000 -000            -000 -000          -uuu -uuu
 PWM2L            0000 ---0       0000 ---0            0000 ---0          uuuu ---u
 PWM2H            0000 0000       0000 0000            0000 0000          uuuu uuuu
 PWM3L            0000 ---0       0000 ---0            0000 ---0          uuuu ---u
 PWM3H            0000 0000       0000 0000            0000 0000          uuuu uuuu
 ADRL (ADRFS=0)   xxxx ----       xxxx ----            xxxx ----          uuuu ----
 ADRL (ADRFS=1)   xxxx xxxx       xxxx xxxx            xxxx xxxx          uuuu uuuu
 ADRH (ADRFS=0)   xxxx xxxx       xxxx xxxx            xxxx xxxx          uuuu uuuu
 ADRH (ADRFS=1)   ---- xxxx       ---- xxxx            ---- xxxx          ---- uuuu
 ADCR0            0110 0000       0110 0000            0110 0000          uuuu uuuu


Rev. 1.00                               63                                September 21, 2010
                                                                                      HT45R52/HT45R54

                             Reset                RES Reset           WDT Time-out         WDT Time-out
        Register
                           (Power-on)         (Normal Operation)    (Normal Operation)       (HALT)
 ADCR1                   0000 0000              0000 0000              0000 0000          uuuu uuuu
 ADCR2                   --00 0000              --00 0000              --00 0000          --uu uuuu
 ANCSR0                  0000 0000              0000 0000              0000 0000          uuuu uuuu
 ANCSR1                  0000 0000              0000 0000              0000 0000          uuuu uuuu
 ANCSR2                  0000 0000              0000 0000              0000 0000          uuuu uuuu
 OPAC                    0x00 0000              0x00 0000              0x00 0000          uuuu uuuu
 CLKMOD                  000- 1111              000- 1111              000- 1111          uuu- uuuu
 PAWU                    0000 0000              0000 0000              0000 0000          uuuu uuuu
 PAPU                    0000 0000              0000 0000              0000 0000          uuuu uuuu
 PBPU                    0000 0000              0000 0000              0000 0000          uuuu uuuu
 PCPU                    0000 0000              0000 0000              0000 0000          uuuu uuuu
 PDPU                    --00 000-              --00 000-              --00 000-          --uu uuu-
 INTEDGE                 ---- 0000              ---- 0000              ---- 0000          ---- uuuu
 MISC                    0000 1010              0000 1010              0000 1010          uuuu uuuu
 SIMCTL0                 111- -000              111- -000              111- -000          uuu- -uuu
 SIMCTL1                 1000 00-1              1000 00-1              1000 00-1          uuuu uu-u
 SIMDR                   xxxx xxxx               xxxx xxxx             xxxx xxxx          uuuu uuuu
 SIMAR/SIMCTL2           0000 0000              0000 0000              0000 0000          uuuu uuuu

Note:    ²u² stands for unchanged
         ²x² stands for unknown
         ²-² stands for unimplemented
         If PD0/RES is selected to RES function, the PD.0 and PDC.0 are always ²0².




Rev. 1.00                                              64                                 September 21, 2010
                                                                                                             HT45R52/HT45R54

Oscillator
Various oscillator options offer the user a wide range of         oscillator circuit contains a filter circuit to reduce the
functions according to their various application require-         possibility of erratic operation due to noise on the oscil-
ments. Five types of system clocks can be selected                lator pins. An additional configuration option must be
while various clock source options for the Watchdog               setup to configure the device according to whether the
Timer are provided for maximum flexibility. All oscillator        oscillator frequency is high, defined as equal to or above
options are selected through the configuration options.           1MHz, or low, which is defined as below 1MHz.
                                                                  More information regarding oscillator applications is lo-
System Clock Configurations
                                                                  cated on the Holtek website.
There are five methods of generating the system clock,
                                                                                         C 1
three high oscillators, one low oscillators and an exter-
                                                                                                                          O S C 1
nally supplied clock. The one high oscillators are the ex-
ternal crystal/ceramic oscillator, internal RC oscillator                                             R 1

and the external RC network. The low oscillators is the                                                                   O S C 2
fully integrated 32kHz oscillator known with the name                                    C 2
LIRC. Selecting whether the low or high oscillator is
                                                                                Crystal/Ceramic Oscillator
used as the system oscillator is implemented using the
HLCLK bit in the CLKMOD register. The source clock for
                                                                  External System RC Oscillator - ERC
the high and low oscillators is chosen via configuration
options. The frequency of the slow oscillator is also de-         After selecting the correct configuration option, using
termined using the SLOWC0~ SLOWC2 bits in the                     the external system RC oscillator requires that a resis-
CLKMOD register.                                                  tor, with a value between 47kW and 1.5MW, is con-
                                                                  nected between OSC1 and VDD, and a 470pF capacitor
       Type          Name       Freq.          Pins
                                                                  is connected to ground. Although this is a cost effective
                               400kHz~                            oscillator configuration, the oscillation frequency can
 External Crystal     HXT                  OSC1/OSC2
                               12MHz                              vary with VDD, temperature and process variations and
                               400kHz~                            is therefore not suitable for applications where timing is
 External RC          ERC                     OSC1                critical or where accurate oscillator frequencies are re-
                               12MHz
                                                                  quired. For the value of the external resistor ROSC refer
 Internal High
                     HIRC                       ¾                 to the Appendix section for typical RC Oscillator vs.
 Speed RC
                                                                  Temperature and VDD characteristics graphics.
 Internal Low
                     LIRC       32kHz           ¾                                                 V    D D
 Speed RC
                               400kHz~
 External Clock       ECK                     OSC1
                               12MHz                                                 R    O S C

                                                                                                               O S C 1
System Crystal/Ceramic Oscillator - HXT                                           4 7 0 p F
After selecting the external crystal configuration option,
the simple connection of a crystal across OSC1 and                                                             P D 2
OSC2, is normally all that is required to create the nec-
essary phase shift and feedback for oscillation, without                                              RC Oscillator
requiring external capacitors. However, for some crystal
                                                                  Note that an internal capacitor together with the external
types and frequencies, to ensure oscillation, it may be
                                                                  resistor, ROSC, are the components which determine the
necessary to add two small value capacitors, C1 and
                                                                  frequency of the oscillator. The external capacitor
C2. Using a ceramic resonator will usually require two
                                                                  shown on the diagram does not influence the frequency
small value capacitors, C1 and C2, to be connected as
                                                                  of oscillation. Note that if this external system RC oscil-
shown for oscillation to occur. The values of C1 and C2
                                                                  lation option is selected, as it requires OSC1 external
should be selected in consultation with the crystal or
                                                                  pin for its operation, the PD2/OSC2 pin is free for use as
resonator manufacturer¢s specification. In most applica-
                                                                  normal I/O pin. The internal oscillator circuit contains a
tions, resistor R1 is not required, however for those ap-
                                                                  filter circuit to reduce the possibility of erratic operation
plications where the LVR function is not used, R1 may
                                                                  due to noise on the oscillator pins.
be necessary to ensure the oscillator stops running
when VDD falls below its operating range. The internal




Rev. 1.00                                                    65                                                          September 21, 2010
                                                                                                                              HT45R52/HT45R54

Internal RC Oscillator - HIRC                                                      their external hardware to the microcontroller operation.
The internal RC oscillator is a fully integrated system os-                        This is selected using a configuration option and supply-
cillator requiring no external components. The internal                            ing the clock on pin OSC1. Pin OSC2 should be left
RC oscillator has three fixed frequencies of either                                floating if the external oscillator is used. The internal os-
4MHz, 8MHz or 12MHz, the choice of which is indicated                              cillator circuit contains a filter circuit to reduce the possi-
by the configuration options. Note that if this internal                           bility of erratic operation due to noise on the oscillator
system clock option is selected, as it requires no exter-                          pin, however as the filter circuit consumes a certain
nal pins for its operation, the OSC1 and OSC2 pins are                             amount of power.
free for use as normal I/O pins. Refer to the Appendix
section for more information on the actual internal oscil-                         System Operating Modes
lator frequency vs. Temperature and VDD characteris-
                                                                                   The devices have the ability to operate in several differ-
tics graphics.
                                                                                   ent modes. This range of operating modes, known as
                                                                                   Normal Mode, Slow Mode, Idle Mode and Sleep Mode,
Internal Low Speed Oscillator - LIRC
                                                                                   allow the devices to run using a wide range of different
When microcontrollers enter a power down condition,                                slow and fast clock sources. The devices also possess
their internal clocks are normally switched off to stop                            the ability to dynamically switch between different clocks
microcontroller activity and to conserve power. How-                               and operating modes. With this choice of operating
ever, in many microcontroller applications it may be nec-                          functions users are provided with the flexibility to ensure
essary to keep some internal functions operational,                                they obtain optimal performance from the device ac-
such as timers, even when the microcontroller is in the                            cording to their application specific requirements.
Power-down mode. To do this, the device has an inter-
nal 32kHz oscillator, LIRC oscillator, which is a fully inte-                      Clock Sources
grated free running RC oscillator with a typical period of                         In discussing the system clocks for the devices, they
31.2ms at 5V, requiring no external components. It is se-                          can be seen as having a dual clock mode. These dual
lected via configuration option. When the device enters                            clocks are what are known as a High Oscillator and the
the Power Down Mode, the system clock will stop run-                               other as a Low Oscillator. The High and Low Oscillator
ning, however the LIRC oscillator will continue to run if                          are the system clock sources and can be selected dy-
selected to keep various internal functions operational.                           namically using the HLCLK bit in the CLKMOD register.

External Oscillator - ECK                                                          The High Oscillator has the internal name fM whose
                                                                                   source is selected using a configuration option from a
The system clock can also be supplied by an externally                             choice of either an external crystal/resonator, external
supplied clock giving users a method of synchronising                              RC oscillator or external clock source.
         b 7                                                                            b 0
     S L O W C 2 S L O W C 1 S L O W C 0 S IM ID L E    L T O   H T O   ID L E N   H L C L K   C L K M O D         R e g is te r

                                                                                               fS Y S s e le c t
                                                                                                1 : fM
                                                                                               0 : fS L O W

                                                                                               Id le m o d e
                                                                                               1 : e n a b le
                                                                                                0 : d is a b le

                                                                                               H ig h o s c illa to r r e a d y fla g
                                                                                                1 : tim e - o u t
                                                                                                 0 : n o n - tim e - o u t

                                                                                               L o w o s c illa to r r e a d y fla g
                                                                                                1 : tim e - o u t
                                                                                                 0 : n o n - tim e - o u t

                                                                                               S P I/I2 C c o n tin u e s r u n n in g in Id le m o d e
                                                                                                1 :e n a b le
                                                                                                 0 :d is a b le

                                                                                                fS L O W s e le c tio n
                                                                                               S L O W W C 2 S L O W W C 1                 S L O W W C 0            fS      L O W
                                                                                                         0               0                        0                      fS     L
                                                                                                           0               0                        1                    fS     L
                                                                                                             0               1                        0             fM        /6 4
                                                                                                               0               1                        1           fM        /3 2
                                                                                                                 1               0                        0         fM        /1 6
                                                                                                                   1               0                        1        fM         /8
                                                                                                                     1               1                        0        fM       /4
                                                                                                                       1               1                        1      fM       /2
                                                       Clock Control Register - CLKMOD


Rev. 1.00                                                                     66                                                                 September 2, 2010
                                                                                                                                                                                                    HT45R52/HT45R54

The Low Oscillator clock source, has the internal name                                                                                 · Normal mode
fSL, whose source is from the internal LIRC oscillator.                                                                                               fM on, fSLOW on, fSYS=fM, CPU on, fS on, fWDT on/off de-
This internal fSL, fM clock, is further modified by the                                                                                               pending upon the WDT configuration option and WDT
                                                                                                                                                      control register.
SLOWC0~SLOWC2 bits in the CLKMOD register to
provide the low frequency clock source fSLOW.                                                                                          · Slow mode0
                                                                                                                                                      fM off, fSLOW=LIRC oscillator, fSYS=fSLOW, CPU on, fS on,
An additional sub internal clock, with the internal name ,                                                                                            fWDT on/off depending upon the WDT configuration op-
is a 32kHz clock source which can be sourced from the                                                                                                 tion and WDT control register.
internal LIRC oscillator. Together with fSYS/4, it is used as
                                                                                                                                       · Slow mode1
a clock source for certain internal functions such as the
                                                                                                                                                      fM on, fSLOW=fM/2~fM/64, fSYS=fSLOW, CPU on, fS on, fWDT
Watchdog Timer, Buzzer, RTC Interrupt and Time Base
                                                                                                                                                      on/off depending upon the WDT configuration option
Interrupt. The internal clock fS, is simply a choice of either
                                                                                                                                                      and WDT control register.
fSUB or fSYS/4, using a configuration option.
                                                                                                                                       · Idle mode
Operating Modes                                                                                                                                       fM, fSLOW, fSYS off, CPU off; fSUB on, fS on/off by selecting
                                                                                                                                                      fSUB or fSYS/4, fWDT on/off depending upon the WDT
After the correct clock source configuration selections
                                                                                                                                                      configuration option and WDT control register.
are made, overall operation of the chosen clock is
achieved using the CLKMOD register. A combination of                                                                                   · Sleep mode
the HLCLK and IDLEN bits in the CLKMOD register and                                                                                                   fM, fSLOW, fSYS, fS, CPU off; fSUB, fWDT on/off depending
use of the HALT instruction determine in which mode the                                                                                               upon the WDT configuration option and WDT control
                                                                                                                                                      register.
device will be run. The devices can operate in the follow-
ing Modes.




                                                                                                  N o rm a l M o d e



                                                                                                                fM O n ,
                                                                                                             L IR C O n ,
                                                                                                                                                                                                          w a
                                         -u p                                                                  fS Y S = fM                                         H A                                        ke
                                     k e                                         = 0                                                                                   L T                                       -u
                                 w a                                         N "                                                                                             &                                        p
                                                                         L E                                                                                                     "ID
                                                                     "ID                                                                                                                L E
                                                                                                                                                                                            N "
                                                             &
                                                     L T                                                                                                                                        =
                                                                                                                                                                                                      1
                                                 H A




                       S le e p M o d e                                                                                                                                                                                      Id le M o d e
                                                                                                                             R e s e t "H L C L K "
                                                                                                  S e t "H L C K "




                             fM O ff,                                                                                                                                                                                            fM O ff,
                                                                                                                                                                                                                                               #
                         L IR C O n * ,                                                                                                                                                                                      L IR C O n ,
                           fS Y S = O ff                                                                                                                                                                                       fS Y S = O ff




                                                   w a
                                                       ke
                             H A                          -u
                                                             p                                                                                                                                 -u p
                                 L T                                                                                                                                                       k e
                                       &
                                                                                                       S lo w         M o d e                                                          w a                                    = 1
                                           "ID                                                                                                                                                                            N "
                                                 L E                                                                                                                                                                  L E
                                                     N "                                                                                                                                                          "ID
                                                         =                                                                                                                                                    &
                                                                 0                                                                                                                                 L T
                                                                                                           fM O n     /O ff,                                                                   H A
                                                                                                           L IR C       O n ,
                                                                                            fS   Y S        = fM /2      ~ fM /6 4
                                                                                                               L IR   C

  " * " D e p e n d s th e W D T e n a b le /d is a b le c o n d itio n .                                                                                       " # " L IR C m u s t b e O N .
   if W D T is e n a b le d , fS U B = L IR C , th e n L IR C O n                                                                                                If fS U B = L IR C , th e n L IR C                       is O N .

                                                                                       Dual Clock Mode Operation




Rev. 1.00                                                                                                             67                                                                                                       September 21, 2010
                                                                                                                                                        HT45R52/HT45R54

                H ig h F r e q u e n c y O s c illa to r


            O S C 1              E C K



            O S C 1              E R C
                                                                        H ig h F r e q u e n c y O s c illa to r
                                                                         C o n fig u r a tio n O p tio n
            O S C 1                                                                                                                                            H L C L K B it
                                 H X T
            O S C 2
                                                                                                             fM
                                                                               M U X                                                                                   M U X                fS   Y S

                                 H IR C

                                                                                                                              fM
                                                                                                                                                                               fS   L O W

                                                                                                                        S lo w
                                                                                               fS    L                                  fM /2 , ... fM /6 4 , fS   L
                                                                                                                       C lo c k
                                                                                                                     C o n tro l


                                          L IR C                                                                                       S L O W C 0
                                                                                                                                        S L O W C 1
                                                                                                                                         S L O W C 2
                         L o w   F r e q u e n c y O s c illa to r
                                                                                          fS        U B                                                      R T C in te r r u p t,
                                                                                                                                            fS
                                                                                                                      M U X                             T im e B a s e in te r r u p t,
                                                                          fS   Y S   /4
                                                                                                                                                              B u z z e r, W D T

                                                                                                                          fS
                                                                                                          C o n fig u r a tio n O p tio n
                                                                     Dual Clock Mode Structure



Power Down Mode and Wake-up
Power Down Mode                                                                                                   oscillator. The WDT will stop if its clock source origi-
                                                                                                                  nates from the system clock.
All of the Holtek microcontrollers have the ability to enter
                                                                                                           · The I/O ports will maintain their present condition.
a Power Down Mode. When the device enters this
mode, the normal operating current, will be reduced to                                                     · In the status register, the Power Down flag, PDF, will
an extremely low standby current level. This occurs be-                                                           be set and the Watchdog time-out flag, TO, will be
cause when the device enters the Power Down Mode,                                                                 cleared.
the system oscillator is stopped which reduces the
                                                                                                           Standby Current Considerations
power consumption to extremely low levels, however,
as the device maintains its present internal condition, it                                                 As the main reason for entering the Power Down Mode
can be woken up at a later stage and continue running,                                                     is to keep the current consumption of the MCU to as low
without requiring a full reset. This feature is extremely                                                  a value as possible, perhaps only in the order of several
important in application areas where the MCU must                                                          micro-amps, there are other considerations which must
have its power supply constantly maintained to keep the                                                    also be taken into account by the circuit designer if the
device in a known condition but where the power supply                                                     power consumption is to be minimized. Special atten-
capacity is limited such as in battery applications.                                                       tion must be made to the I/O pins on the device. All
                                                                                                           high-impedance input pins must be connected to either
Entering the Power Down Mode                                                                               a fixed high or low level as any floating input pins could
There is only one way for the device to enter the Power                                                    create internal oscillations and result in increased cur-
Down Mode and that is to execute the ²HALT² instruc-                                                       rent consumption. This also applies to devices which
tion in the application program. When this instruction is                                                  have different package types, as there may be
executed, the following will occur:                                                                        undonbed pins, which must either be setup as outputs
                                                                                                           or if setup as inputs must have pull-high resistors con-
· The system oscillator will stop running and the appli-
                                                                                                           nected. Care must also be taken with the loads, which
  cation program will stop at the ²HALT² instruction.
                                                                                                           are connected to I/O pins, which are setup as outputs.
· The Data Memory contents and registers will maintain
                                                                                                           These should be placed in a condition in which minimum
  their present condition.
                                                                                                           current is drawn or connected only to external circuits
· The WDT will be cleared and resume counting if the                                                       that do not draw current, such as other CMOS inputs.
  WDT clock source is selected to come from the WDT                                                        Also note that additional standby current will also be re-


Rev. 1.00                                                                                           68                                                                          September 21, 2010
                                                                                               HT45R52/HT45R54

quired if the configuration options have enabled the                Fast Wake-Up
LIRC internal oscillator.                                           To minimise power consumption the device can enter
                                                                    the SLEEP or IDLE Mode, where the clock source to the
Wake-up
                                                                    device will be stopped. However when the device is
After the system enters the Power Down Mode, it can be              woken up again, it can take a considerable time for the
woken up from one of various sources listed as follows:             original system oscillator to restart, stabilise and allow
· An external reset                                                 normal operation to resume. To ensure the device is up
· An external falling edge on Port A                                and running as fast as possible a Fast Wake-Up function
                                                                    is provided, which allows fSUB, namely the LIRC oscilla-
· A system interrupt
                                                                    tor, to act as a temporary clock to first drive the system
· A WDT overflow
                                                                    until the original system oscillator has stabilised. As the
If the system is woken up by an external reset, the de-             clock source for the Fast Wake-Up function is the
vice will experience a full system reset, however, if the           Watchdog Timer clock, the Watchdog Timer must be en-
device is woken up by a WDT overflow, a Watchdog                    abled for this function to operate. If the Watchdog Timer
Timer reset will be initiated. Although both of these               is not enabled then the Fast Start-up function cannot be
wake-up methods will initiate a reset operation, the ac-            used. The Fast Wake-Up enable/disable function is con-
tual source of the wake-up can be determined by exam-               trolled using the configuration option.
ining the TO and PDF flags. The PDF flag is cleared by a
                                                                    If the Crystal oscillator is selected as the NORMAL
system power-up or executing the clear Watchdog
                                                                    Mode system clock, and if the Fast Wake-Up function is
Timer instructions and is set when executing the ²HALT²             enabled, then it will take one to two tSUB clock cycles of
instruction. The TO flag is set if a WDT time-out occurs,           the LIRC oscillator for the system to wake-up. The sys-
and causes a wake-up that only resets the Program                   tem will then initially run under the fSUB clock source until
Counter and Stack Pointer, the other flags remain in                1024 Crystal clock cycles have elapsed, at which point
their original status.                                              the HTO flag will switch high and the system will switch
Each pin on Port A can be setup via an individual config-           over to operating from the Crystal oscillator.
uration option to permit a negative transition on the pin           If the ERC or HIRC oscillators or LIRC oscillator is used
to wake-up the system. When a Port A pin wake-up oc-                as the system oscillator then it will take 1~2 clock cycles
curs, the program will resume execution at the instruc-             of the ERC, HIRC or LIRC to wake up the system from
tion following the ²HALT² instruction.                              the SLEEP or IDLE Mode.
If the system is woken up by an interrupt, then two possi-          Note that if the Watchdog Timer is disabled, which
ble situations may occur. The first is where the related            means that the LIRC is off, then there will be no Fast
interrupt is disabled or the interrupt is enabled but the           Wake-Up function available when the device wakes-up
stack is full, in which case the program will resume exe-           from the SLEEP Mode.
cution at the instruction following the ²HALT² instruction.
In this situation, the interrupt which woke-up the device           Low Voltage Detector - LVD
will not be immediately serviced, but will rather be ser-
viced later when the related interrupt is finally enabled or        The Low Voltage Detect internal function provides a
when a stack level becomes free. The other situation is             means for the user to monitor when the power supply
where the related interrupt is enabled and the stack is             voltage falls below a certain fixed level as specified in
not full, in which case the regular interrupt response              the DC characteristics.
takes place. If an interrupt request flag is set to ²1² be-
                                                                    LVD Operation
fore entering the Power Down Mode, the wake-up func-
tion of the related interrupt will be disabled.                     The LVD function must be first enabled via a
                                                                    configuration option after which bits 3 and 5 of the RTCC
No matter what the source of the wake-up event is, once
                                                                    register are used to control the overall function of the
a wake-up situation occurs, a time period equal to tSST
                                                                    LVD. Bit 3 is the enable/disable control bit and is known
system clock periods will be required before normal sys-
                                                                    as LVDC, when set low the overall function of the LVD
tem operation resumes. However, if the wake-up has
                                                                    will be disabled. Bit 5 is the LVD detector output bit and
originated due to an interrupt, the actual interrupt sub-
                                                                    is known as LVDO. Under normal operation, and when
routine execution will be delayed by an additional one or
                                                                    the power supply voltage is above the specified VLVD
more cycles. If the wake-up results in the execution of
                                                                    value in the DC characteristic section, the LVDO bit will
the next instruction following the ²HALT² instruction, this
                                                                    remain at a zero value. If the power supply voltage
will be executed immediately after the tSST system clock
                                                                    should fall below this VLVD value then the LVDO bit will
period delay has ended.
                                                                    change to a high value indicating a low voltage condi-
                                                                    tion. Note that the LVDO bit is a read-only bit. By polling
                                                                    the LVDO bit in the RTCC register, the application pro-


Rev. 1.00                                                      69                                         September 21, 2010
                                                                                                                                                                                              HT45R52/HT45R54

gram can therefore determine the presence of a low                                                                     In addition to a configuration option to enable the
voltage condition.                                                                                                     Watchdog Timer, there are four bits, WDTEN3~
                                                                                                                       WDTEN0, in the MISC register to offer an additional en-
After power-on, or after a reset, the LVD will be switched
                                                                                                                       able control of the Watchdog Timer. These bits must be
off by clearing the LVDC bit in the RTCC register to zero.
                                                                                                                       set to a specific value of 1010 to disable the Watchdog
Note that if the LVD is enabled there will be some power
                                                                                                                       Timer. Any other values for these bits will keep the
consumption associated with its internal circuitry, how-
                                                                                                                       Watchdog Timer enabled. After power on these bits will
ever, by clearing the LVDC bit to zero the power can be
                                                                                                                       have the disabled value of 1010.
minimised. It is important not to confuse the LVD with
the LVR function. In the LVR function an automatic reset                                                               One of the WDT clock sources is the internal fSUB, which
will be generated by the microcontroller, whereas in the                                                               sourced from the LIRC internal oscillator. The LIRC in-
LVD function only the LVDO bit will be affected with no                                                                ternal oscillator has an approximate period of 31.2ms at
influence on other microcontroller functions.                                                                          a supply voltage of 5V. However, it should be noted that
There are a range of voltage values, selected using a                                                                  this specified internal clock period can vary with VDD,
configuration option, which can be chosen to activate                                                                  temperature and process variations. The other Watch-
the LVD.                                                                                                               dog Timer clock source option is the fSYS/4 clock.
                                                                                                                       Whether the Watchdog Timer clock source is its own in-
                                                                                                                       ternal LIRC or fSYS/4, it is divided by 213~216, using con-
Watchdog Timer                                                                                                         figuration option to obtain the required Watchdog Timer
The Watchdog Timer is provided to prevent program                                                                      time-out period. The max time out period is when the 216
malfunctions or sequences from jumping to unknown lo-                                                                  option is selected. This time-out period may vary with
cations, due to certain uncontrollable external events                                                                 temperature, VDD and process variations. As the clear
such as electrical noise. It operates by providing a de-                                                               instruction only resets the last stage of the divider chain,
vice reset when the Watchdog Timer counter overflows.                                                                  for this reason the actual division ratio and correspond-
                                                                                                                       ing Watchdog Timer time-out can vary by a factor of two.
Watchdog Timer Operation                                                                                               The exact division ratio depends upon the residual value
The Watchdog Timer clock source is provided by the in-                                                                 in the Watchdog Timer counter before the clear instruc-
ternal clock, fS, which is in turn supplied by one of two                                                              tion is executed.
sources selected by configuration option: fSUB or fSYS/4.                                                              If the fSYS/4 clock is used as the Watchdog Timer clock
Note that if the Watchdog Timer configuration option                                                                   source, it should be noted that when the system enters
has been disabled, then any instruction relating to its op-                                                            the Power Down Mode, then the instruction clock is
eration will result in no operation.                                                                                   stopped and the Watchdog Timer will lose its protecting
Most of the Watchdog Timer options, such as en-                                                                        purposes. For systems that operate in noisy environ-
able/disable, Watchdog Timer clock source and clear in-                                                                ments, using the LIRC oscillator is strongly recom-
struction type are selected using configuration options.                                                               mended.

      C L R W D T 1 F la g
                                                        C o n tro l
                                                          L o g ic
      C L R W D T 2 F la g

    1 o r 2 In s tr u c tio n s

                                                                                                                                                                                      C L R
                       fS   Y S    /4          W D T S o u rc e       fS                              fS /2     8

         L IR C O s c illa to r
                                              C o n fig u r a tio n            8 - b it D iv id e r                   7 - b it P r e s c a le r                               ¸   2            W D T T im e - o u t
                                                   O p tio n                                                                                                                                    (2 13/fS , 2 14/fS , 2 15/fS o r 2   1 6   /fS )

                                                                                                                              C o n fig O p tio n
                                                                                                              fS /2   1 2   , fS /2   1 3   , fS /2   1 4   o r fS /2   1 5


                                                                                            Watchdog Timer

        b 7                                                                                                        b 0
     O D E 3    O D E 2           O D E 1   O D E 0    W D T E N 3         W D T E N 2     W D T E N 1         W D T E N 0                   M IS C         R e g is te r

                                                                                                                                              W a tc h d o g T im e r E n a b le C o n tr o l
                                                                                                                                             W D T E N 3 W D T E N 2 W D T E N 1 W D T E N 0
                                                                                                                                                      1                 0           1         0                                  d is a b le
                                                                                                                                               a ll o th e r v a lu e s                                                           e n a b le

                                                                                                                                             P A 0 ~ P A 3 O p e n D r a in C o n tr o l
                                                                                                                                              - d e s c r ib e d e ls e w h e r e
                                                                  Watchdog Timer Software Control - MISC


Rev. 1.00                                                                                                70                                                                                                September 21, 2010
                                                                                                  HT45R52/HT45R54

Under normal program operation, a Watchdog Timer                       by configuration option. The first option is to use the sin-
time-out will initialise a device reset and set the status bit         gle ²CLR WDT² instruction while the second is to use the
TO. However, if the system is in the Power Down Mode,                  two commands ²CLR WDT1² and ²CLR WDT2². For the
when a Watchdog Timer time-out occurs, the TO bit in                   first option, a simple execution of ²CLR WDT² will clear
the status register will be set and only the Program                   the WDT while for the second option, both ²CLR WDT1²
Counter and Stack Pointer will be reset. Three methods
                                                                       and ²CLR WDT2² must both be executed to successfully
can be adopted to clear the contents of the Watchdog
                                                                       clear the Watchdog Timer. Note that for this second op-
Timer. The first is an external hardware reset, which
                                                                       tion, if ²CLR WDT1² is used to clear the Watchdog Timer,
means a low level on the RES pin, the second is using
                                                                       successive executions of this instruction will have no ef-
the watchdog software instructions and the third is via a
                                                                       fect, only the execution of a ²CLR WDT2² instruction will
²HALT² instruction.
                                                                       clear the Watchdog Timer. Similarly after the ²CLR
Clearing the Watchdog Timer                                            WDT2² instruction has been executed, only a successive
                                                                       ²CLR WDT1² instruction can clear the Watchdog Timer.
There are two methods of using software instructions to
clear the Watchdog Timer, one of which must be chosen




Configuration Options
Configuration options refer to certain options within the MCU that are programmed into the device during the program-
ming process. During the development process, these options are selected using the HT-IDE software development
tools. As these options are programmed into the device using the hardware programming tools, once they are selected
they cannot be changed later as the application software has no control over the configuration options. All options must
be defined for proper system function, the details of which are shown in the table.

    No.                                                               Options
 Oscillator Options
              High Oscillator type selection - fM
              1. External Crystal oscillator
      1       2. External RC oscillator
              3. Internal RC oscillator
              4. Externally supplied clock
      2       Internal RC Oscillator frequency select: 4MHz, 8MHz or 12MHz
      3       fS clock selection: fSUB or fSYS/4. fSUB is the LIRC internal oscillator
      4       XTAL mode selection: 455kHz or 1MHz~12MHz
      5       Fast wake-up from HALT mode (Only for external crystal oscillator): enable/disable
 Reset Option
      6       Reset pin function: PD0 or RES Pin
 PFD Options
      7       PA3: normal I/O or PFD output
      8       PFD clock selection: Timer/Event Counter 0 or Timer/Event Counter 1
 Buzzer Options
      9       PB0/PB1: normal I/O or BZ/BZ or PB0=BZ and PB1 as normal I/O
     10       Buzzer frequency: fS/22, fS/23, fS/24, fS/25, fS/26, fS/27, fS/28, fS/29
 Time Base Option
     11       Time base time-out period: 212/fS, 213/fS, 214/fS, 215/fS,
 Watchdog Options
     12       Watchdog Timer function: enable or disable
     13       CLRWDT instructions: 1 or 2 instructions
     14       WDT time-out period: 212/fS~213/fS, 213/fS~214/fS, 214/fS~215/fS, 215/fS~216/fS


Rev. 1.00                                                        71                                         September 21, 2010
                                                                                                                                              HT45R52/HT45R54

     No.                                                                                         Options
 LVD/LVR Options
     15       LVD function: enable or disable
     16       LVR function: enable or disable
     17       LVR/LVD voltage: 2.1V/2.2V or 3.15V/3.3V or 4.2V/4.4V
 SPI Options
     18       SIM pin enable/disable
     19       SPI_WCOL: enable/disable
     20       SPI_CSEN: enable/disable, used to enable/disable (1/0) software CSEN function
 2
 I C Option
     21       I2C debounce Time: no debounce, 1 system clock debounce, 2 system clock debounce
 Timer/Event Counter and External Interrupt Pins Filter Option
     22       Interrupt and Timer/Event Counter input pins internal filter On/Off control - applies to all pins


Application Circuits
                                                               V        D D

                                            0 .0 1 m F
                                                                                                 V D D


                                                                              1 0 k W ~                    R e s e t
                                                                               1 0 0 k W                    C ir c u it
                                  1 N 4 1 4 8                                                                               P A 0 /A N 0 ~
                   0 .1 m F
                                                                                                 P D 0 /R E S                P A 7 /A N 7
                                                                                  3 0 0 W
                                                0 .1 ~ 1 m F                                                               P B 0 /A N 8 ~
                                                                                                                            P B 3 /A N 1 1
                                                                                                 V S S
                                                                                                           P D 3 /O P V IN P /V R E F
                                                                                                                    P D 4 /O P V IN N
                                                                                                                     P D 5 /O P O U T
                                                                        O S C                    P D 1 /O S C 1
                                                                       C ir c u it               P D 2 /O S C 2
                                                         S e e O s c illa to r
                                                              S e c tio n
                                                                                                                H T 4 5 R 5 2




                                                                   V    D D

                                            0 .0 1 m F
                                                                                                 V D D

                                                                                                                            P A 0 /A N 0 ~
                                                                              1 0 k W ~                    R e s e t         P A 7 /A N 7
                                                                               1 0 0 k W                    C ir c u it
                                  1 N 4 1 4 8
                   0 .1 m F                                                                                                P B 0 /A N 8 ~
                                                                                                 P D 0 /R E S               P B 7 /A N 1 5
                                                                                  3 0 0 W
                                                0 .1 ~ 1 m F
                                                                                                                           P C 0 /A N 1 6 ~
                                                                                                                            P C 7 /A N 2 3
                                                                                                 V S S
                                                                                                           P D 3 /O P V IN P /V R E F
                                                                                                                    P D 4 /O P V IN N
                                                                                                                     P D 5 /O P O U T
                                                                        O S C                    P D 1 /O S C 1
                                                                       C ir c u it               P D 2 /O S C 2
                                                         S e e O s c illa to r
                                                              S e c tio n
                                                                                                                H T 4 5 R 5 4


Rev. 1.00                                                                                   72                                                    September 21, 2010
                                                                                                         HT45R52/HT45R54

Instruction Set
Introduction                                                                  sure correct handling of carry and borrow data when re-
C e n t ra l t o t he s uc c es s f ul oper a t i on o f a n y                sults exceed 255 for addition and less than 0 for sub-
                                                                              traction. The increment and decrement instructions
microcontroller is its instruction set, which is a set of pro-
                                                                              INC, INCA, DEC and DECA provide a simple means of
gram instruction codes that directs the microcontroller to
                                                                              increasing or decreasing by a value of one of the values
perform certain operations. In the case of Holtek
                                                                              in the destination specified.
microcontroller, a comprehensive and flexible set of
over 60 instructions is provided to enable programmers
                                                                              Logical and Rotate Operations
to implement their application with the minimum of pro-
gramming overheads.                                                           The standard logical operations such as AND, OR, XOR
                                                                              and CPL all have their own instruction within the Holtek
For easier understanding of the various instruction
                                                                              microcontroller instruction set. As with the case of most
codes, they have been subdivided into several func-
                                                                              instructions involving data manipulation, data must pass
tional groupings.
                                                                              through the Accumulator which may involve additional
                                                                              programming steps. In all logical data operations, the
Instruction Timing
                                                                              zero flag may be set if the result of the operation is zero.
Most instructions are implemented within one instruc-                         Another form of logical data manipulation comes from
tion cycle. The exceptions to this are branch, call, or ta-                   the rotate instructions such as RR, RL, RRC and RLC
ble read instructions where two instruction cycles are                        which provide a simple means of rotating one bit right or
required. One instruction cycle is equal to 4 system                          left. Different rotate instructions exist depending on pro-
clock cycles, therefore in the case of an 8MHz system                         gram requirements. Rotate instructions are useful for
oscillator, most instructions would be implemented                            serial port programming applications where data can be
within 0.5ms and branch or call instructions would be im-                     rotated from an internal register into the Carry bit from
plemented within 1ms. Although instructions which re-                         where it can be examined and the necessary serial bit
quire one more cycle to implement are generally limited                       set high or low. Another application where rotate data
to the JMP, CALL, RET, RETI and table read instruc-                           operations are used is to implement multiplication and
tions, it is important to realize that any other instructions                 division calculations.
which involve manipulation of the Program Counter Low
register or PCL will also take one more cycle to imple-                       Branches and Control Transfer
ment. As instructions which change the contents of the                        Program branching takes the form of either jumps to
PCL will imply a direct jump to that new address, one                         specified locations using the JMP instruction or to a sub-
more cycle will be required. Examples of such instruc-                        routine using the CALL instruction. They differ in the
tions would be ²CLR PCL² or ²MOV PCL, A². For the                             sense that in the case of a subroutine call, the program
case of skip instructions, it must be noted that if the re-                   must return to the instruction immediately when the sub-
sult of the comparison involves a skip operation then                         routine has been carried out. This is done by placing a
this will also take one more cycle, if no skip is involved                    return instruction RET in the subroutine which will cause
then only one cycle is required.                                              the program to jump back to the address right after the
                                                                              CALL instruction. In the case of a JMP instruction, the
Moving and Transferring Data
                                                                              program simply jumps to the desired location. There is
The transfer of data within the microcontroller program                       no requirement to jump back to the original jumping off
is one of the most frequently used operations. Making                         point as in the case of the CALL instruction. One special
use of three kinds of MOV instructions, data can be                           and extremely useful set of branch instructions are the
transferred from registers to the Accumulator and                             conditional branches. Here a decision is first made re-
vice-versa as well as being able to move specific imme-                       garding the condition of a certain data memory or indi-
diate data directly into the Accumulator. One of the most                     vidual bits. Depending upon the conditions, the program
important data transfer applications is to receive data                       will continue with the next instruction or skip over it and
from the input ports and transfer data to the output ports.                   jump to the following instruction. These instructions are
                                                                              the key to decision making and branching within the pro-
Arithmetic Operations                                                         gram perhaps determined by the condition of certain in-
The ability to perform certain arithmetic operations and                      put switches or by the condition of internal data bits.
data manipulation is a necessary feature of most
microcontroller a p p l i c at i o n s . W i t h i n t h e H o l t e k
microcontroller instruction set are a range of add and
subtract instruction mnemonics to enable the necessary
arithmetic to be carried out. Care must be taken to en-




Rev. 1.00                                                                73                                        September 21, 2010
                                                                                           HT45R52/HT45R54

Bit Operations                                                    Other Operations
The ability to provide single bit operations on Data Mem-         In addition to the above functional instructions, a range
ory is an extremely flexible feature of all Holtek                of other instructions also exist such as the ²HALT² in-
microcontrollers. This feature is especially useful for           struction for Power-down operations and instructions to
output port bit programming where individual bits or port         control the operation of the Watchdog Timer for reliable
pins can be directly set high or low using either the ²SET        program operations under extreme electric or electro-
[m].i² or ²CLR [m].i² instructions respectively. The fea-         magnetic environments. For their relevant operations,
ture removes the need for programmers to first read the           refer to the functional related sections.
8-bit output port, manipulate the input data to ensure
that other bits are not changed and then output the port          Instruction Set Summary
with the correct new data. This read-modify-write pro-            The following table depicts a summary of the instruction
cess is taken care of automatically when these bit oper-          set categorised according to function and can be con-
ation instructions are used.                                      sulted as a basic instruction reference using the follow-
                                                                  ing listed conventions.
Table Read Operations
                                                                  Table conventions:
Data storage is normally implemented by using regis-
ters. However, when working with large amounts of                 x: Bits immediate data
fixed data, the volume involved often makes it inconve-           m: Data Memory address
nient to store the fixed data in the Data Memory. To over-        A: Accumulator
come this problem, Holtek microcontrollers allow an               i: 0~7 number of bits
area of Program Memory to be setup as a table where               addr: Program memory address
data can be directly stored. A set of easy to use instruc-
tions provides the means by which this fixed data can be
referenced and retrieved from the Program Memory.



   Mnemonic                                     Description                                   Cycles       Flag Affected
 Arithmetic
 ADD A,[m]        Add Data Memory to ACC                                                         1         Z, C, AC, OV
 ADDM A,[m]       Add ACC to Data Memory                                                        1Note      Z, C, AC, OV
 ADD A,x          Add immediate data to ACC                                                      1         Z, C, AC, OV
 ADC A,[m]        Add Data Memory to ACC with Carry                                              1         Z, C, AC, OV
 ADCM A,[m]       Add ACC to Data memory with Carry                                             1Note      Z, C, AC, OV
 SUB A,x          Subtract immediate data from the ACC                                           1         Z, C, AC, OV
 SUB A,[m]        Subtract Data Memory from ACC                                                  1         Z, C, AC, OV
 SUBM A,[m]       Subtract Data Memory from ACC with result in Data Memory                      1Note      Z, C, AC, OV
 SBC A,[m]        Subtract Data Memory from ACC with Carry                                       1         Z, C, AC, OV
 SBCM A,[m]       Subtract Data Memory from ACC with Carry, result in Data Memory               1Note      Z, C, AC, OV
 DAA [m]          Decimal adjust ACC for Addition with result in Data Memory                    1Note            C
 Logic Operation
 AND A,[m]        Logical AND Data Memory to ACC                                                 1               Z
 OR A,[m]         Logical OR Data Memory to ACC                                                  1               Z
 XOR A,[m]        Logical XOR Data Memory to ACC                                                 1               Z
 ANDM A,[m]       Logical AND ACC to Data Memory                                                1Note            Z
 ORM A,[m]        Logical OR ACC to Data Memory                                                 1Note            Z
 XORM A,[m]       Logical XOR ACC to Data Memory                                                1Note            Z
 AND A,x          Logical AND immediate Data to ACC                                              1               Z
 OR A,x           Logical OR immediate Data to ACC                                               1               Z
 XOR A,x          Logical XOR immediate Data to ACC                                              1               Z
 CPL [m]          Complement Data Memory                                                        1Note            Z
 CPLA [m]         Complement Data Memory with result in ACC                                      1               Z
 Increment & Decrement
 INCA [m]         Increment Data Memory with result in ACC                                       1               Z
 INC [m]          Increment Data Memory                                                         1Note            Z
 DECA [m]         Decrement Data Memory with result in ACC                                       1               Z
 DEC [m]          Decrement Data Memory                                                         1Note            Z


Rev. 1.00                                                    74                                         September 21, 2010
                                                                                         HT45R52/HT45R54

  Mnemonic                                     Description                                  Cycles       Flag Affected
 Rotate
 RRA [m]          Rotate Data Memory right with result in ACC                                  1             None
 RR [m]           Rotate Data Memory right                                                    1Note          None
 RRCA [m]         Rotate Data Memory right through Carry with result in ACC                    1              C
 RRC [m]          Rotate Data Memory right through Carry                                      1Note           C
 RLA [m]          Rotate Data Memory left with result in ACC                                   1             None
 RL [m]           Rotate Data Memory left                                                     1Note          None
 RLCA [m]         Rotate Data Memory left through Carry with result in ACC                     1              C
 RLC [m]          Rotate Data Memory left through Carry                                       1Note           C
 Data Move
 MOV A,[m]        Move Data Memory to ACC                                                      1             None
 MOV [m],A        Move ACC to Data Memory                                                     1Note          None
 MOV A,x          Move immediate data to ACC                                                   1             None
 Bit Operation
 CLR [m].i        Clear bit of Data Memory                                                    1Note          None
 SET [m].i        Set bit of Data Memory                                                      1Note          None
 Branch
 JMP addr         Jump unconditionally                                                         2             None
 SZ [m]           Skip if Data Memory is zero                                                 1Note          None
 SZA [m]          Skip if Data Memory is zero with data movement to ACC                       1note          None
 SZ [m].i         Skip if bit i of Data Memory is zero                                        1Note          None
 SNZ [m].i        Skip if bit i of Data Memory is not zero                                    1Note          None
 SIZ [m]          Skip if increment Data Memory is zero                                       1Note          None
 SDZ [m]          Skip if decrement Data Memory is zero                                       1Note          None
 SIZA [m]         Skip if increment Data Memory is zero with result in ACC                    1Note          None
 SDZA [m]         Skip if decrement Data Memory is zero with result in ACC                    1Note          None
 CALL addr        Subroutine call                                                              2             None
 RET              Return from subroutine                                                       2             None
 RET A,x          Return from subroutine and load immediate data to ACC                        2             None
 RETI             Return from interrupt                                                        2             None
 Table Read
 TABRDC [m]       Read table (current page) to TBLH and Data Memory                           2Note          None
 TABRDL [m]       Read table (last page) to TBLH and Data Memory                              2Note          None
 Miscellaneous
 NOP              No operation                                                                 1            None
 CLR [m]          Clear Data Memory                                                           1Note         None
 SET [m]          Set Data Memory                                                             1Note         None
 CLR WDT          Clear Watchdog Timer                                                         1           TO, PDF
 CLR WDT1         Pre-clear Watchdog Timer                                                     1           TO, PDF
 CLR WDT2         Pre-clear Watchdog Timer                                                     1           TO, PDF
 SWAP [m]         Swap nibbles of Data Memory                                                 1Note         None
 SWAPA [m]        Swap nibbles of Data Memory with result in ACC                               1            None
 HALT             Enter power down mode                                                        1           TO, PDF

Note:   1. For skip instructions, if the result of the comparison involves a skip then two cycles are required,
           if no skip takes place only one cycle is required.
        2. Any instruction which changes the contents of the PCL will also require 2 cycles for execution.
        3. For the ²CLR WDT1² and ²CLR WDT2² instructions the TO and PDF flags may be affected by
           the execution status. The TO and PDF flags are cleared after both ²CLR WDT1² and
           ²CLR WDT2² instructions are consecutively executed. Otherwise the TO and PDF flags
           remain unchanged.




Rev. 1.00                                                 75                                          September 21, 2010
                                                                               HT45R52/HT45R54

Instruction Definition

ADC A,[m]            Add Data Memory to ACC with Carry
Description          The contents of the specified Data Memory, Accumulator and the carry flag are added. The
                     result is stored in the Accumulator.
Operation            ACC ¬ ACC + [m] + C
Affected flag(s)     OV, Z, AC, C

ADCM A,[m]           Add ACC to Data Memory with Carry
Description          The contents of the specified Data Memory, Accumulator and the carry flag are added. The
                     result is stored in the specified Data Memory.
Operation            [m] ¬ ACC + [m] + C
Affected flag(s)     OV, Z, AC, C

ADD A,[m]            Add Data Memory to ACC
Description          The contents of the specified Data Memory and the Accumulator are added. The result is
                     stored in the Accumulator.
Operation            ACC ¬ ACC + [m]
Affected flag(s)     OV, Z, AC, C

ADD A,x              Add immediate data to ACC
Description          The contents of the Accumulator and the specified immediate data are added. The result is
                     stored in the Accumulator.
Operation            ACC ¬ ACC + x
Affected flag(s)     OV, Z, AC, C

ADDM A,[m]           Add ACC to Data Memory
Description          The contents of the specified Data Memory and the Accumulator are added. The result is
                     stored in the specified Data Memory.
Operation            [m] ¬ ACC + [m]
Affected flag(s)     OV, Z, AC, C

AND A,[m]            Logical AND Data Memory to ACC
Description          Data in the Accumulator and the specified Data Memory perform a bitwise logical AND op-
                     eration. The result is stored in the Accumulator.
Operation            ACC ¬ ACC ²AND² [m]
Affected flag(s)     Z

AND A,x              Logical AND immediate data to ACC
Description          Data in the Accumulator and the specified immediate data perform a bitwise logical AND
                     operation. The result is stored in the Accumulator.
Operation            ACC ¬ ACC ²AND² x
Affected flag(s)     Z

ANDM A,[m]           Logical AND ACC to Data Memory
Description          Data in the specified Data Memory and the Accumulator perform a bitwise logical AND op-
                     eration. The result is stored in the Data Memory.
Operation            [m] ¬ ACC ²AND² [m]
Affected flag(s)     Z


Rev. 1.00                                         76                                     September 21, 2010
                                                                                HT45R52/HT45R54

CALL addr          Subroutine call
Description        Unconditionally calls a subroutine at the specified address. The Program Counter then in-
                   crements by 1 to obtain the address of the next instruction which is then pushed onto the
                   stack. The specified address is then loaded and the program continues execution from this
                   new address. As this instruction requires an additional operation, it is a two cycle instruc-
                   tion.
Operation          Stack ¬ Program Counter + 1
                   Program Counter ¬ addr
Affected flag(s)   None

CLR [m]            Clear Data Memory
Description        Each bit of the specified Data Memory is cleared to 0.
Operation          [m] ¬ 00H
Affected flag(s)   None

CLR [m].i          Clear bit of Data Memory
Description        Bit i of the specified Data Memory is cleared to 0.
Operation          [m].i ¬ 0
Affected flag(s)   None

CLR WDT            Clear Watchdog Timer
Description        The TO, PDF flags and the WDT are all cleared.
Operation          WDT cleared
                   TO ¬ 0
                   PDF ¬ 0
Affected flag(s)   TO, PDF

CLR WDT1           Pre-clear Watchdog Timer
Description        The TO, PDF flags and the WDT are all cleared. Note that this instruction works in conjunc-
                   tion with CLR WDT2 and must be executed alternately with CLR WDT2 to have effect. Re-
                   petitively executing this instruction without alternately executing CLR WDT2 will have no
                   effect.
Operation          WDT cleared
                   TO ¬ 0
                   PDF ¬ 0
Affected flag(s)   TO, PDF

CLR WDT2           Pre-clear Watchdog Timer
Description        The TO, PDF flags and the WDT are all cleared. Note that this instruction works in conjunc-
                   tion with CLR WDT1 and must be executed alternately with CLR WDT1 to have effect. Re-
                   petitively executing this instruction without alternately executing CLR WDT1 will have no
                   effect.
Operation          WDT cleared
                   TO ¬ 0
                   PDF ¬ 0
Affected flag(s)   TO, PDF




Rev. 1.00                                        77                                       September 21, 2010
                                                                                  HT45R52/HT45R54

CPL [m]            Complement Data Memory
Description        Each bit of the specified Data Memory is logically complemented (1¢s complement). Bits
                   which previously contained a 1 are changed to 0 and vice versa.
Operation          [m] ¬ [m]
Affected flag(s)   Z

CPLA [m]           Complement Data Memory with result in ACC
Description        Each bit of the specified Data Memory is logically complemented (1¢s complement). Bits
                   which previously contained a 1 are changed to 0 and vice versa. The complemented result
                   is stored in the Accumulator and the contents of the Data Memory remain unchanged.
Operation          ACC ¬ [m]
Affected flag(s)   Z

DAA [m]            Decimal-Adjust ACC for addition with result in Data Memory
Description        Convert the contents of the Accumulator value to a BCD ( Binary Coded Decimal) value re-
                   sulting from the previous addition of two BCD variables. If the low nibble is greater than 9 or
                   if AC flag is set, then a value of 6 will be added to the low nibble. Otherwise the low nibble
                   remains unchanged. If the high nibble is greater than 9 or if the C flag is set, then a value of
                   6 will be added to the high nibble. Essentially, the decimal conversion is performed by add-
                   ing 00H, 06H, 60H or 66H depending on the Accumulator and flag conditions. Only the C
                   flag may be affected by this instruction which indicates that if the original BCD sum is
                   greater than 100, it allows multiple precision decimal addition.
Operation          [m] ¬ ACC + 00H or
                   [m] ¬ ACC + 06H or
                   [m] ¬ ACC + 60H or
                   [m] ¬ ACC + 66H
Affected flag(s)   C

DEC [m]            Decrement Data Memory
Description        Data in the specified Data Memory is decremented by 1.
Operation          [m] ¬ [m] - 1
Affected flag(s)   Z

DECA [m]           Decrement Data Memory with result in ACC
Description        Data in the specified Data Memory is decremented by 1. The result is stored in the Accu-
                   mulator. The contents of the Data Memory remain unchanged.
Operation          ACC ¬ [m] - 1
Affected flag(s)   Z

HALT               Enter power down mode
Description        This instruction stops the program execution and turns off the system clock. The contents
                   of the Data Memory and registers are retained. The WDT and prescaler are cleared. The
                   power down flag PDF is set and the WDT time-out flag TO is cleared.
Operation          TO ¬ 0
                   PDF ¬ 1
Affected flag(s)   TO, PDF




Rev. 1.00                                         78                                        September 21, 2010
                                                                              HT45R52/HT45R54

INC [m]            Increment Data Memory
Description        Data in the specified Data Memory is incremented by 1.
Operation          [m] ¬ [m] + 1
Affected flag(s)   Z

INCA [m]           Increment Data Memory with result in ACC
Description        Data in the specified Data Memory is incremented by 1. The result is stored in the Accumu-
                   lator. The contents of the Data Memory remain unchanged.
Operation          ACC ¬ [m] + 1
Affected flag(s)   Z

JMP addr           Jump unconditionally
Description        The contents of the Program Counter are replaced with the specified address. Program
                   execution then continues from this new address. As this requires the insertion of a dummy
                   instruction while the new address is loaded, it is a two cycle instruction.
Operation          Program Counter ¬ addr
Affected flag(s)   None

MOV A,[m]          Move Data Memory to ACC
Description        The contents of the specified Data Memory are copied to the Accumulator.
Operation          ACC ¬ [m]
Affected flag(s)   None

MOV A,x            Move immediate data to ACC
Description        The immediate data specified is loaded into the Accumulator.
Operation          ACC ¬ x
Affected flag(s)   None

MOV [m],A          Move ACC to Data Memory
Description        The contents of the Accumulator are copied to the specified Data Memory.
Operation          [m] ¬ ACC
Affected flag(s)   None

NOP                No operation
Description        No operation is performed. Execution continues with the next instruction.
Operation          No operation
Affected flag(s)   None

OR A,[m]           Logical OR Data Memory to ACC
Description        Data in the Accumulator and the specified Data Memory perform a bitwise logical OR oper-
                   ation. The result is stored in the Accumulator.
Operation          ACC ¬ ACC ²OR² [m]
Affected flag(s)   Z




Rev. 1.00                                       79                                      September 21, 2010
                                                                                 HT45R52/HT45R54

OR A,x             Logical OR immediate data to ACC
Description        Data in the Accumulator and the specified immediate data perform a bitwise logical OR op-
                   eration. The result is stored in the Accumulator.
Operation          ACC ¬ ACC ²OR² x
Affected flag(s)   Z

ORM A,[m]          Logical OR ACC to Data Memory
Description        Data in the specified Data Memory and the Accumulator perform a bitwise logical OR oper-
                   ation. The result is stored in the Data Memory.
Operation          [m] ¬ ACC ²OR² [m]
Affected flag(s)   Z

RET                Return from subroutine
Description        The Program Counter is restored from the stack. Program execution continues at the re-
                   stored address.
Operation          Program Counter ¬ Stack
Affected flag(s)   None

RET A,x            Return from subroutine and load immediate data to ACC
Description        The Program Counter is restored from the stack and the Accumulator loaded with the
                   specified immediate data. Program execution continues at the restored address.
Operation          Program Counter ¬ Stack
                   ACC ¬ x
Affected flag(s)   None

RETI               Return from interrupt
Description        The Program Counter is restored from the stack and the interrupts are re-enabled by set-
                   ting the EMI bit. EMI is the master interrupt global enable bit. If an interrupt was pending
                   when the RETI instruction is executed, the pending Interrupt routine will be processed be-
                   fore returning to the main program.
Operation          Program Counter ¬ Stack
                   EMI ¬ 1
Affected flag(s)   None

RL [m]             Rotate Data Memory left
Description        The contents of the specified Data Memory are rotated left by 1 bit with bit 7 rotated into bit
                   0.
Operation          [m].(i+1) ¬ [m].i; (i = 0~6)
                   [m].0 ¬ [m].7
Affected flag(s)   None

RLA [m]            Rotate Data Memory left with result in ACC
Description        The contents of the specified Data Memory are rotated left by 1 bit with bit 7 rotated into bit
                   0. The rotated result is stored in the Accumulator and the contents of the Data Memory re-
                   main unchanged.
Operation          ACC.(i+1) ¬ [m].i; (i = 0~6)
                   ACC.0 ¬ [m].7
Affected flag(s)   None




Rev. 1.00                                         80                                       September 21, 2010
                                                                                     HT45R52/HT45R54

RLC [m]            Rotate Data Memory left through Carry
Description        The contents of the specified Data Memory and the carry flag are rotated left by 1 bit. Bit 7
                   replaces the Carry bit and the original carry flag is rotated into bit 0.
Operation          [m].(i+1) ¬ [m].i; (i = 0~6)
                   [m].0 ¬ C
                   C ¬ [m].7
Affected flag(s)   C

RLCA [m]           Rotate Data Memory left through Carry with result in ACC
Description        Data in the specified Data Memory and the carry flag are rotated left by 1 bit. Bit 7 replaces
                   the Carry bit and the original carry flag is rotated into the bit 0. The rotated result is stored in
                   the Accumulator and the contents of the Data Memory remain unchanged.
Operation          ACC.(i+1) ¬ [m].i; (i = 0~6)
                   ACC.0 ¬ C
                   C ¬ [m].7
Affected flag(s)   C

RR [m]             Rotate Data Memory right
Description        The contents of the specified Data Memory are rotated right by 1 bit with bit 0 rotated into
                   bit 7.
Operation          [m].i ¬ [m].(i+1); (i = 0~6)
                   [m].7 ¬ [m].0
Affected flag(s)   None

RRA [m]            Rotate Data Memory right with result in ACC
Description        Data in the specified Data Memory and the carry flag are rotated right by 1 bit with bit 0 ro-
                   tated into bit 7. The rotated result is stored in the Accumulator and the contents of the Data
                   Memory remain unchanged.
Operation          ACC.i ¬ [m].(i+1); (i = 0~6)
                   ACC.7 ¬ [m].0
Affected flag(s)   None

RRC [m]            Rotate Data Memory right through Carry
Description        The contents of the specified Data Memory and the carry flag are rotated right by 1 bit. Bit 0
                   replaces the Carry bit and the original carry flag is rotated into bit 7.
Operation          [m].i ¬ [m].(i+1); (i = 0~6)
                   [m].7 ¬ C
                   C ¬ [m].0
Affected flag(s)   C

RRCA [m]           Rotate Data Memory right through Carry with result in ACC
Description        Data in the specified Data Memory and the carry flag are rotated right by 1 bit. Bit 0 re-
                   places the Carry bit and the original carry flag is rotated into bit 7. The rotated result is
                   stored in the Accumulator and the contents of the Data Memory remain unchanged.
Operation          ACC.i ¬ [m].(i+1); (i = 0~6)
                   ACC.7 ¬ C
                   C ¬ [m].0
Affected flag(s)   C




Rev. 1.00                                          81                                          September 21, 2010
                                                                                     HT45R52/HT45R54

SBC A,[m]          Subtract Data Memory from ACC with Carry
Description        The contents of the specified Data Memory and the complement of the carry flag are sub-
                   tracted from the Accumulator. The result is stored in the Accumulator. Note that if the result
                   of subtraction is negative, the C flag will be cleared to 0, otherwise if the result is positive or
                   zero, the C flag will be set to 1.
Operation          ACC ¬ ACC - [m] - C
Affected flag(s)   OV, Z, AC, C

SBCM A,[m]         Subtract Data Memory from ACC with Carry and result in Data Memory
Description        The contents of the specified Data Memory and the complement of the carry flag are sub-
                   tracted from the Accumulator. The result is stored in the Data Memory. Note that if the re-
                   sult of subtraction is negative, the C flag will be cleared to 0, otherwise if the result is
                   positive or zero, the C flag will be set to 1.
Operation          [m] ¬ ACC - [m] - C
Affected flag(s)   OV, Z, AC, C

SDZ [m]            Skip if decrement Data Memory is 0
Description        The contents of the specified Data Memory are first decremented by 1. If the result is 0 the
                   following instruction is skipped. As this requires the insertion of a dummy instruction while
                   the next instruction is fetched, it is a two cycle instruction. If the result is not 0 the program
                   proceeds with the following instruction.
Operation          [m] ¬ [m] - 1
                   Skip if [m] = 0
Affected flag(s)   None

SDZA [m]           Skip if decrement Data Memory is zero with result in ACC
Description        The contents of the specified Data Memory are first decremented by 1. If the result is 0, the
                   following instruction is skipped. The result is stored in the Accumulator but the specified
                   Data Memory contents remain unchanged. As this requires the insertion of a dummy in-
                   struction while the next instruction is fetched, it is a two cycle instruction. If the result is not
                   0, the program proceeds with the following instruction.
Operation          ACC ¬ [m] - 1
                   Skip if ACC = 0
Affected flag(s)   None

SET [m]            Set Data Memory
Description        Each bit of the specified Data Memory is set to 1.
Operation          [m] ¬ FFH
Affected flag(s)   None

SET [m].i          Set bit of Data Memory
Description        Bit i of the specified Data Memory is set to 1.
Operation          [m].i ¬ 1
Affected flag(s)   None




Rev. 1.00                                          82                                          September 21, 2010
                                                                                     HT45R52/HT45R54

SIZ [m]            Skip if increment Data Memory is 0
Description        The contents of the specified Data Memory are first incremented by 1. If the result is 0, the
                   following instruction is skipped. As this requires the insertion of a dummy instruction while
                   the next instruction is fetched, it is a two cycle instruction. If the result is not 0 the program
                   proceeds with the following instruction.
Operation          [m] ¬ [m] + 1
                   Skip if [m] = 0
Affected flag(s)   None

SIZA [m]           Skip if increment Data Memory is zero with result in ACC
Description        The contents of the specified Data Memory are first incremented by 1. If the result is 0, the
                   following instruction is skipped. The result is stored in the Accumulator but the specified
                   Data Memory contents remain unchanged. As this requires the insertion of a dummy in-
                   struction while the next instruction is fetched, it is a two cycle instruction. If the result is not
                   0 the program proceeds with the following instruction.
Operation          ACC ¬ [m] + 1
                   Skip if ACC = 0
Affected flag(s)   None

SNZ [m].i          Skip if bit i of Data Memory is not 0
Description        If bit i of the specified Data Memory is not 0, the following instruction is skipped. As this re-
                   quires the insertion of a dummy instruction while the next instruction is fetched, it is a two
                   cycle instruction. If the result is 0 the program proceeds with the following instruction.
Operation          Skip if [m].i ¹ 0
Affected flag(s)   None

SUB A,[m]          Subtract Data Memory from ACC
Description        The specified Data Memory is subtracted from the contents of the Accumulator. The result
                   is stored in the Accumulator. Note that if the result of subtraction is negative, the C flag will
                   be cleared to 0, otherwise if the result is positive or zero, the C flag will be set to 1.
Operation          ACC ¬ ACC - [m]
Affected flag(s)   OV, Z, AC, C

SUBM A,[m]         Subtract Data Memory from ACC with result in Data Memory
Description        The specified Data Memory is subtracted from the contents of the Accumulator. The result
                   is stored in the Data Memory. Note that if the result of subtraction is negative, the C flag will
                   be cleared to 0, otherwise if the result is positive or zero, the C flag will be set to 1.
Operation          [m] ¬ ACC - [m]
Affected flag(s)   OV, Z, AC, C

SUB A,x            Subtract immediate data from ACC
Description        The immediate data specified by the code is subtracted from the contents of the Accumu-
                   lator. The result is stored in the Accumulator. Note that if the result of subtraction is nega-
                   tive, the C flag will be cleared to 0, otherwise if the result is positive or zero, the C flag will
                   be set to 1.
Operation          ACC ¬ ACC - x
Affected flag(s)   OV, Z, AC, C




Rev. 1.00                                          83                                          September 21, 2010
                                                                                     HT45R52/HT45R54

SWAP [m]           Swap nibbles of Data Memory
Description        The low-order and high-order nibbles of the specified Data Memory are interchanged.
Operation          [m].3~[m].0 « [m].7 ~ [m].4
Affected flag(s)   None

SWAPA [m]          Swap nibbles of Data Memory with result in ACC
Description        The low-order and high-order nibbles of the specified Data Memory are interchanged. The
                   result is stored in the Accumulator. The contents of the Data Memory remain unchanged.
Operation          ACC.3 ~ ACC.0 ¬ [m].7 ~ [m].4
                   ACC.7 ~ ACC.4 ¬ [m].3 ~ [m].0
Affected flag(s)   None

SZ [m]             Skip if Data Memory is 0
Description        If the contents of the specified Data Memory is 0, the following instruction is skipped. As
                   this requires the insertion of a dummy instruction while the next instruction is fetched, it is a
                   two cycle instruction. If the result is not 0 the program proceeds with the following instruc-
                   tion.
Operation          Skip if [m] = 0
Affected flag(s)   None

SZA [m]            Skip if Data Memory is 0 with data movement to ACC
Description        The contents of the specified Data Memory are copied to the Accumulator. If the value is
                   zero, the following instruction is skipped. As this requires the insertion of a dummy instruc-
                   tion while the next instruction is fetched, it is a two cycle instruction. If the result is not 0 the
                   program proceeds with the following instruction.
Operation          ACC ¬ [m]
                   Skip if [m] = 0
Affected flag(s)   None

SZ [m].i           Skip if bit i of Data Memory is 0
Description        If bit i of the specified Data Memory is 0, the following instruction is skipped. As this re-
                   quires the insertion of a dummy instruction while the next instruction is fetched, it is a two
                   cycle instruction. If the result is not 0, the program proceeds with the following instruction.
Operation          Skip if [m].i = 0
Affected flag(s)   None

TABRDC [m]         Read table (current page) to TBLH and Data Memory
Description        The low byte of the program code (current page) addressed by the table pointer (TBLP) is
                   moved to the specified Data Memory and the high byte moved to TBLH.
Operation          [m] ¬ program code (low byte)
                   TBLH ¬ program code (high byte)
Affected flag(s)   None

TABRDL [m]         Read table (last page) to TBLH and Data Memory
Description        The low byte of the program code (last page) addressed by the table pointer (TBLP) is
                   moved to the specified Data Memory and the high byte moved to TBLH.
Operation          [m] ¬ program code (low byte)
                   TBLH ¬ program code (high byte)
Affected flag(s)   None



Rev. 1.00                                           84                                          September 21, 2010
                                                                            HT45R52/HT45R54

XOR A,[m]          Logical XOR Data Memory to ACC
Description        Data in the Accumulator and the specified Data Memory perform a bitwise logical XOR op-
                   eration. The result is stored in the Accumulator.
Operation          ACC ¬ ACC ²XOR² [m]
Affected flag(s)   Z

XORM A,[m]         Logical XOR ACC to Data Memory
Description        Data in the specified Data Memory and the Accumulator perform a bitwise logical XOR op-
                   eration. The result is stored in the Data Memory.
Operation          [m] ¬ ACC ²XOR² [m]
Affected flag(s)   Z

XOR A,x            Logical XOR immediate data to ACC
Description        Data in the Accumulator and the specified immediate data perform a bitwise logical XOR
                   operation. The result is stored in the Accumulator.
Operation          ACC ¬ ACC ²XOR² x
Affected flag(s)   Z




Rev. 1.00                                      85                                    September 21, 2010
                                                                                                         HT45R52/HT45R54

Package Information
20-pin DIP (300mil) Outline Dimensions
                             A                                                                   A

         2 0                         1 1                                   2 0                           1 1
     B                                                             B
         1                           1 0                               1                                 1 0




                                                  H                                                                      H

 C                                                             C

 D                                                             D

               E         F       G                    I                          E           F       G                       I



                     Fig1. Full Lead Packages                                               Fig2. 1/2 Lead Packages


· MS-001d (see fig1)

                                                               Dimensions in inch
                   Symbol
                                                Min.                                 Nom.                        Max.
                     A                      0.980                                     ¾                          1.060
                     B                      0.240                                     ¾                          0.280
                     C                      0.115                                     ¾                          0.195
                     D                      0.115                                     ¾                          0.150
                     E                      0.014                                     ¾                          0.022
                     F                      0.045                                     ¾                          0.070
                     G                          ¾                                    0.100                         ¾
                     H                      0.300                                     ¾                          0.325
                     I                          ¾                                    0.430                         ¾

                                                               Dimensions in mm
                   Symbol
                                                Min.                                 Nom.                        Max.
                     A                      24.89                                     ¾                          26.92
                     B                          6.10                                  ¾                           7.11
                     C                          2.92                                  ¾                           4.95
                     D                          2.92                                  ¾                           3.81
                     E                          0.36                                  ¾                           0.56
                     F                          1.14                                  ¾                           1.78
                     G                          ¾                                    2.54                          ¾
                     H                          7.62                                  ¾                           8.26
                     I                          ¾                                    10.92                         ¾




Rev. 1.00                                                 86                                                   September 21, 2010
                                                         HT45R52/HT45R54

· MO-095a (see fig2)

                                    Dimensions in inch
            Symbol
                       Min.               Nom.                 Max.
              A        0.945                ¾                  0.985
              B        0.275                ¾                  0.295
              C        0.120                ¾                  0.150
              D        0.110                ¾                  0.150
              E        0.014                ¾                  0.022
              F        0.045                ¾                  0.060
              G         ¾                 0.100                  ¾
              H        0.300                ¾                  0.325
              I         ¾                 0.430                  ¾

                                    Dimensions in mm
            Symbol
                       Min.               Nom.                 Max.
              A        24.00                ¾                  25.02
              B        6.99                 ¾                   7.49
              C        3.05                 ¾                   3.81
              D        2.79                 ¾                   3.81
              E        0.36                 ¾                   0.56
              F        1.14                 ¾                   1.52
              G         ¾                  2.54                  ¾
              H        7.62                 ¾                   8.26
              I         ¾                 10.92                  ¾




Rev. 1.00                      87                            September 21, 2010
                                                                                         HT45R52/HT45R54

20-pin SOP (300mil) Outline Dimensions




                           2 0                 1 1

                       A                                   B

                           1                   1 0


                                     C


                                         C '
                                                                            G
                   D                                                                        H

                                 E                     F                        a


· MS-013

                                                                    Dimensions in inch
            Symbol
                                                     Min.                 Nom.                    Max.
              A                                      0.393                  ¾                     0.419
              B                                      0.256                  ¾                     0.300
              C                                      0.012                  ¾                     0.020
              C¢                                     0.496                  ¾                     0.512
              D                                       ¾                     ¾                     0.104
              E                                       ¾                   0.050                     ¾
              F                                      0.004                  ¾                     0.012
              G                                      0.016                  ¾                     0.050
              H                                      0.008                  ¾                     0.013
              a                                       0°                    ¾                       8°

                                                                    Dimensions in mm
            Symbol
                                                     Min.                 Nom.                    Max.
              A                                      9.98                   ¾                     10.64
              B                                      6.50                   ¾                      7.62
              C                                      0.30                   ¾                      0.51
              C¢                                     12.60                  ¾                     13.00
              D                                       ¾                     ¾                      2.64
              E                                       ¾                    1.27                     ¾
              F                                      0.10                   ¾                      0.30
              G                                      0.41                   ¾                      1.27
              H                                      0.20                   ¾                      0.33
              a                                       0°                    ¾                       8°




Rev. 1.00                                                      88                               September 21, 2010
                                                                                                              HT45R52/HT45R54

24-pin SKDIP (300mil) Outline Dimensions

                                 A                                                                    A

             2 4                         1 3                                       2 4                          1 3
 B                                                                     B
         1                               1 2                                   1                                1 2




                                                        H                                                                       H

     C                                                                     C
     D                                                                     D
                   E     F           G                      I                            E        F       G                         I


                         Fig1. Full Lead Packages                                                Fig2. 1/2 Lead Packages


· MS-001d (see fig1)

                                                                     Dimensions in inch
                       Symbol
                                                    Min.                            Nom.                                Max.
                         A                      1.230                                        ¾                          1.280
                         B                      0.240                                        ¾                          0.280
                         C                      0.115                                        ¾                          0.195
                         D                      0.115                                        ¾                          0.150
                         E                      0.014                                        ¾                          0.022
                         F                      0.045                                        ¾                          0.070
                         G                          ¾                               0.100                                 ¾
                         H                      0.300                                        ¾                          0.325
                             I                      ¾                               0.430                                 ¾

                                                                     Dimensions in mm
                       Symbol
                                                    Min.                            Nom.                                Max.
                         A                      31.24                                        ¾                          32.51
                         B                          6.10                                     ¾                           7.11
                         C                          2.92                                     ¾                           4.95
                         D                          2.92                                     ¾                           3.81
                         E                          0.36                                     ¾                           0.56
                         F                          1.14                                     ¾                           1.78
                         G                          ¾                                    2.54                             ¾
                         H                          7.62                                     ¾                           8.26
                             I                      ¾                               10.92                                 ¾




Rev. 1.00                                                       89                                                    September 21, 2010
                                                         HT45R52/HT45R54

· MS-001d (see fig2)

                                    Dimensions in inch
            Symbol
                       Min.               Nom.                 Max.
              A        1.160                ¾                  1.195
              B        0.240                ¾                  0.280
              C        0.115                ¾                  0.195
              D        0.115                ¾                  0.150
              E        0.014                ¾                  0.022
              F        0.045                ¾                  0.070
              G         ¾                 0.100                  ¾
              H        0.300                ¾                  0.325
              I         ¾                 0.430                  ¾

                                    Dimensions in mm
            Symbol
                       Min.               Nom.                 Max.
              A        29.46                ¾                  30.35
              B        6.10                 ¾                   7.11
              C        2.92                 ¾                   4.95
              D        2.92                 ¾                   3.81
              E        0.36                 ¾                   0.56
              F        1.14                 ¾                   1.78
              G         ¾                  2.54                  ¾
              H        7.62                 ¾                   8.26
              I         ¾                 10.92                  ¾




Rev. 1.00                      90                            September 21, 2010
                                                         HT45R52/HT45R54

· MO-095a (see fig2)

                                    Dimensions in inch
            Symbol
                       Min.               Nom.                 Max.
              A        1.145                ¾                  1.185
              B        0.275                ¾                  0.295
              C        0.120                ¾                  0.150
              D        0.110                ¾                  0.150
              E        0.014                ¾                  0.022
              F        0.045                ¾                  0.060
              G         ¾                 0.100                  ¾
              H        0.300                ¾                  0.325
              I         ¾                 0.430                  ¾

                                    Dimensions in mm
            Symbol
                       Min.               Nom.                 Max.
              A        29.08                ¾                  30.10
              B        6.99                 ¾                   7.49
              C        3.05                 ¾                   3.81
              D        2.79                 ¾                   3.81
              E        0.36                 ¾                   0.56
              F        1.14                 ¾                   1.52
              G         ¾                  2.54                  ¾
              H        7.62                 ¾                   8.26
              I         ¾                 10.92                  ¾




Rev. 1.00                      91                            September 21, 2010
                                                                                                 HT45R52/HT45R54

24-pin SOP (300mil) Outline Dimensions




                               2 4                       1 3

                       A                                           B

                           1                             1 2



                                     C


                                             C '
                                                                                     G
                   D                                                                                 H

                                         E                     F                          a


· MS-013

                                                                            Dimensions in inch
            Symbol
                                                   Min.                           Nom.                     Max.
              A                                    0.393                            ¾                      0.419
              B                                    0.256                            ¾                      0.300
              C                                    0.012                            ¾                      0.020
              C¢                                   0.598                            ¾                      0.613
              D                                     ¾                               ¾                      0.104
              E                                     ¾                             0.050                      ¾
              F                                    0.004                            ¾                      0.012
              G                                    0.016                            ¾                      0.050
              H                                    0.008                            ¾                      0.013
              a                                     0°                              ¾                        8°

                                                                            Dimensions in mm
            Symbol
                                                   Min.                           Nom.                     Max.
              A                                    9.98                             ¾                      10.64
              B                                    6.50                             ¾                       7.62
              C                                    0.30                             ¾                       0.51
              C¢                                   15.19                            ¾                      15.57
              D                                     ¾                               ¾                       2.64
              E                                     ¾                              1.27                      ¾
              F                                    0.10                             ¾                       0.30
              G                                    0.41                             ¾                       1.27
              H                                    0.20                             ¾                       0.33
              a                                     0°                              ¾                        8°




Rev. 1.00                                                              92                                September 21, 2010
                                                                                           HT45R52/HT45R54

28-pin SKDIP (300mil) Outline Dimensions




                                           A

                             2 8                           1 5
                         B
                              1                            1 4




                                                                                           H

                     C

                     D
                                                                                               I
                                   E   F               G




                                                                      Dimensions in inch
            Symbol
                                               Min.                         Nom.                     Max.
              A                                1.375                          ¾                      1.395
              B                                0.278                          ¾                      0.298
              C                                0.125                          ¾                      0.135
              D                                0.125                          ¾                      0.145
              E                                0.016                          ¾                      0.020
              F                                0.050                          ¾                      0.070
              G                                 ¾                           0.100                      ¾
              H                                0.295                          ¾                      0.315
              I                                 ¾                           0.375                      ¾

                                                                      Dimensions in mm
            Symbol
                                               Min.                         Nom.                     Max.
              A                                34.93                          ¾                      35.43
              B                                7.06                           ¾                       7.57
              C                                3.18                           ¾                       3.43
              D                                3.18                           ¾                       3.68
              E                                0.41                           ¾                       0.51
              F                                1.27                           ¾                       1.78
              G                                 ¾                            2.54                      ¾
              H                                7.49                           ¾                       8.00
              I                                 ¾                            9.53                      ¾




Rev. 1.00                                                        93                                September 21, 2010
                                                                                                   HT45R52/HT45R54

28-pin SOP (300mil) Outline Dimensions




                               2 8                         1 5

                       A                                             B

                           1                               1 4


                                     C


                                             C '
                                                                                      G
                   D                                                                                  H

                                         E                       F                        a



· MS-013

                                                                              Dimensions in inch
            Symbol
                                                   Min.                             Nom.                    Max.
              A                                    0.393                              ¾                     0.419
              B                                    0.256                              ¾                     0.300
              C                                    0.012                              ¾                     0.020
              C¢                                   0.697                              ¾                     0.713
              D                                     ¾                                 ¾                     0.104
              E                                     ¾                               0.050                     ¾
              F                                    0.004                              ¾                     0.012
              G                                    0.016                              ¾                     0.050
              H                                    0.008                              ¾                     0.013
              a                                     0°                                ¾                       8°

                                                                              Dimensions in mm
            Symbol
                                                   Min.                             Nom.                    Max.
              A                                    9.98                               ¾                     10.64
              B                                    6.50                               ¾                      7.62
              C                                    0.30                               ¾                      0.51
              C¢                                   17.70                              ¾                     18.11
              D                                     ¾                                 ¾                      2.64
              E                                     ¾                                1.27                     ¾
              F                                    0.10                               ¾                      0.30
              G                                    0.41                               ¾                      1.27
              H                                    0.20                               ¾                      0.33
              a                                     0°                                ¾                       8°




Rev. 1.00                                                                94                               September 21, 2010
                                                               HT45R52/HT45R54

Product Tape and Reel Specifications
Reel Dimensions

                                                       D
                          T 2




             A     B                                                             C




                          T 1



SOP 20W (300mil), SOP 24W (300mil), SOP 28W (300mil)

    Symbol                        Description              Dimensions in mm
       A         Reel Outer Diameter                           330.0±1.0
       B         Reel Inner Diameter                           100.0±1.5
                                                                     +0.5/-0.2
       C         Spindle Hole Diameter                        13.0

       D         Key Slit Width                                 2.0±0.5
                                                                     +0.3/-0.2
      T1         Space Between Flange                         24.8

      T2         Reel Thickness                                30.2±0.2




Rev. 1.00                                         95                       September 21, 2010
                                                                                                                  HT45R52/HT45R54

Carrier Tape Dimensions
                                         P 0                        P 1
                           D                                                                                            t


              E

              F
                                                                                    W
                                                                                                            B 0
                                                                                                     C



                               D 1                  P
                                                                                                                        K 0
                                                                  A 0




                                                                               R e e l H o le

                                                                          IC   p a c k a g e p in 1 a n d th e r e e l h o le s
                                                                          a r e lo c a te d o n th e s a m e s id e .


SOP 20W

    Symbol                            Description                                                        Dimensions in mm
                                                                                                                            +0.3/-0.1
      W           Carrier Tape Width                                                                          24.0
       P          Cavity Pitch                                                                                    12.0±0.1
       E          Perforation Position                                                                            1.75±0.10
       F          Cavity to Perforation (Width Direction)                                                         11.5±0.1
                                                                                                                            +0.1/-0.0
       D          Perforation Diameter                                                                            1.5
                                                                                                                            +0.25/-0.00
      D1          Cavity Hole Diameter                                                                       1.50
      P0          Perforation Pitch                                                                                4.0±0.1
      P1          Cavity to Perforation (Length Direction)                                                         2.0±0.1
      A0          Cavity Length                                                                                   10.8±0.1
      B0          Cavity Width                                                                                    13.3±0.1
      K0          Cavity Depth                                                                                     3.2±0.1
       t          Carrier Tape Thickness                                                                          0.30±0.05
       C          Cover Tape Width                                                                                21.3±0.1

SOP 24W

    Symbol                            Description                                                        Dimensions in mm
      W           Carrier Tape Width                                                                              24.0±0.3
       P          Cavity Pitch                                                                                    12.0±0.1
       E          Perforation Position                                                                            1.75±0.1
       F          Cavity to Perforation (Width Direction)                                                         11.5±0.1
                                                                                                                            +0.10/-0.00
       D          Perforation Diameter                                                                       1.55
                                                                                                                            +0.25/-0.00
      D1          Cavity Hole Diameter                                                                       1.50
      P0          Perforation Pitch                                                                                4.0±0.1
      P1          Cavity to Perforation (Length Direction)                                                         2.0±0.1
      A0          Cavity Length                                                                                   10.9±0.1
      B0          Cavity Width                                                                                    15.9±0.1
      K0          Cavity Depth                                                                                     3.1±0.1
       t          Carrier Tape Thickness                                                                          0.35±0.05
       C          Cover Tape Width                                                                                21.3±0.1



Rev. 1.00                                                    96                                                                     September 21, 2010
                                                                  HT45R52/HT45R54

SOP 28W (300mil)

    Symbol                        Description                 Dimensions in mm
      W       Carrier Tape Width                                  24.0±0.3
       P      Cavity Pitch                                        12.0±0.1
       E      Perforation Position                                1.75±0.10
       F      Cavity to Perforation (Width Direction)             11.5±0.1
                                                                        +0.1/-0.0
       D      Perforation Diameter                                1.5
                                                                        +0.25/-0.00
      D1      Cavity Hole Diameter                              1.50
      P0      Perforation Pitch                                    4.0±0.1
      P1      Cavity to Perforation (Length Direction)             2.0±0.1
      A0      Cavity Length                                      10.85±0.10
      B0      Cavity Width                                       18.34±0.10
      K0      Cavity Depth                                        2.97±0.10
       t      Carrier Tape Thickness                              0.35±0.01
       C      Cover Tape Width                                    21.3±0.1




Rev. 1.00                                                97                     September 21, 2010
                                                                                              HT45R52/HT45R54




 Holtek Semiconductor Inc. (Headquarters)
 No.3, Creation Rd. II, Science Park, Hsinchu, Taiwan
 Tel: 886-3-563-1999
 Fax: 886-3-563-1189
 http://www.holtek.com.tw

 Holtek Semiconductor Inc. (Taipei Sales Office)
 4F-2, No. 3-2, YuanQu St., Nankang Software Park, Taipei 115, Taiwan
 Tel: 886-2-2655-7070
 Fax: 886-2-2655-7373
 Fax: 886-2-2655-7383 (International sales hotline)

 Holtek Semiconductor Inc. (Shenzhen Sales Office)
 5F, Unit A, Productivity Building, No.5 Gaoxin M 2nd Road, Nanshan District, Shenzhen, China 518057
 Tel: 86-755-8616-9908, 86-755-8616-9308
 Fax: 86-755-8616-9722

 Holtek Semiconductor (USA), Inc. (North America Sales Office)
 46729 Fremont Blvd., Fremont, CA 94538, USA
 Tel: 1-510-252-9880
 Fax: 1-510-252-9885
 http://www.holtek.com



 Copyright Ó 2010 by HOLTEK SEMICONDUCTOR INC.
 The information appearing in this Data Sheet is believed to be accurate at the time of publication. However, Holtek as-
 sumes no responsibility arising from the use of the specifications described. The applications mentioned herein are used
 solely for the purpose of illustration and Holtek makes no warranty or representation that such applications will be suitable
 without further modification, nor recommends the use of its products for application that may present a risk to human life
 due to malfunction or otherwise. Holtek¢s products are not authorized for use as critical components in life support devices
 or systems. Holtek reserves the right to alter its products without prior notification. For the most up-to-date information,
 please visit our web site at http://www.holtek.com.tw.


Rev. 1.00                                                     98                                         September 21, 2010

								
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