Let’s Do Something Phenomenal
for Future Wireless Base-Stations
Sridhar Rajagopal and Joseph Cavallaro
ECE Dept., Rice University
April 10, 2000
Overview
Future Base-Stations
Current DSP Implementation
Our Approach
– Make Algorithms Computationally effective
– Task Partitioning for pipelining, parallelism
DSP Extensions for Performance Acceleration
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Evolution of Wireless Comm
First Generation
Voice
Second/Current Generation
Voice + Low-rate Data (9.6Kbps)
Third Generation +
Voice + High-rate Data (2 Mbps) + Multimedia
W-CDMA
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Communication System Uplink
Noise +MAI
Base Station
Reflected Paths
Direct Path
User 1
User 2
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Main Processing Blocks
Channel Estimation Detection Decoding
Baseband Layer of Base-Station Receiver
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No Multiuser Detection
Proposed Base-Station
TI's Wireless Basestation (http://www.ti.com/sc/docs/psheets/diagrams/basestat.htm)
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Current DSP Implementation
4
x 10 Data Rate Comparisons for Matched Filter and Multiuser Detector
18
16
14
Targeted Data Rate = 128Kbps
Data Rates Achieved
12
10
Projected (8x)
8
Matched Filter(C64)*
Multiuser Detector(C64)*
6 Matched Filter(C67)
Multiuser Detector(C67)
4 Targeted Data Rate
2
C67 at 166MHz
0
9 10 11 12 13 14 15
Number of Users
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Complexity
Algorithm Choice Limited by Complexity
Main Features
– Matrix based operations
– High levels of parallelism
– Bit level computations
32x32 problem size for the Detector shown
Estimation, Decoding assumed pipelined.
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Reasons
Sophisticated, Compute-Intensive Algorithms
Need more MIPs/FLOPs performance
Unable to fully exploit pipelining or parallelism
Bit - level computations / Storage
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Our Approach
Make algorithms computationally effective
– without sacrificing error rate performance
Task Partitioning on Multiple Processing Elements
– DSPs : Core
– FPGAs : Application Specific / Bit-level Computations
VLSI Implementation to find extensions for DSPs.
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Algorithms
Channel Estimation
– Avoid inversion by iterative scheme
Detection
– Avoid block-based detection by pipelining
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Task Partitioning
Channel Estimation Detection Decoding
Time
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VLSI Implementation
Channel Estimation as a Case Study
Area - Time Efficient Architecture
Real - Time Implementation
Bit- Level Computations - FPGAs
Core Operations - DSPs
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DSP Extensions for Performance
Bit-level storage / processing support
– Registers / Memory / ALU
Efficient Matrix -Based operations
– Matrix- Vector Multiply
Support for Complex-valued data
Efficient memory accesses
Pre-fetching Data - C64
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Software Suggestions
Limited OS Support
Compiler Efficiency
– No more Assembly!
Performance Analysis Tools
Code Composer Studio 1.2
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Conclusions
DSPs to play major role in Future Base-Station
Implementations.
Search for Computationally Efficient Algorithms and Better
Processor Designs to meet Real-Time
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