VHDL Development for ELEC7770 VLSI Project by HC111211061947

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									      VHDL Development
       for ELEC7770 VLSI Project



               Chris Erickson
                Graduate Student
Department of Electrical and Computer Engineering
      Auburn University, Auburn, AL 36849
          Chris.Erickson@auburn.edu
               Objectives
Logically perform the designed functions

Be efficient
– Code length
– Routines
– Signal utilization

Perform the functions appropriately per
cycle
    Component Development
All components designed & developed
  independently
       Instruction Register
       Program Counter
       Register File
       Data Register
       Multiplexers
    Test RS
                                  A
    Test RT            Register
    Test RD              File
                                  B
  Test RegWrite
 Multicycle Datapath

Cycles per instruction (CPI):
       Load Word       5
       Store Word      4
       Register-type   4
       Branch          3
       Jump            3
       3 to 5 Cycles per instruction
    Step            R-type           Mem. Ref.         Branch         J-type
                  (4 cycles)       (4 or 5 cycles)       type       (3 cycles)
                                                      (3 cycles)
 Instruction                      IR ← Memory[PC]; PC ← PC+1
    fetch
 Instruction               A ← Reg(IR[25-21]); B ← Reg(IR[20-16])
  decode/
Register fetch
Execution,                           ALUOut ←           If (A=B)
 Branch &         ALUOut ←          A+sign extend          then     PC←PC[31-
  Jump             A op B              IR[15-0]       PC←ALUOut    26] & IR[25-0]
completion
Mem. Access      Reg(IR[15-11])   MDR←M[ALUout] or
  or R-type       ← ALUOut          M[ALUOut]←B
 completion
Memory read                        Reg(IR[20-16]) ←
 completion                              MDR
                            Control FSM
                             Start
               State 0                           1

                      Instruction                    Instruction
                         fetch                         decode

                                                     R                 J
                                                            B
3                     2
     Read        lw       Compute    6                     8               9 Write PC on
                                               ALU             Write PC
    memory                memory             operation         on branch        jump
     data                   addr.                              condition
                                sw
4                     5                  7
     Write                  Write              Write
    register               memory             register
                            data
                   Code
Initialize, set state = 0
If state = 0 then
Set state 0 signals
Set state = 1 for next clock cycle
If state = 1 then
Set state 1 signals
Set state = 2 for next clock cycle
If state = 2, depending on opcode, we will either
go down path of register-type, load word, store
word, branch, or jump instruction.
        Cycle Boundaries
Multiplexers are handled at the end of
each cycle

Multiplexer outputs serve as “variables” to
be used as inputs for the next clock cycle

Either a multiplexer or another stand-alone
component must have a steady-state
output to serve as input for the next cycle
                 Multicycle Datapath
                                                                                                            Shift
                                                               25-0




                         Instr. reg. (IR)
                                                                                                            left 2
                                                               25-21                                       28-31
                                            20-16




                                                                                               A Reg.
                Memory




                                                                              Register file
PC




                                                                                                                              ALUOut Reg.
        Addr.




                                             Mem. Data (MDR)

                                                               15-11




                                                                                                                     ALU
                                                                                               B Reg.
     Data


                                                                                                                 1



                                                                                       Sign             Shift
                                                                       0-15           extend            left 2
                                                                                                                     Opcode
                                                               31-25
         Completed !!

Any Question? Comments?

								
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