Test equipment for physical layer conformance testing of

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					Test equipment for physical layer conformance
 testing of parallel buses exemplified for SFI-4/5


                         Interoperability Working Group
                        OFC Atlanta, March 23-28, 2003
                            Michael Fleischer-Reumann
                                  Agilent Technologies
                                                 Agenda

1.   Motivation
2.   Location within the system architecture of parallel buses
     specified by OIF and their architectural parameters
3.   General measurement setup to prove SFI-4/5
     compliance
4.   Focus on timing measurements on SFI-4/5 I/Os
     SFI-4 output timing
     SFI-5 output timing
     SFI-4/5 input timing
5.   Specific SFI-5 - item:
     Jitter and Wander (common and relative)
6.   Parallel test equipment: Agilent ParBERT 81250 Platform
7.   Summary
                                                   Motivation
   Interoperability – how to demonstrate it?
    •   Let modules of different vendors work together as
        demonstrated at the booth
   Interoperability – how to assure it?
    •   Let modules of different vendors work together under
        corner cases or marginal conditions!
    •   But usually those can not be achieved with regular
        modules!
    •   Consequently use test equipment
         •   for input ports: to generate corner cases according to
             specifications (e.g. marginal input timing)
         •   for output ports: check that specified limits are met
        to measure the compliance with specifications
        published in implementation agreements
         System architecture and location of
                   different buses/standards



         SPI-3,
TDM SPI-4-1/2,                                SFI-4-1/2,   Serdes VSR-4-01..05
fabric SPI-5,TFI-5 Framer SFI-4-1/2,   FEC
                            SFI-5               SFI-5      /PHY     VSR-5


                                             Focus of this presentation
parallel buses specified by OIF (selection)
           electrical SFI-4/5                          optical VSR-4/5
           10Gb/s                      40Gb/s          10Gb/s            40Gb/s
           SFI-4       SFI-4 phase 2   SFI-5           VSR-4-01          VSR-5

Data       16 x diff   4 x diff        16 x diff       10 x optical      12 x optical
           622Mb/s     2.488...3.125   2.488...3.125   850nm MM          850nm MM
channels               Gb/s            Gb/s            1.25Gb/s          3.318Gb/s
and rate
Clock      (311)       NA              622... 781MHz   NA                NA
           622MHz

Other      NA          NA              + Tx/RxDSC      Protection &      NA
                                                       Error Detection
channels                                               Channel (EDC)
Data       yes         yes but:        Yes but:                       No:
agnostic               coded and       Deskew            Sonet cells/frames required
                       scrambled       signal w/
                                                       Virtual blocks    A1/B1 bytes
                                       special data
                                       content         of EDC shall      boarder used
                                                       match SONET       for
                                                       frames            deskewing
        general measurement setups to prove
                        SFI-4/5 compliance
SFI-4/5 side             Serial side
ParBERT 675M/3.35G       on serial side DUT’s
                                                                                         DCA
generators stimulate     functionality (BER=0) or
DUT on SFI-4/5 bus       performance (eye
varying parameters       mask, jitter) is




                                                                    mux/
(e.g timing) to          monitored with ParBERT      Parallel




                                                                    TX
emulate critical         10.8G/45G analyzer or
corner cases             with DCA                   BERT PG                              Serial
                                                                   DUT e.g.             BERT ED
                                                                                  O/E
ParBERT 675M/ 3.35G
                                                                   300pin
Analyzers monitor                                                   MSA
DUT’s functionality
(BER=0, RXDSC=ok) on
SFI-4/5 and




                                                                    de-mux
measure compliance                                   Parallel




                                                                     RX/
for skew/jitter with
                         ParBERT 10.8/45G
timing measurement
or signal quality with   generators stimulates      BERT ED                              Serial
fast eye mask or eye     DUT on serial side
diagram                  (electrical or optical)                                        BERT PG
measurement.             with nominal signals
                                                                                  E/O

Direct Input
to Output: DItO
                             Loopback or              electrical              optical
                             Back to Back
                             (B2B)
    Focus on: Output Timing Measurements
                                   (SFI-4)
   Specification
     • Data valid window: UI-400ps
       or ts/th=+/-200ps
   Measurements and results
     • BERT-scan:
       ts/th value and pass/fail,
       skew between channels
     • Fast eye mask:
       user defined eye mask pass/fail
     • Eye diagram
    Focus on: Output Timing Measurements
                                   (SFI-5)
   Specification
     • Maximum skew between data and deskew channels:
       2UI (at DUT output), 5(.65)UI after “channel”
   Measurements and results
     •   Fast eye mask w/ user defined points => pass/fail
     •   Eye diagram
     •   BERT-scan
     •   data capture
         w/ automatic
         sample point
         adjust =>
         skew between
         channels
         and Rx/TxDSC
    Focus on: Input Timing Measurements
                             (SFI-4/SFI-5)
   Specifications
    •   SFI-4: Ts/th +/-300ps
    •   SFI-5: skew < 5(.65)UI
   Measurement
    •   set input timing to corner cases to verify
        conformance and check correct functionality or
    •   vary input timing until functional failure appears to
        characterize valid input timing range
    •   BUT: How to check correct functionality/ failure?
         •   Check waveform on serial side?
         •   Check BER=0 on serial side!
         •   Loop back and check BER=0 on parallel side!
Functional verification by waveform check only?

Only one
waveform
stems
from a
failure
free
serializer   jammed bit             inverted bit
or mux!!




             delayed bit            failure free
Specific item for SFI-5: HF jitter tolerance
Noise       Pulse or PRBS      Eye opening at receiver
Source           generator




          1: 2
         power
         adder




    Jitter two ranges:
modulation 50 & 500ps/V
   inputs
                               DJ, (RJ) and TJ are user definable
   ParBERT                     through variable amplitude and
                         DUT




  Generators                   frequency simple adjustment to
                               different data rates
                           Specific item for SFI-5:
                      Common plus relative Wander
     Test in two ranges with different setups at discrete frequencies

     range 1: >1.3UI, <120kHz                 range 2: <1.3UI, >120kHz
    ParBERT in ext. clock mode              ParBERT running at 2.5Gb/s
                                              modulate generators with slightly
    central clock modulated by           

                                              different frequencies
     external signal generator
                                                                      10MHz ref
                                              f1+Df           f1

       UI wander
    10.65

                                     ParBERT




                                                                MUX
     1.3                            Generators
           relative
     0.1
                              f
                                                               ParBERT 81250 Platform
                                                                                            Product offering
                          E4875A ParBERT Software Suit E4875A
Software
                          includes GUI, Measurement Software,
                          SFI-5 and 10GbE Post-Processing Tools
                          Q-factor and timing analysis incl. RJ/DJ separation

Modules



      E4805B/08A      E4832A         E4861A                        E4810A               E4866A           N4872A
                                                   E4861B                                                13.5 Gb/s
      Standard/       675 Mb/s       2.7 Gb/s                      3.35 Gb/s            10.8 Gb/s
                                                   3.35 Gb/s                                             Generator
      High            Module         Module                        Electrical/Optical   Generator
                                                   Module                                                Module
      Performance                                                  Generator Module     Module
      Clock
      Module                                                       E4811A               E4867A            N4873A
                                                                   3.35 Gb/s
                                                                                        10.8 Gb/s         13.5 Gb/s
                                                                   Optical/Electrical   Analyzer          Analyzer
                                                                   Analyzer Module
                                                                                        Module            Module
                                                                                                                 E4896A 45 Gb/s Pattern Generator Bundle
                                                                                                                 E4867A 45 Gb/s Error Detector Bundle
                                                                                                                 E4883A Lightw ave Transmitter Module
                                                                                                                 E4882A Lightw ave Receiver Module
Front Ends                                                                                                       E4884A High Performance Lightwave Opti
           E4838A    E4835AE4862A/64A/63A/65A    E4862B/63B
          675 Mb/s 675 Mb/s    2.7/1.6 Gb/s       3.35 Gb/s
          Generator AnalyzerGenerator/AnalyzerGenerator/Analyzer


            675 Mb/s         2.7/1.6 Gb/s 3.35 Gb/s                              10.8 Gb/s          13.5 Gb/s            45 Gb/s
                                                    Summary
   Variety of bus architectures requires versatile test equipment
   Absolutely necessary to stimulate all relevant signals of the
    bus (data + clock + dsc + ...) w/ the ability to vary signal
    parameters and data content
     • to adopt to different buses and
     • to create corner cases /stress conditions
   Necessary to verify correct functionality by more than a
    waveform measurement
     • either on serial side upon Direct Input to Output
       measurement w/ Serial BERT or single BERT ED channel
     • on parallel side after loop-back-test (w/ parallel analysis
       equipment i.e. parallel BERT ED)
   Ability of parallel BERT ED (ParBERT) to measure on all (data)
    channels simultaneously lowers test time significantly

				
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