VLSI Design Full-custom IC Design Flow ew路論

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VLSI Design Full-custom IC Design Flow ew路論 Powered By Docstoc
					Introduction to VLSI Circuits and Systems
                           路       論
             VLSI Design
     Full-custom IC Design Flow

            Dept. of Electronic Engineering
       National Chin-Yi University of Technology
                       Fall 2007
                Outline

Schematic with Composer of ICFB (Cadence)
Pre-simulation using Hspice
Layout with Virtuoso or Laker
Verification using Calibre or Dracula
  DRC
  LVS
  PEX
Post-simulation using Hspice

                                            2
       Custom IC Design
We offer the technology files of the following,
      and copy it to your home directory
   Technology      File Name                Purpose
                    display.drf        Virtuoso       料

                     035ms.tf

                    mm0355v.l            Spice model file

    TSMC035     Laker ( a directory)    Laker         料

                    calibre.drc                 DRC

                    calibre.lvs                 LVC

                    calibre.pex                 PEX


                                                            3
                  Environment

Operation System: Solaris 8 (Sun Blade 2500)
Account is personal student’s identity number, ex. g955168
Using X-win32 or ReflectionX to remote WorkStation




                                                             4
Console
      Shell is C-shell




                             1.      source
                             license
                         錄
                  2.         home dir/.cshrc




                                          5
Schematic with Composer




                          6
                              ICFB
Under home directory           Mkdir work_tsmc035
                 錄
Under work_tsmc035 directory          icfb &




Under your design directory
                                      Cadence   ICFB




                                                       7
   Merge Display File to Virtuoso
       Schematic & Layout view
Key Step: Tools Display Resource Manger…




                                            (1) ../technology/display.drf
                                              (2) Add



                               (3) ./work_tsmc035/display.drf



                                                                   8
                立                  Library
不                  不              library
Step 1: Select File New Library
Step 2: Name tsmc035_techfile (user-define)
Step 3: ASCII Technology File ../technology/035ms.tf




       Step 1             Step 2




                                      Step 3
                                                       9
             立             Design Library
Step 4: Select File New Library
Step 5: Name basic_logic (usr-define)
Step 6: Technology Library tsmc035_techfile


         Step 4

                                              Step 6




                  Step 5




                                                       10
   Create a Cellview under Design Library

  立       cell inv (inverter)
Step 7: Select File New Cellview




                                            11
Step 8:       analogLib   立     instance


PMOS: pmos4
NMOS: nmos4




                              instance (hot key ‘i’)




                                                       12
                              input and output
                        (hot key ‘p’)




    inverter
(pmos, nmos, vdd, gnd
and wire-connection)


                                          13
        Generating Netlist using CDL

Step 9: File   Export   CDL




                              Netlist   name.sp


                                                  14
15
Modify the inv.sp and Create a another inv_sim.sp




Delete




         NM   NCH
         PM   PCH


                                                    16
          Pre-sim. using Hspice
  行 Hspice    netlist Spice Model file mm0355v.l
        錄
Console soclab02% hspice inv_sim.sp




                          路       !




                                                   17
     hspice job concluded      soclab02% awaves &
Step 10: Open               Step 10




                                        Ctrl+a




                                                    18
    inverter   input &
output




                         19
Waveform with Awaves




  **   Pre-sim.   行layout**
                              20
Layout with Virtuoso Editor




                              21
       Layout with Virtuoso Editor

Step 1: Link Calibre into Virtuoso
(load(“/usr/mentor/Calibre_ss/cur/lib/calibre.skl”)
Step 2: File New Cellview                        Under the same
                                                   library and cell
                                                   name

              Step 1




                          Step 2


                                                   Select Virtuoso, and
                                                   View Name is layout
                                                                      22
Virtuoso Layout Window

                                Make sure linking
                                Calibre success!




   LSW:                 layer
                  Display resource manger (Merge
   display.drf)




                                                    23
               N-Well COMS Inverter




The cross-section view and layout of a CMOS(n-well) inverter




                                                               24
TSMC035 Minimum Design Rule with
         COMS Inverter




                                   25
Minimum NIMP extension         Minimum N-Well width 1.7
of N+ Diffusion 0.25 um        um


Minimum POLY1 extension        Minimum Metal1 extension
of Diffusion 0.4 um            of Contact 0.15 um



Minimum Contact to             Contact size 0.4 * 0.4 um
Contact spacing 0.4 um


Minimum Diffusion              Minimum N-Well extension
extension of Contact is 0.15   of P+ Diffusion 1.2 um
um

                               Minimum Metal1 width 0.5
                               um

Minimum clearance from
Contact on Diffusion region
to a Poly gate 0.3 um          Minimum Diffusion width
                               0.3 um



                               Minimum PIMP extension
Minimum Poly1 width 0.35       of P+ Diffusion 0.25 um
um
An Inverter Layout




                     27
    Layout Verification
with Calibre DRC/LVS/PEX




                           28
               Calibre DRC (5/1)
Step 1: File   Export       Stream




    Layout GDSII


                   Step 1




                                     29
                  Calibre DRC (2/5)
Step 2: Calibre    Run DRC
                               Calibre DRC window




                                                    30
                Calibre DRC (3/5)
Step 3: Rules    TSMC035   calibre DRC rules file




                                                    31
                Calibre DRC (4/5)
Step 4:Inputs   Layout       Files   inv.gds (路   )




                 layout view來
          行      路
                           disalbe



                                                      32
             Calibre DRC (5/5)
Step 5:Run DRC        No error!       略 design rule error
                             “        DRC     -     -
                                  ”




                                                            33
              Calibre LVS (1/6)
Step 1:   inv.sp    netlist LVS




                                  34
                  Calibre LVS (2/6)
Step 2: Calibre    Run LVS




                                      35
                Calibre LVS (3/5)
Step 3: Rules    TSMC035   calibre LVS rules file




                                                    36
                Calibre LVS (4/6)
Step 4:Inputs   Layout   Files   inv.gds (路   )




                                                  37
                Calibre LVS (5/6)
Step 4:Inputs   Netlist       Files   inv.sp (路   )




                    schematic view來   行
                路
                    disalbe


                                                      38
Calibre LVS (6/6)




                    39
              Calibre PEX (1/8)
Step 1:   inv.sp    netlist PEX




                                  40
Calibre PEX (2/8)




                    41
Calibre PEX (3/8)




                    42
Calibre PEX (4/8)




                    43
Calibre PEX (5/8)




                    44
Calibre PEX (6/8)




                    45
Calibre PEX (7/8)

行RC




                    46
Calibre PEX (8/8)




                    47
                    Modify inv_pex.sp




inv_pex.sp.inv.pxi &
inv_pex.sp.pex       PEX
            RC參數




                                        48
inv_pex.sp.inv.pxi &
inv_pex.sp.pex       PEX
            RC參數



                           49
Post-simulation Result




                         50
錄: Layout with Laker Editor




                              51
                    Laker
                      Laker
g9556168% laker &
                              立




                                  52
    立




路




        53
Working Window




                 54
Layer Table




              55
Change Grid
              CIC Grid 0.025um




                                 56
         2NAND



立Transistor




                 57
58
59
60
61
PMOS   Body

  NMOS    Body




                 62
Stream Out




             63
Stream In




            64
65
COMS Inverter




                66

				
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posted:12/10/2011
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