EE410 LAB #1
Boise State University, College of Engineering
Basic Inverter Design
Due 5 PM, 9/15/99
- Ken Boorom
1) Learn to capture schematics of an inverter
2) Learn to simulate the schematics
3) Lean to layout the schematics
You need to submit the following items from this lab:
ITEM #1: Netlist for your inverter
ITEM #2: CIF file for your inverter
ITEM #3: Answers to questions
You can submit files by e-mailing them to me. All of these are text files - pls just send them as regular
messages, and not as attachments or encoded files. Pls indicate what file you are submitting in the
From Unix, you would mail these files:
mailx -s "LAB 1 Netlist" firstname.lastname@example.org < (netlist file)1
mailx -s "LAB 1 CIF" email@example.com < (CIF FILE)
Subject: Lab 1 Answers
(type answers here)
The command, with spaces changed to underscores, would
read mailx_-s_"LAB_1_Netlist"firstname.lastname@example.org_< (netlist file)
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YOUR NAME: _____________________
0.2 Prelab (to be turned in before lab starts)
The answers to the questions below are contained in various places in this lab.
You will need to read the lab to answer some of them.
(1) Draw a schematic of a Static CMOS inverter. Show the body contacts on the PMOS and NMOS
(2) Draw the same schematic without the body contacts.
(3) Why do we sometimes leave the body contacts off schematics?
(4) Write down the netlist for the schematic in #2.
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(5) Draw a "test jig" schematic for an inverter. Show the inverter as a block with inputs and outputs, and
show the voltage source as a 100 Mhz sine wave.
(6) Draw a series of timing diagrams showing 30nsec of the sine wave's activity, and the inverter output.
Assume the inverter delay is 2nsec.
(Answers to the following questions are contained in the lab)
(7) List two 'views' used in Cadence and what information they contain in them:
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(8) In the naming convention we are using, what would the difference between a NAND4A and a
(9) List one bad thing that will happen if you try to connect two parts by dropping them on top of
(10) Give one reason why we create a symbol view:
(11) Give an example of one kind error a DRC looks for:
(12) Give an example of one kind error an LVS looks for:
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Text Editor (bottom left-hand side, looks like a
1.0 Logging In piece of paper with a pen on it): This is a mouse-
driven text editor which follows the Windows
To log in to a Unix Server, enter your logon and keyboard convention. If you are a windows user,
password. you may find this editor more intuitive.
Things that can go wrong and what to do about Terminal (bottom left-hand side, click on the up
them: arrow over the Text Editor, then select TERMINAL):
This brings up the Unix command window, which
The screen says your password is invalid: Make you will use to manipulate files, run applications,
sure you entered your password correctly. Unix and do other things.
passwords are case-sensitive – make sure caps
lock is not on. Try re-entering your password. If all You need to start a Unix terminal window to bring up
else fails, call Alex Pierce and have him reset your Cadence's software,
The screen locks up, and weird messages
appear at the bottom of the screen: This means 4.0 Starting Cadence Software
the main Unix server is shut down, or there is some
networking problem. Try another system. Contact This example assumes you turned in your class signup
Alex Pierce and tell him which system you which form, and the instructor has had time to set up your
system you were trying to use. account for Cadence.
Open a terminal window, and type the following:
2.0 The Front Panel
Once you have logged in, the front panel will icfb &
appear at the bottom of your screen:
There is a space between the "cd" and the tilde (~).
There is a space between the icfb and the &.
When you are done working, you must log off the
icfb stands for “IC-Front-To-Back"
computer. Do this by clicking on the EXIT sign on
the front panel. Please do not leave your computer
Hint: Do not forget to change into ee410. If
logged in when you are not using it – it can create
you do, you will have to exit icfb and start
The Command Interpreter Window appears:
3.0 Relevant Front Panel
The following front panel features are relevant to
File Manager (bottom left-hand side, looks
like a filing cabinet): This allows you to copy,
erase, rename, and move files using a
graphical user interface. You are welcome to
use this if you like, but instructions will be 4.1 Creating a New Schematic
provided using the Unix command line
interface. We will now create a new, blank schematic sheet.
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To do this, select File / New / Cell View and fill out Note that the tilde is equal to /home/students/yourdirectory
it out: so you can replace this part with a tilde (i.e.:
View Name: Schematic ~/ee410/yourname/INV1A/schematic
(2) A cell is a digital or analog circuit. Examples of cells
include: an inverter; a nand gate; a shift register; a DRAM
cell. Since circuits can contain other circuits, examples of
higher level cells could include a Pentium processor; a
router chip; an A/D converter.
(3) A cell can have multiple views. Each "view" has
different data about the cell. In this course, we will be
working with two views: schematic and layout, which
EXAMPLE - Note view name should be schematic, predictably contain the schematics and layouts.
(4) The Composer tool edits schematics. The Virtuoso
tool edits layouts.
There are four things you must specify to create a
new file: (5) You do not have to call the schematic schematic.
This is just a convention. I frequently make 'backup'
(1) The name of the library. To simplify life for the copies of my work by saving my schematic to schematic1,
instructor, everyone's library has a different name. schematic2, schematic3, etc. The same goes for layout.
Pick the library which corresponds to your name. To keep things straight, I leave my most current version in
the views names schematic and layout.
(2) The name of the cell. We will call the cell INV1A
(6) Different companies have different conventions for
(3) The name of the view. We will call the view naming cells. We will use the following convention in this
(4) The name of the tool. The Composer tool edits Cell name is UPPER CASE for historical reasons
schematics. If you fill in the view, hit the tab key,
Format is CELLFUNCTIONnndd where nn=number of
and Cadence will fill this in for you.
inputs and dd=drive strength
A = Minimum drive strength, B=Two times A, C=Four
Here is a short description of the relevance of all of
Times A, D=Eight times A
So INV1A is a 1-input inverter with minimum drive
(1) The data for the cell will be stored in a file called
library_name/cellname/view under your current
directory. In the above example, all the data will be
Select File/Save to save your blank schematic.
stored in a directory called
4.1 Adding Components to the
The hierarchy is:
/home/students - where student accounts are Schematic
+/yourdirectory - where your files are
+/ee410 - where your ee410 files are at First, you will add a PMOS transistor to the schematic.
+/yourname - Your design library for ee410
+/INV1A - The name of the cell Do this by selecting ADD/COMPONENT, and specifying
+/schematic - The schematics of the cell the following component:
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We are using the NCSU Design Kit (North Carolina
State University). This library NCSU_Analog_Parts
has many useful things in it for simulating
schematics, such as voltage sources, transistors,
The NCSU Design Kit can work with many different
processes (TSMC, HP, Orbit, etc.) Each process
has its own set of design rules and transistor
models. In setting up your library, we have
"attached it" to the process from Orbit called CN20.
The default model name that appears when you
create the transistor below (orb20P) shows this.
After you type symbol, hit the tab key, and you will
get a menu box that looks something like this:
Specify the WIDTH of the PMOS as 6 microns (12 grid
Usually, we just fill out the length and width in grid units
and let the computer calculate the rest of the values. You
can, however, enter you own values for some of the
parameters to override the computer's calculation.
WARNING: If you enter the length by hand, this
software will interpret '6' as 6 meters. This will cause
lots of problems!
So make sure to type 6u for 6 microns.
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You will be asked to supply information about the
length and width. Use the following values:
Move the mouse to a place on your schematic
window and click it to deposit a PMOS transistor.
NOTES ON THE SCHEMATIC EDITING
1. This interface is a fairly standard windowing
interface with a few exceptions. Most commands
work by selecting an area of the schematic, either
by clicking it, or creating a box by dragging the
2. A few useful commands include:
Escape: Cancel current mode
Select/Drag: Move an item Connect the gates of the two transistors by drawing a wire
Shift-Move: Copy an item (ADD/WIRE). Click once on the first gate, move the
Select/Delete: Delete an item mouse then click again on the second gate. Add more
Arrow Keys: Move the viewport around wires to make an inverter:
3. Sometimes, the escape key does not work on
the X-Terminals to cause Cadence to quit its mode.
If you have this problem, start a new command (like
COPY or MOVE) and then click the CANCEL
button. The current mode you are in is always
displayed at the bottom of the view screen.
4. There are many other commands. The best way
for you to figure out what they do is to try them out!
The commands are located under the drop down
menus, and some other ones are located as
buttons on the left hand side of the window.
5. Avoid trying to connect components by dropping
them on top of eachother. This may or may not
connect them, and you will not be able to probe the
net later on. Instead, put them near eachother and Add Ground and Vdd symbols by adding the following
draw a wire between them. components (ADD/COMPONENT):
Repeat this process for an NMOS transistor.
Specify the width of the NMOS as 3 microns, or
You should have something that looks something
like this (note: your transistor widths should agree
with what you specified, not what is in the picture!)
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When you have completed your inverter, the
schematic should look like this:
After you fill out the form, move the cursor to the
schematic and click once on the wire leading from the
gates of the transistors
NOTE: This tool's user interface differs from many
others in that you do not press any APPLY or OK
button before performing this action.
Repeat this process (ADD/PIN) for the output pin:
Save your work by selecting FILE/CHECK AND SAVE.
The tool should save the schematic without reporting any
Save your work by selecting FILE/CHECK AND errors.
4.2 Identifying INPUT and 4.3 Saving and Creating a Symbol
OUPUT points The final step in creating the cell involves creating a
The schematic is electrically correct, but it lacks
information that would allow another engineer to This view is a simplified schematic view which just shows
use it. the inputs, the outputs, and a block.
Mainly, the "INPUT" and "OUTPUT" points have not When you add a cell to your schematics, you can use the
been identified. You can identify them by inspection symbol view or the schematic view. Most engineers will
but Cadence can't. use the symbol view because it keeps the top level
schematics less cluttered.
To identify the connection points, we add something
called a "PIN" to the schematic. To do this, select To create a symbol, select DESIGN/CREATE CELL
ADD/PIN then fill out the form as shown below: VIEW/FROM CELL VIEW.
You need to give it the library name and the cell name.
Replace "type_your_name_here" with the name of your
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To specify these items, we will create a new schematic
which will consist of the inverter we are testing plus a
This schematic differs from the first one we created in that
we do not intend to fabricate it. We are creating the
schematic to test the inverter.
5.1 Creating the Test Bench
Next, you will be given some symbol generation
Create a new schematic as described earlier:
Accept the defaults. The defaults will put the inputs
on the left side of the block, the outputs on the right
5.0 Simulating your Schematic As usual, replace "type_your_name_here" with the name
of your library:
In this section, we will create a "test bench" for your
schematic. Library=Your Library
CellName = test_INV1A
A Test Bench has three components: Tool=Composer
(a) The circuit to test As a convention, we will call the test benches for our cells
(b) A stimulus provided to the circuit test_CELLNAME.
(c) An expected result
In a formal test bench, all three of these items Once your have the blank schematic window, add a copy
would be specified so the bench could be run of the inverter you created earlier by selecting
automatically. In an integrated circuit with millions ADD/COMPONENT and specifying the inverter's symbol
of gates, it is important to be able to automate test view:
operations to quickly identify faults.
In our test bench, we will be formally specifying only
the first two items. We will verify the expected
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CellName = INV1A
ViewName = symbol
The other component we will add is a voltage
source. Select ADD/COMPONENT and specify the
Once you fill in the first three items and hit the tab
key, the other items will appear.
Also, add a ground:
Specify the magnitude, amplitude, frequency, DC
Voltage as shown:
Use the ADD/WIRE function to connect the components
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From Analog Artist, select Analysis and Choose. Fill out
the form as indicated below:
We could simulate the schematic this way, but it
would not be realistic because there is no load on
To simulate a load, add a second copy of the
inverter and connect it to the
HINT: Do not try to connect two components by
dropping the pins right on top of eachother.
Instead, place the components near eachother and Next select Outputs / Plot / Select On Schematic and
connect the pins with a wire. click once on the wires which
(a) Connect the voltage source to the inverter
6.0 Simulating (b) Connect the output of the first inverter to the input of
the next inverter
We are now ready to simulate. Select Tools /
Analog Artist from the menu at the top of the
Next, select Simulation / Run.
The activity for the simulation is displayed in the
Command Interpreter Window:
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Transistor models used for this simulation were keyed
from the names "ORB20P" and "ORB20N" which were
entered when you added the transistors to the schematic.
The Simulation program has a list of paths which is
searches for files matching these names to find the model.
You can view this list by selecting the "Models" menu on
Your plot should look something like this:
6.1 Submitting the Netlist
You can save a copy of the netlist for your inverter to a file
by selecting Simulation / Display Netlist / Display
Final. This will show the final netlist on your screen.
Go to this window and select File / Save As and specify a
filename, such as ~/lab1netlist
You can e-mail me the netlist with the following Unix
mailx -s "LAB1 Netlist" email@example.com<~/lab1netlist2
We will use this plot to calculate the rise time and
fall time of the inverter. 7.0 Design Iteration
The rise time is measured from the mid-point of the
input to the mid-point of the output. What rise time
do you see from your circuit? 2
The command, with spaces
(QUESTION 1 to submit via e-mail for lab) changed to underscores, would
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We will now investigate to see what happens when
we change inverter sizes. We will do this by
making a copy of the existing INV1A cells and
changing their transistor widths?
MAKE A COPY OF THE CELLS
Next, we will create a layout view and layout the inverter.
1. Open the INV1A schematic (File / Open / We will layout only the INV1A case for simplicity.
To create a layout view, select FILE/NEW CELL VIEW
2. Save it as INV1C (File / Save As / Specify and specify the following:
3. Close INV1A (File / Close)
4. Open INV1C (File / Open / Specify INV1C)
5. RIGHT CLICK on each transistor and change
the WIDTH to four times what it currently is.
6. Save the new design.
Select EDIT/DISPLAY OPTIONS and change the grid
MAKE A COPY OF THE TEST BENCH spacing as shown below. We are designing in a 2 micron
process, so this will give you a 2 micron grid for
1. Open the test bench test_INV1A and save it as
convenience. It will also make sure you can not place a
component at any illegal subdivision of the grid.
2. Open the test bench test_INV1C and replace
INV1A with INV1C. Save the test bench as
NOTE: Unlike Windows, when you perform a SAVE
AS, the editor does not switch its context to the new
design. Be aware of this when creating new
designs from old ones using save as, as you may
inadvertently change the original design!
Simulate the new design.
Has using a larger sized transistors improved the
speed of the inverter? Why or why not?
8.1 Adding the Components
The objective is to create a layout that matches the
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First, we will add a PMOS transistor to the Your design should look like this:
schematic. To do this, select Add / Component
and specify the following:
To view the layers contained in each of these transistors,
type the "+" key. This will cause Cadence to view more
WARNING: If you enter the length by hand, this
software will interpret '2' as 2 meters. This will
lock up the schematic editor. You will have to
shut down all your windows and restart
Cadence, losing any changes you made since
your last save. This is very annoying. So make
sure to type 2u for 2 microns, or just enter the
grid units and let it calculate for you. 8.2 Design Rule Checking
Add the PMOS transistor with a width of 6 microns There are TWO types of checks your layout must pass to
(12 grid units) be correct.
Click the mouse once on the blank layout. The first type, a design rule check (or DRC) verifies that
the circuit you have created can be fabricated. It checks
We will discuss the meaning of the fingers later. to make sure you have not tried to create features that are
too small, or placed things too close together.
Add an NMOS transistor similarly.
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We will perform a design rule check now. To do
this, select VERIFY / DRC. Accept the default
You should not see any errors. The report should
look like this:
The following report is an example of what the
report looks like when there are DRC rules in the
If you see an error, you will need to identify it and correct
it. Errors are highlighted on your layout with white bars or
crosses. To see the cause of an error, select VERIFY /
EXPLAIN MARKERS and select the error you have a
All the numbers refer to SCMOS design rules which are
documented on pages 98-104 of Rabaey, and on the
class web site.
In addition to the explanation, the program tells you
the number of the rule that was violated. The rules NOTE ON DESIGN RULES: Scalable CMOS design
are documented in the SCMOS Design Rules which rules are used widely in academia. They allow a single
are available through the MOSIS web site design to be ported between different processes. For this
(www.mosis.org) reason, they are very useful in situations where you need
to prove a design, and perhaps use it in the future to prove
The program also graphically displays the error by other designs.
drawing thin white lines on the layout between the
two layers which are interfering: SCMOS design rules are not the only ones that exist. In
fact, virtually every fab will have its own set of design
rules. SCMOS design rules are very conservative, so a
design which follows SCMOS rules should also follow any
fab's design rules.
But the reverse is not true. Fab design rules trade off the
flexibility of SCMOS design rules in exchange for more
compact designs. In production situations, where die size
translates to cost, specific fab design rules are favored
over SCMOS design rules.
Because design rules give you information about how well
a fab controls its process, many fabs consider their design
rules proprietary and will only release them to customers
once the customer has signed a non-disclosure
agreement (NDA). These agreements can complicate the
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process of integrated circuit design. A modern,
customer-oriented fab which is eager for customer's
business will provide a minimally intrusive NDA's, or
waive the NDA requirement entirely.
8.4 Completing the Layout
To complete the layout, we must do the following:
1. Connect the two transistor gates
2. Connect the two transistor drains
3. Connect the PMOS transistor source to Vdd
4. Connect the NMOS transistor source to gnd
5. Connect the substrate to Gnd near the NMOS
6. Connect the substrate to Vdd near the PMOS
7. Add Pins
8. Successfully complete an LVS and DRC
1. Connect the Gates
To connect different the gates, we will draw pieces
of poly on the schematic. The transistors you
created leave the gates in poly and the drain/source
in metal1. To make an electrical connection to any
layer, you can simply draw a new piece of that layer
over an existing piece of that layer.
To draw poly, click on the POLY box on the layer Next, select CREATE/RECTANGLE and draw a series of
palette: rectangles to connect the two gates.
NOTE: If you would like to see how large something
is, you can use the "RULER" command. Select
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MISC/RULER than click once on the start of the
ruler, and a second time on the end of the ruler. NOTE: The label is case sensitive.
The above example shows how you might 4. Connect NMOS source to gnd!
measure the size of a contact
Repeat step 3, only now draw the line of metal-1 beneath
the NMOS transistor, and specify gnd! instead of vdd!
2. Connect the Drains
5. Connect PMOS substrate to Vdd
Repeat the process as described in (1), only this
time you will click on metal1 instead of poly. Draw an NWELL surrounding the entire PMOS transistor,
and extending over (underneath) the metal-1 line above
the PMOS by selecting NWELL from the palette and then
Add / Rectangle.
Select Add / Contact and specify the contact as NTAP:
The editor follows a windows-like interface. Click Place several contacts on the area where the Metal-1 that
on any object to select it. To delete it, press the serves as Vdd overlaps the Nwell.
delete key. To move it, select EDIT/MOVE.
Multiple items can be selected by clicking on them 6. Connect NMOS substrate to Gnd
while pressing the CTRL key.
Select ADD/CONTACT and specify the contact as PTAP.
You can select just an edge of a figure by pressing Place several contacts on the area of the M1 that serves
F4 then clicking on the edge. This allows you to as Gnd near the PMOS transistor.
drag the edge so that you can resize the figure.
You can stay in edge select mode as long as you
like, or leave it by pressing F4 again. 7. Adding Pins
You must indicate where the INPUT and OUPUTS of this
3. Connect PMOS source to vdd! layout are. This must be done so that the tools
understand how the circuit operates.
To do this, draw a line of metal-1 4 lambda wide
and 45 lambda long at the top of the layout. To do this, you create PINS. To create a pin, you select
Connect this metal layer to the source of the Create / Pin and fill in the following form:
We must now identify the metal-1 as vdd!. To do
this, select Add / Label and type vdd! in as the
label. Click once on the metal-1 layer to place the
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Select Verify / Extract.
You must specify the name of the pin, and the layer
it is being created in. This layer must match the
layer which represents the signal in the layout.
Don't forget to click on the CREATE LABEL box. 2. Compare the Extracted View to the Schematic
Once you have filled this out, go to the layout and Select Verify and LVS. The first time you to this, you get
click on some area containing the layer to which the an obnoxious window. Select Form Contents every time.
pin is to be attached. Click a second time to place
Note that this interface is a departure from the
windows standard in what you do not select any
"OK" from the menu above. You just fill it out and
then go click on the layout.
Create the following pins:
Pin Name Layer
vdd! metal1 If Cadence hasn't filled in the fields for you below, fill them
gnd! metal1 in as indicated. HINT: Cadence is notorious for putting the
A poly wrong values in here when you least expect it, so check
Y metal1 them every time.
8.5 Performing an LVS
Performing an LVS involves the following steps:
1. Extract the layout
2. Compare the extracted view to the schematic
3. Identify errors, fix them
4. Repeat steps 1-3 until no more errors exists
1. Extract the layout
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* Open your layout view, re-extract
* Open your extracted view, re-run LVS
3. Identify errors
To see the results of the LVS, click on the OUTPUT
Note that you are comparing the SCHEMATIC
against the EXTRACTED view. If you type
LAYOUT instead of EXTRACTED you will get an
error that has no relationship to the mistake you
Click RUN when done.
After a few moments, you will get the message:
This report was caused by mistyping Vdd for vdd!. It is
Note that the job runs in the background. This indicating that the layout and schematic do not match up.
means you can do other things. Don't make the
mistake of thinking Cadence hasn't submitted the This report means the LVS failed - the netlists did not
job, and submitting it a bunch of times! Click the match. TO get details, select the Info button:
monitor button to see what is happening.
Note that "succeeded" is a misleading word
here. Even if the schematics and layouts do not
match, Cadence says the job has succeeded.
The only time it "fails" is when there is a
problem doing the comparison.
The only problem I have encountered is an error
message that says "The extracted view is older
than the schematic." To fix this "problem":
* Close your extracted and layout views Root causing errors in LVS is NOT EASY!
* Open the schematic view
* Select check and save If you change the layout or schematic, you will have to re-
save it, and repeat from the EXTRACT step.
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When the LVS passes, you will get a message that Possible things that could damage your layout include:
looks like this:
(a) If your layout includes a lower level cell, and you
change that cell, your layout will change instantly.
So be careful when changing cells. Sometimes it is best
to leave the old cell alone and create a new one.
If you must change a cell that is used by a verified layout,
then you will have to re-run DRC and LVS on the layout.
This is similar to the process of having to recompile any
piece of C programming code that uses an #include file
once that #include file is changed.
(b) Inadvertently saving a file over the layout
(c) Going back into the layout to "fix" something, and
inadvertently getting your self into a situation where you
can't get the layout to verify gain.
The second two cases can be avoided by saving copies of
your working layout.
Note that in practice, DRC errors are about 100 times
easier to fix than LVS errors.
10.0 Submitting the CIF File
4.0 Fix Errors and Repeat CIF standard for Caltech Interchange Format.
You are done when you design passes BOTH DRC It is a text-based file format which can be used to describe
and LVS. full custom layouts.
The CIF format is not well defined, so industry uses
9.0 Completing Your Design GDSII, a format created by Cadence but released as a
standard so others can use it.
Once you completed LVS and DRC, you have a
very valuable thing: a verified design. For this class, you will be submitting your labs in CIF
format because it is easier to e-mail.
Protect your design. Save some copies of it. You
could save it to a different library or cell name, but I To generate a CIF file, go to the Command Interpreter
prefer to change the view name. For example, I Window:
as the view name for my layout which has been
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Select File / Export / CIF.
Specify the name of the cell to export:
Cell Name: INV1A
Type the name of the CIF file to create:
Then click OK. Any error messages will be
reported to the CIW. The job runs in background
and takes a moment to complete. When it is done,
you will get a window saying so.
To mail the CIF file to me, type:
mailx -s"Lab1 CIF File" firstname.lastname@example.org <~/lab1.cif
This command, with spaces changed to underscores would read:
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Appendix A: Unix Terminal Window
You may wish to use the Unix Terminal window to manipulate files in your directories.
This section provides some help in doing
Note that you can use the File Manager - you do not need to know how to use Unix to complete this lab
(although most IC designers learn Unix as a matter of necessity).
To open the terminal window, click on the TERMINAL icon (see above for location).
Unix is case-sensitive. If an example shows a command being entered in lower case, you must enter the
command in lower-case. Filenames can contain upper and lower case letters and are also case sensitive.
You may now type Unix commands into this window. These are similar to DOS commands, but there are some
important differences. The table below gives a comparison of Unix and DOS commands:
DOS Command NT Command Unix Equivalent Purpose
Dir dir ll or ls Show files in a directory
Deltree rm xxx /s rm –R s Remove directory and all
subdirectories and files
mkdir mkdir mkdir Create a directory
erase erase rm Remove a file
-- -- man Display help about a
uparrow uparrow Esc-K Scroll through previous
cd cd cd Change directory
xcopy a b /s xcopy a b /s cp –r a b Copy directory
find find grep Locate lines inside a file
with a specific string
type type more Display contents of a file
path path echo $PATH Show the current path
(directories that will be
searched for executables)
cd \ cd \ cd ~ Go to your home directory’s
\ \ / Separator for directory
/xxx /xxx -xxx Format for switches for
The session below provides a sample of a Unix session.
In this session, the words “system /home/kboorom $” are a prompt, and are printed by the Unix system –
you do not need to type these words in yourself.
system /home/kboorom $
system /home/kboorom $ mkdir
usage: mkdir [-p] [-m mode] dirname ...
system /home/kboorom $ mkdir lab1
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system /home/kboorom $ cd lab1
system lab1 $ ll
system lab1 $ vi file1
system lab1 $ ll
-rw-rw-r-- 1 kboorom www 15 Aug 26 13:08 file1
system lab1 $ more file1
THIS IS A TEST
system lab1 $
In this example, the user types mkdir and enter. Because the syntax is incorrect, mkdir displays a short
message regarding the proper syntax.
HINT: You can get immediate help for many commands by typing the command and hitting
Enter. An alternate method is to type “man” and then the command to get the ‘manual pages’
Example: man mkdir.
Next, the user makes the directory, changes the current directory into that directory, and lists the files in it.
The user then runs “vi” to create and edit a file (the commands the user entered into vi are omitted). Then, the
user runs more to view the contents of the file.
The “ll” command displays files in the following format:
-rw-rw-r-- 1 kboorom www 15 Aug 26 13:08 file1
The first column shows the permissions of the file. Three types of access are defined in Unix –
Execute, Read and Write. Permissions can be defined for the owner, the group, and everyone
else. In this example, the owner can read and write the file, the group can read and write the file,
and everyone else can just read the file.
“kboorom” is the Unix user name of the owner. “www” is the name of the group.
“15” is the number of bytes in the file. This is followed by the date and the filename.
For more information: type man ll
'vi' command set
'vi' is a text editor which many engineers use to edit text files.
Although there are other editors, such as Emacs, or the windows- based text editor built into the HPUX systems,
many systems default to 'vi' so engineers often wind up learning how to use it.
To start vi, type vi and the name of the file to edit.
The following is a partial list of the 'vi' command set. 'vi' is case sensitive.
* Arrowed cursor keys work OK – mouse may not.
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* To insert text, type i. To stop inserting, type the Esc key
* To delete a line, type dd
* To delete a character, type x
* To delete a bunch of lines, type nnndd where nnn is the number of lines to delete
* To save the file, type :w and hit enter.
* To quit, type :q
* To quit without saving, type :q!
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Appendix C: Cadence Toolset
We have access to most of Cadence's toolset. But we will only be using the tools listed in Bold below for this
(table courtesy of Iowa State’s Web Site)
Design Framework II TM can be quite intimidating at first, as most students haven't ever worked
with a package of its size or power before. Here's a quick guide to some popular Cadence TM
Analog ArtistTM - Design Framework II TM based analog/mixed-signal design environment
Block EnsembleTM - Design Framework II TM based top level place and router
Cadence- the EDA company who designed the software you are using. Note the tool suite is
not collectively known as "Cadence"
Category - A logic grouping of cells that are displayed in the Library Browser
cdsSpice - Design Framework II TM version of Berkeley's SPICE simulation package
Cell - The basic building block of a design. Each cell has one or more views.
Cell EnsembleTM - channel-based standard cell place and router
Cell3 EnsembleTM - area-based standard cell place and router
CellView - One type of format for representing data in a cell (layout, schematic, etc)
Composer - Design Framework II TM based schematic editor
cWavesTM - graphical waveform viewer for Verilog
Design Framework 2TM (DFII) - X-based applications framework from Cadence
Diva - DFII-based interactive design verification. Provides interactive DRC, ERC, LVS, LPE,
DRC - Design Rule Checking (example: layout spacing errors)
ERC - Electronic Rule Checking (example: shorts between power/ground, impromperly biased
HDL - Hardware Description Lanuage
icfb - Integrated Circuit Design/Front-to-Back. The command used to start Design Framework
II TM and checkout all licenses
Library - The top level where to story design. All files in a library share a common process
Logic Synthesis - The extraction of a gate-level netlist from an HDL description
LPE - Layout Parameter Extraction
LVS - Layout Versus Schematic comparison
Netlist - a representation of data, describing devices and their connectivity
OpenbookTM - CadenceTM's online manual
PRE - Parasitic Resistance Extraction
PreviewTM - Design Framework II TM based floorplanner
SKILLTM - Design Framework II TM's LISP-like scripting language
SpectreTM - Design Framework II TM's improved SPICE-like simulator
SynergyTM - Design Framework II TM's logic synthesis tool
SynopsysTM - Third party logic synthesis tool
VerilogTM - (1) A C-like digital hardware description language. (2) A logic-level simulator for
Verilog Switch-RCTM - The RC switch level simulator for the VerilogTM simulator
Virtuoso - Design Framework II layout editor
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