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					      Dell Confidential                                                                                                      Document No. COR.40.WWP.SQ.0023 Rev 4.0



                                                       PCBA Quality Process Audit
Information and Instructions
                                                                                                                                                                               Rev. 4
PURPOSE
This document was developed as an Audit Tool to assess PCBA Manufacturing Process Capability.
It is intended to provide an assessment of PCBA Manufacturing Capability based on PCBA Manufacturing Complexity.
Less complex PCBA's will not require the same manufacturing capability as more complex PCBA's.
Thus by matching capability with complexity, the most economic manufacturing solution can be determined for a sustained quality performance.
The tool may also be used to assess RMA/Repair Capability.
A qualified auditor may also use this tool as a guideline to conduct a process 'Gap Analysis' based on product complexity.
The Lead Free section of this Audit Tool may be used to audit a suppliers compliance with Dell's "Lead Free Supplier Assessment Survey" and their overall
readiness to produce Lead Free product.

SCOPE
The PCBA Audit Document is primarily intended to be used for suppliers/manufacturers of PCBA Products for Dell.
The audit document may also be used to assess the manufacturing process for any PCBA that is incorporated into a Dell assembly.
When used to assess RMA/Repair Capability, the tool may be used at any location where RMA/Repair activity takes place.
The Lead Free section of this Audit Tool is intended to assess the Lead Free process and product readiness for any supplier whose process or product
includes the production or repair of solder joints. This section of the Audit Tool also applies to any supplier whose process or product uses solder for
mechanical joining of parts.

PCBA COMPLEXITY and CAPABILITY MATCHING
The SQE Auditor will decide what PCBA Complexity category to audit a supplier facility or potential supplier facility against.
This determination is made based on the complexity of the PCBA product to be outsourced or evaluated
To do this, the complexity of the product must first be calculated using Dell Tool COR.40.WWP.SQ.0229. This is available on Value Chain.
Knowing the product complexity, it is then possible to use this tool to make an assessment of the line installed for a product of that complexity.
There are 10 categories of complexity used by Dell, ranging from 1 (Most Complex) to 10 (Least Complex).
In this audit, complexity categories are grouped into five categories as can be seen on the individual audit worksheets.

Lead Free Commodity Complexity Matrix
The Lead Free section of this Audit Tool is divided into 3 commodity complexity categories. The complexity level used for this audit will be determined
by the Dell Commodity team and the Dell SQE.

Category 3 is the highest complexity. This category will include Motherboards assemblies and OEM / ODM manufacturers. Any supplier audited in this
category will be required to complete the lead free section of this Audit Tool, the Supplier Lead Free Assessment Survey, a product level qualification,
L3 Reliability testing as defined in Dell specification D4559, and participate in a Lead Free section of their QBR.

Category 2 is for medium to complex PCBA's. Suppliers with product in this category will be required to complete the lead free section of this Audit Tool, the
Supplier Lead Free Assessment Survey, a product level qualification, L2 or L3 Reliability testing as defined in Dell specification D4559,
and participate in a Lead Free section of their QBR.

Audit requirements are the same for Category 3 and Category 2.

Category 1 is for low complexity PCBA's such as control panels, risers, etc. Suppliers with product in this category will be required to complete the lead free
section of this Audit Tool, and the Supplier Lead Free Assessment Survey. Qualification may be per Level 1 requirements as defined in Dell specification
D4559 or by certificate of compliance, as defined by the Dell Commodity team. If the supplier participates in the QBR process, a Lead Free section will be
added to the QBR score card.

AUDIT BY SELF ASSESSMENT
A supplier's facility is required to complete a self assessment using this tool in advance of the Dell Audit.
By doing this the facility will be able to prepare for the audit and seek advance help and guidance from Dell SQE to be best positioned to succeed.
It is expected that during the self-assessment process, that the supplier will use this opportunity to ask questions for either clarification or to better understand intent of the
audit criteria. Waiting for the formal Dell audit to ask these types of questions is too late. It is also expected that based on self audit results, a supplier will inform the Dell
team of their readiness for a formal Dell audit.
A self assessment is completed by adding a score to the relevant column in each worksheet once product complexity has been determined.
If a facility has multiple lines building Dell product of the same complexity, the supplier shall ensure all lines are available to be audited.
The SQE Auditor will randomly select one line to be audited for the product complexity to be assessed.
During the audit process, the Dell SQE may wish to review every question/criterion listed on the audit document, or alternatively the SQE may choose
to focus only on those questions for which the supplier awarded themselves a score of 1 by self-assessment. The path taken is left to SQE discretion.
The score awarded by the SQE Auditor will be entered in the 'Actual' column on each worksheet.
In this way the delta between the self assessment and the actual score is known. The size of this delta is a measure of audit preparedness and understanding. The
difference between "self score" and "actual score" will be approximately 5% if preparation and understanding is good.
The Lead Free self audit information should come from the suppliers "Lead Free Self Assessment" survey input.

AUDIT RESULTS
The SQE Auditor must complete at least 7 of the 14 processes before an Audit Result can be declared.
It is strongly recommended that all 14 sections of the audit be completed for suppliers who have no previous experience with manufacturing PCBA's for Dell or for existing
Dell suppliers who are attempting to build a higher complexity PCBA product for the first time.
The Lead Free section is mandatory for any audit score.

The overall process average result determines the Audit score achieved for the PCBA Supplier assessed.
The 'Pass' score for the Audit is 80% for all PCBA Products irrespective of complexity.
If an overall process average score of equal or greater than 80% is achieved, and no individual processes have failed, a 'Pass' result is awarded.



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      Dell Confidential                                                                                                         Document No. COR.40.WWP.SQ.0023 Rev 4.0


If one or more individual processes have failed, but an overall Audit score of equal or greater than 80% was achieved, either a "Conditional Pass" or a "Fail" Result shall
be awarded. The determination of this audit result is at the discretion of the Lead SQE Auditor, based on the severity of the issues for any of the failing sections.
If the overall process average score is less than 80%, a "Fail" result is awarded.
NOTE: An individual process fails when the section score is below 80% OR if an "non-negotiable" question scores 0. (see "Audit Mechanics" instructions for additional
information.)

If the "Lead Free" section fails, an overall fail result is awarded.
If the supplier does not receive a passing score on the Lead Free section, then they may not ship Lead Free product to Dell. The supplier must address any
action items associated with the Lead Free section and receive a passing score before shipping Lead Free product to Dell.

If a "Conditional Pass" or "Fail" Result is awarded, a Corrective Action Plan is due from the supplier within two weeks of the date of audit completion.
The Corrective Action Plan must contain a timeline to 'bridge' to a Pass status and must propose a target date for a Dell follow-up Audit.
Failure to achieve a Pass Result on the follow up Audit may impact business award decisions.

A PASS RESULT
Once a supplier's facility has passed the Audit for a particular product complexity, the facility's process is approved for all products of that complexity.
Thus, the facility has proven their capability to build a product of that complexity for the line audited. As long as the same process capability
is deployed for any new lines, there is no need to do 'official' audits for any additional lines added for product of that complexity.
NOTE: While it is not an 'official' requirement to use the audit tool for additional lines, it is strongly advised that the SQE utilize the audit tool to verify that the capability of
any new line is matched to the existing capability of the existing lines for a given PCBA complexity.
NOTE: For the purpose of "proven capability to build a product", a "facility" is defined as the same physical building, AND the same product complexity, AND the same
supplier production and quality management team resources.

If a facility is approved for the most complex PCBA product, this does NOT necessarily mean they are automatically approved for all less complex products at that facility.
Regardless of product complexity level, any test processes related to a new product should be audited because test processes are unique, based on product type, not
PCBA process complexity.

An Audit will need to be conducted to ensure the capability deployed at least meets the minimum requirements for the less complex product.


A suppliers facility must pass the Lead Free section of the audit before they will be allowed to ship Lead Free product to Dell. A minimum score of 80% must be
obtained to pass the Lead Free section.

AUDIT MECHANICS and QUESTIONS
The Audit breaks down the PCBA Manufacturing Process into individual process steps, each of which is represented by an individual worksheet.
Within each worksheet is contained a series of questions specifically pertaining to the process being examined.
These questions are focused on evaluating Process Disciplines, Control Methods, Process Capability/Technology, and Attention to Detail.
The questions were devised and developed as closed questions with every attempt to avoid ambiguity.
Because of the closed nature of the questions, there can only be one of two answers to any question, i.e. Yes (1) or No (0).
Thus, the criterion is either fully met or it is not. If the Criterion is met, a score of 1 is obtained. If the Criterion is not met, a score of 0 is obtained.
If there is any doubt as to the score to award for any given Criterion, a score of zero shall be awarded by default.
Any Criterion that scores 1 shall be clearly demonstrated, followed, and be beyond reproach.
In the event that a supplier clearly meets the intent of the audit question, but does not exactly do what the question asks, a score of 1 shall be given.

There are cells within the audit document that are shaded in gray. These cells may be coded as Not Applicable (NA) under certain conditions.
If coded NA, the denominator in the score percentage calculation will automatically be adjusted to account for this NA allocation to the cell.
The conditions under which NA may be allocated are as follows:-
1. NA may be allocated to a cell if the question is not applicable to the product due to some 'real' physical reason.
    For example, if there are no MSD devices are on a product, then the questions pertaining to MSD's would be coded NA.
2. NA may be allocated to a cell if the question is not applicable to the product because the physical product does not undergo a specific process.
    For example, if there are no press fit connectors on a product, then the questions pertaining to the press fit process may be coded NA.
3. NA may be allocated to a cell if by answering some questions 'yes', other questions become redundant or irrelevant.
    For example, if AOI is deployed, then the questions pertaining to Manual Inspection may be scored NA

Note 1: Not all gray shaded questions will be coded NA. The NA status is conditional on the above and SQE discretion.
Note 2: Gray shaded cells are applicable when the process is deployed, and may still score zero if the above conditions are not satisfied.
          For example, AOI is not required for complexity 5 PCBA's, but it may be deployed based on supplier preference
          If AOI is deployed, AOI questions must be scored 1 or 0, not NA.
Note 3: No other questions, other than those that have been predetermined by the gray shading, can be considered to be NA.

There are certain questions in each section, (shaded in blue), that are considered non negotiable (NN). In other words the question must score a 1.
If any of these questions score a 0, then the process section under review will automatically fail (NN Fail), regardless of overall score.
For example, if the overall result for a section is equal to or greater than 80% and if any one of the "non negotiable" questions scored a zero, then the overall result for that
section will be Fail, irrespective of the overall score.

AUDITING A NEW SUPPLIER OR A NEW SUPPLIER FACILITY
If a potential supplier or new supplier facility is required to be audited then the category to be completed in the audit document shall
appropriately reflect the complexity of the product to be manufactured.
However, since such a supplier/facility will not be manufacturing a Dell product the SQE Auditor will have to select a line with a product which
most closely matches the product to be manufactured and which is representative of the production line that the supplier intends to use to build Dell product.
The SQE will not consider auditing a 'virtual' line based on some future installed capability.

The Lead Free section is required to be audited for all new suppliers for facilities.

AUDITING FOR RMA/REPAIR
This tool may also be used to assess capability of RMA/Repair facilities.
All process highlighted on the Menu page are relevant for when it is necessary to conduct a Manufacturing Process QPA

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      Dell Confidential                                                                                                    Document No. COR.40.WWP.SQ.0023 Rev 4.0

However, only those menu buttons highlighted in 'blue' an applicable sections of the Lead Free section (3.8 - 3.14, 4, 6, 7, 8, 9) may be used
for a Repair/RMA QPA Audit.

TRAINING
The PCBA Process Audit is very technical in content.
SQE's who use this tool are considered within Dell as being sufficiently qualified to conduct this audit.
To obtain this qualification, an SQE will have participated in at least three audits and lead a fourth under the supervision of a qualified auditor.
SQE's wishing to use this tool should contact their regional champion to arrange for training, qualification and certification.

SQE's should receive training on Dell's Lead Free implementation strategy before conducting the Lead Free audit.

AUDIT SCHEDULE
The Audit may be used as and when the need arises. However, Dell will conduct an official audit at least annually for key suppliers. Before conducting
an audit, the auditor must ensure the Dell commodity management team responsible for the relationship are advised of the audit schedule.
It is also intended for suppliers to conduct internal audits by self assessment every quarter so progress may be reported to Dell.

ADDITIONAL QUESTIONS
Please contact Eric Hoh at eric_hoh@dell.com for additional information or if there are any specific questions with regard to the technical content.
Please contact Wallace Ables at wallace_ables@dell.com for additional information on the Lead Free section of the score card or to provide comments or
corrections.

REVISION HISTORY
A00 Initial Release. Oct 1996 (EMF Controlled Document). Authored by William Ryan
A01 Minor corrections. Dec 1996. (EMF Controlled Document). Changes by William Ryan
Rev 1.4 Addition of RMA and Test Update. Jan 1999. (Initial Release as a Corporate Document). Changes by Wallace Ables.
Rev 2.0 Extensive Review and Re-Write. July 2002. Authored by William Ryan.
Rev 3.0 Changes Listed Below. Authored by William Ryan.
             Listed the non-negotiable items for PCBA Manufacturing.
             Added details and rules to the instruction sheet for clarity.
             Edited approximately 50% questions to increase clarity.
             Removed hard NAs and placed rules in place for the use of NA.
             Removed requirement for self-calibrating soldering irons,
             Added rules on how may sections to be audited before a result can be declared.
             Remove AOI requirements for Desktops.
             Removed any inference to specific machinery/equipment manufacturers.
             Changed PCBA categories to align with the Complexity Model.
             Added MSD requirements to meet latest JEDEC standard.
Rev 4.0 Added the Lead Free audit section. Authored by Wallace Ables
             Added instructions for the Lead Free audit




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Dell Confidential                                                    Document No. COR.40.WWP.SQ.0023 Rev 4.0




                                 PCBA Quality Process Audit
Main Menu
                                                                                                      Rev. 4

                      SMT             PTH               Test                       General

                Paste Printing   Manual Assembly   In Circuit Test                  Lead Free



                    Placement    Wave Soldering    Functional Test               General Process



                     Reflow        Post Wave                                     Rework & Repair



                                 Mechanical Assy                                  RMA Process



                                  Instructions        Results                        Packing




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      Dell Confidential                                                                                                                                                                        Document No. COR.40.WWP.SQ.0023 Rev 4.0




                                               PCBA Quality Process Audit                                                                             Menu

Process Audit Results
                                                                                                                                                               Rev. 4
                             Supplier Name:                                                       Building:                           Date:
                              Facility Name:                                               Line Assessed:                             Team:
                     Dell Product Reviewed:                                              Total # Dell Lines:


Audit Results                                                                                                    1, 2        3, 4     5, 6     7, 8   9, 10   RMA       PCBA Complexity
                                                  (Please type Y for the Product Type audited or RMA audit)
Lead Free Commodity Complexity                                                                                   3,2          1      RMA                                Commodity Complexity
                                               (Please type Y for the Complexity Type audited or RMA audit)

                            Self Score             Dell Score         Pass Score          Max Score              Outcome            Comments

1. Lead Free                                                              80%                100%              Not Audited
2. Paste Printing                                                         80%                100%              Not Audited
3. Placement                                                              80%                100%              Not Audited
4. Reflow                                                                 80%                100%              Not Audited
5. Manual                                                                 80%                100%              Not Audited
6. Wave Soldering                                                         80%                100%              Not Audited
7. Post Wave                                                              80%                100%              Not Audited
8. Mech Assembly                                                          80%                100%              Not Audited
9. In Circuit Test                                                        80%                100%              Not Audited
10. Fn Test                                                               80%                100%              Not Audited
11. General                                                               80%                100%              Not Audited
12. Rework & Repair                                                       80%                100%              Not Audited
13. RMA Process                                                           80%                100%              Not Audited
14. Packing                                                               80%                100%              Not Audited

                            Self Score          Dell Score            Pass Score             Result
  Overall Score Not Audited                    Not Audited                80%                                  Enter Result
                                                                                                                                    SQE Comments on Result

                                                      1. Lead Free
                                                     100%
                                    14. Packing                           2. Paste Printing
                                                      80%
                    13. RMA Process                                                  3. Placement
                                                      60%

                                                      40%
           12. Rework & Repair                        20%                                 4. Reflow

                                                        0%

                     11. General                                                          5. Manual



                          10. Fn Test                                                6. Wave Soldering


                             9. In Circuit Test                            7. Post Wave
                                                   8. Mech Assembly




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             Dell Confidential                                                                                                                                                                   Document No. COR.40.WWP.SQ.0023 Rev 4.0


                                                                                      PCBA Quality Process Audit
                                                                                                                                                                                          Menu
 Lead Free Supplier
 Assessment Ref. #
                      Lead Free Assessment Question                        Instructions
                                                                                                                                                                             Return to Lead Free Sheet


                        #                                           Audit Criterion                                                                           Dell Auditor Instructions
                      1. Definition of Lead Free
                                                                                                                           Verify that the supplier has obtained a copy of Dell specification D4394. This
                                                                                                                           specification defines the allowable levels of Lead for Dell lead free products. The
                                                                                                                           allowable levels of Lead to be in compliance with the RoHS directive have not been
ENG 1.1a1.1                                                                                                                finalized. Until this legislative requirement is finalized, Dell has adopted a conservative
                                                                                                                           (lower) acceptable level of Lead. If the final legislation allows a higher level of Lead in
                             Have you received the "General Specification for Allowable Levels of Lead (Pb) in Dell        electronics, then Dell will adjust their requirements to align with the legislative
                             Products" (Dell P/N D4394)?                                                                   requirements.

ENG 1.1b1.2
                                                                                                                           Verify that the supplier agrees with Dell's definition of allowable levels of Lead and that
                                                                                                                           the suppliers process and product will be in compliance with the requirements for D4394.
                             Do you agree with the definitions?
                                                                                                                           The RoHS directive allows exemptions for lead in specific components and applications.
                                                                                                                           If any of the suppliers process or materials will contain any Lead above the requirements
                                                                                                                           in D4394, the material or component must fit one of the proposed exemptions. The
ENG 1.2               1.3
                                                                                                                           supplier must provide you with a list of all components and materials they plan to ship to
                             Have you identified all parts that require exemption to the RoHS requirements with            Dell that will contain any Lead, and the appropriate exemption that applies to each
                             detailed information surrounding why the exemption is required?                               material or component.
                                                                                                                    Any materials or components that contain Lead above the allowable levels in D4394
                                                                                                                    must be replaced with compliant Lead Free materials. In most cases, this means the
                                                                                                                    supplier will source a different component or material that is in compliance. At this time,
                                                                                                                    many components, and some raw materials, are not available in a Lead Free, High
ENG 1.3               1.4                                                                                           Process temperature compliant form factor. The supplier must have identified all of
                                                                                                                    these materials and components and have a sourcing plan (schedule) for a Lead Free
                                                                                                                    compliant version of the component or material. A list of components or materials that
                             Do you have an action plan for every part that is non-RoHS compliant and does not have contain Lead along with the Lead Free source and availability schedule will fulfill this
                             an exemption?                                                                          requirement.
                      2. Lead Free Sub-Tier Management
                                                                                                                           The supplier should have a Corporate document similar to Dell's D4394 that defines their
SQE 1.1               2.1    Does your company have a Corporate wide "Lead Free" specification that defines your           requirements for Lead Free materials and finished assemblies. Have the supplier
                             companies requirements for "Lead Free" raw materials and finished product?                    provide you with a copy of this document for your verification.

                                                                                                                           Has the supplier already provided Dell with a copy of this document? If not, then obtain
SQE 1.2               2.2                                                                                                  a copy of the document. If the supplier does not have a document, or will not provide
                                                                                                                           Dell with a copy of the document, then they will not receive credit for this question.
                             Has a copy of your Corporate "Lead Free" specification been provided to Dell?
                                                                                                                           This question is intended to understand what system the supplier will use to make sure
                                                                                                                           all of the sub-tier suppliers will be in compliance. You are looking for a tracking method
SQE 1.3               2.3
                             Have you established a complete list of your sub-tier suppliers to be used to track           the supplier is using to identify their entire sub-tier supply base and to track each sub-tier
                             compliance with your "Lead Free" requirements?                                                suppliers compliance status.

                                                                                                                           The supplier should have sent a copy of their Lead Free requirements document to each
SQE 1.4               2.4                                                                                                  of their Sub-tier suppliers. You are looking for a tracking method to document which sub-
                             Have you sent a copy of your "Lead Free" specification and requirements to all of your
                                                                                                                           tier supplies have been sent their Lead Free requirements document.
                             sub-tier suppliers?
                                                                                                                           Sending a document to a sub-tier supplier does not necessarily mean the supplier has
                                                                                                                           received or read the document. You are looking for evidence that the supplier has a
SQE 1.5               2.5
                             Do you have an updated list of your sub-tier suppliers that acknowledge receipt of your       closed loop follow up verification system in place to make sure each sub-tier supplier
                             "Lead Free" specification and requirements?                                                   acknowledges receipt of the Lead Free specification.

                                                                                                                          The complete list of sub-tier suppliers should document and track the status of
                                                                                                                          compliance of each supplier. This may be tracked by part number instead of supplier.
SQE 1.6               2.6
                                                                                                                          The primary point you are trying to verify is that the supplier has a system in place to
                             Do you have an updated list that tracks the compliance status of each sub-tier supplier to track the current status of Lead Free compliance from each of their sub-tier suppliers.
                             your "Lead Free" specification and requirements?
                                                                                                                          Each supplier is expected to have an internal operation procedure or work instruction for
                                                                                                                          the personnel in the receiving or incoming inspection area that tells them how to verify if
                                                                                                                          materials received are in compliance with their "Lead Free" specification requirements.
                                                                                                                          Compliance checking may be done by in house analytical testing, outside (3rd party
SQE 1.7               2.7                                                                                                 vendor) analytical testing, by certificate of compliance from the sub-tier vendor, or some
                                                                                                                          other method. You must make a judgment call on whether you believe the verification
                             Do you have an Operating Procedure in place at your receiving or incoming inspection         procedure is adequate to ensure materials are properly verified. If the procedure does
                             area that documents procedures for verification of compliance with your "Lead Free"          not exist, or you do not feel that it is adequate, the supplier will not get credit for this
                             specification for incoming materials?                                                        question.
                                                                                                                          Audit the incoming or receiving inspection records for several part numbers to verify that
                                                                                                                          the materials have been properly verified according to their procedure. There must be
SQE 1.8               2.8
                             Do you have records that demonstrate your Incoming Materials area is in compliance           document records that verifies compliance for every part number / shipment received by
                             with the Verification operating procedure?                                                   the supplier.
                                                                                                                          The intent of this question is to verify the suppliers ability to test incoming materials for
                                                                                                                          Lead content. This may be done in house by the supplier or at an outside 3rd party
                                                                                                                          vendor. In some cases, materials received will not be clearly marked as to their Lead
                                                                                                                          Free status. For example, some component vendors will not be changing their
                                                                                                                          component part number when they transition from Leaded to Lead Free. Instead, they
SQE 1.9               2.9
                                                                                                                          will publish a lot code date when the transition occurred. This may be confusing if the
                                                                                                                          Incoming and Receiving area does not know the lot code that is lead free. If there is
                             Do you have analytical testing capability, either at your incoming inspection area or at a reason to suspect materials may contain lead, or if the supplier wishes to do a spot audit
                             local 3rd party analytical testing vendor, available to perform testing on a sample basis to for compliance, they must have analytical testing capability in place to check for Lead
                             verify Lead Free compliance of incoming materials?                                           content.

                                                                                                                           This question is intended to probe how well the supplier understands and controls what
                                                                                                                           lead free alloys are being used by it's sub-tier suppliers. The supplier should have
N/A                   2.10                                                                                                 records or data that documents what type of alloy is being used by their sub-tier
                                                                                                                           suppliers. The supplier should also have some form of documentation they use to
                            Can you define, control and provide traceability thereof for the solder alloy mix being
                                                                                                                           specify what type of lead free alloy their sub-tier suppliers are allowed to use.
                            used by your sub-tier suppliers?
                      3. Tin-Silver-Copper (Sn-Ag-Cu) Alloy Process Development
                                                                                                                           Has the supplier provided Dell with a copy of the specifications (usually a vendors data
ENG 3.1               3.1                                                                                                  sheet) for their Lead Free solder paste? If more than one solder paste has been
                                                                                                                           qualified by the supplier, then they must provide a data sheet for each solder paste.
                             Have you provided Dell a copy of the specifications on your Lead Free solder paste?




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    Dell Confidential                                                                                                                                                       Document No. COR.40.WWP.SQ.0023 Rev 4.0


                                                                                                     The supplier should have completed a statistically valid Design of Experiments to
                                                                                                     evaluate multiple SnAgCu solder pastes, PCB surface finishes (Immersion Silver, Entek /
                                                                                                     OSP, Ag, etc) and reflow process parameters. The supplier should be able to review
SQE 2.1   3.2
                                                                                                     their DOE data with you to support their selection of Solder Paste, Surface finish, and
                                                                                                     reflow profile. If the supplier has not completed a valid DOE, but has selected the solder
                 Have you completed a Design of Experiments (DOE) to evaluate multiple SnAgCu solder
                                                                                                     paste based on a few quick experiments, they should not receive credit for this question.
                 paste alloys, surface finishes, and process parameters for your SMT process?
                 Do you have DOE qualification data for your SnAgCu SMT process that meets the       The supplier should have reliability test data results from their DOE that meets the test
SQE 2.2   3.3
                 requirements of Dell's "Lead Free Qualification Requirements", document D4559?      plan requirements of Dell document D4559.
                                                                                                     Has the supplier provided Dell with a copy of the specifications (usually a vendors data
                                                                                                     sheet) for their Wave Solder alloy? If more than one solder alloy or brand has been
ENG 3.2   3.4
                                                                                                     qualified by the supplier, then they must provide a data sheet for each solder alloy or
                 Have you provided specifications on your Lead Free Wave Solder (Flow Solder) alloy? brand.
                                                                                                     Has the supplier provided Dell with a copy of the specifications (usually a vendors data
ENG 3.3   3.5                                                                                        sheet) for their Wave Solder flux? If more than one solder flux has been qualified by the
                 Have you provided specifications on your Lead Free Wave Solder (Flow Solder) flux?  supplier, then they must provide a data sheet for each solder flux.
                                                                                                         The supplier should have completed a statistically valid Design of Experiments to
                                                                                                         evaluate multiple lead free wave solder alloys (SnAgCu or SnCu), PCB surface finishes
                                                                                                         (Immersion Silver, Entek / OSP, Ag, etc), wave solder fluxes, and wave solder process
                                                                                                         parameters. The supplier should be able to review their DOE data with you to support
SQE 2.3   3.6                                                                                            their selection of Wave Solder Alloy, Surface finish, wave solder flux, and wave solder
                                                                                                         temperature profile, and other wave solder process parameters. If the supplier has not
                 Have you completed a Design of Experiments (DOE) to evaluate multiple SnAgCu or         completed a valid DOE, but has selected the wave solder materials and process
                 SnCu solder alloys, surface finishes, and process parameters for your Wave Solder       parameters based on a few quick experiments, they should not receive credit for this
                 process?                                                                                question.
                 Do you have DOE qualification data for your SnAgCu or SnCu Wave Solder process that
                                                                                                     The supplier should have reliability test data results from their DOE that meets the test
SQE 2.4   3.7    meets the requirements of Dell's "Lead Free Qualification Requirements", document
                                                                                                     plan requirements of Dell document D4559.
                 D4559?

                                                                                                         Has the supplier provided Dell with a copy of the specifications (usually a vendors data
                                                                                                         sheet) for their Wave Solder Machine. We are looking for evidence that the solder pot /
SQE 2.5   3.8
                                                                                                         solder pump material is compatible with lead free solder. Solder pots / solder pumps
                 Do you have documentation from your Wave Solder equipment vendor that verifies that     designed for Sn-Pb machines will be dissolved by lead free solders.
                 the equipment is compatible with the SnAgCu or SnCu alloy selected?
                                                                                                         Has the supplier provided Dell with a copy of the specifications (usually a vendors data
                                                                                                         sheet) for their rework and repair Lead Free alloy? If more than one solder alloy or brand
ENG 3.4   3.9
                                                                                                         has been qualified by the supplier, then they must provide a data sheet for each solder
                 Have you provided specifications on your Lead Free rework / repair solder alloy?        alloy or brand.
                                                                                                         Has the supplier provided Dell with a copy of the specifications (usually a vendors data
                                                                                                         sheet) for their rework and repair Lead Free flux? If more than one solder flux has been
ENG 3.5   3.10
                                                                                                         qualified by the supplier, then they must provide a data sheet for each solder flux or
                 Have you provided specifications on your Lead Free rework / repair flux?                brand.

                                                                                                     The supplier should have completed a statistically valid Design of Experiments to
                                                                                                     evaluate multiple lead free rework alloys (SnAgCu), PCB surface finishes (Immersion
                                                                                                     Silver, Entek / OSP, Ag, etc), and rework fluxes, and rework process parameters for each
                                                                                                     major form factor of component (BGA's, QFP, 0603, PTH, etc). The supplier should be
                                                                                                     able to review their DOE data with you to support their selection of the rework alloy,
                                                                                                     rework flux, rework equipment, rework temperature profile, and other rework process
SQE 2.6 3.11                                                                                         parameters for each component form factor. The DOE should also verify that solder
                                                                                                     joints of component adjacent (150 mils or more) to the reworked component are not
                                                                                                     reflowed or disturbed during the repair cycle. If the supplier has not completed a valid
                                                                                                     DOE, but has selected the rework materials, equipment, and process parameters based
                                                                                                     on a few quick experiments, they should not receive credit for this question. If
             Have you completed a Design of Experiments (DOE) to evaluate multiple SnAgCu solder temperatures of adjacent component solder joints have not been verified, the supplier
             alloys, surface finishes, and process parameters for your rework process for each major should not get credit for this question.
             component form factor (BGA, QFP, 0603, PTH, etc.)?
                                                                                                         The supplier should have reliability test data results from their DOE that meets the test
               Do you have DOE qualification data for each SnAgCu component rework process that          plan requirements of Dell document D4559. The supplier does not have to perform
SQE 2.7   3.12 meets the requirements of Dell's "Lead Free Qualification Requirements", document
                                                                                                         dedicated rework evaluations. Rework may be evaluated and qualified as part of their
               D4559? Rework can be qualified as part of the SMT and Wave Solder process                 SMT and Wave Solder qualification experiments by doing forced rework.
               qualification as forced rework locations on the test boards.
                                                                                                         Lead Free rework will require higher temperature profiles. This may require new rework
                                                                                                         equipment with higher heating capability for preheat (bottom or top side) and for reflow.
                                                                                                         Many suppliers are also using rework tooling with Nitrogen capability, to provide better
                                                                                                         wetting during rework. All rework tips and nozzles that come in contact with the Lead
SQE 2.8   3.13
                                                                                                         Free solder must be made from a material that is compatible with SnAgCu solder. Solder
                                                                                                         tips and nozzles for SnPb solder will be quickly corroded and damaged by SnAgCu
                 Have you identified all new requirements for your Lead Free rework tool set, for each   solder. All rework tips and nozzles must be new. SnPb tips and nozzles may not be
                 major component package type? Examples would include a new type of rework tool, a       reconditioned to be used for Lead Free rework.
                 different rework tool material of construction, Nitrogen atmosphere requirement, etc.
                                                                                                         The supplier should have component temperature measurements for each component
                                                                                                         package type to ensure that the component temperature specifications are not being
                                                                                                         violated during rework. The supplier should also have measurement data to verify that
SQE 2.9   3.14                                                                                           localized board warpage is within acceptable limits after each rework process. The
                                                                                                         supplier should have measurement data to show that BGA solder joints are uniform size
                                                                                                         and height across the package after rework. Warpage during BGA rework will cause non-
                Have rework risks have been documented for each major component package type
                                                                                                         uniform solder joint width and height which will reduce the reliability of the solder joints.
                (board warpage, component delamination, etc.).
          4. Optimization of SnAgCu Alloy Process

                                                                                                         The supplier should have DOE data to support the optimized process parameters for
                                                                                                         their SnAgCu assembly process. Examples of process parameters that should be
                                                                                                         evaluated are: optimized solder stencil design parameters, placement accuracy
                                                                                                         requirements, reflow profile parameters (ramp rates, dwell times, time above liquidus,
SQE 3.1   4.1
                                                                                                         max / min temperatures, cool down rates, conveyor speed), wave solder profile
                                                                                                         parameters, wave solder defects (solder balls, shorts, hole fill, warpage, flux residue),
                 Has each step of the assembly process (screen print, placement, reflow, fabrication,    test probe performance with SnAgCu alloy and flux. After completion of the Optimization
                 assembly, test, rework, etc.) been optimized by the use of a DOE or other statistical   DOE work, the supplier should be able to identify their Lead Free process capability.
                 process tool?
SQE 3.2   4.2                                                                                            The supplier should have a documented DOE plan and results for question 4.1.
                 Are the DOE plans and results documented to support your optimized process settings?
                                                                                                         The results for the suppliers Optimization DOE should be documented in their process
                                                                                                         setup documentation. This documentation may be in the form of Operating Procedures
                                                                                                         for the Operators, Set up instructions for the Technicians / Engineers, a Engineering /
SQE 3.3   4.3
                                                                                                         Quality procedure, etc. Any of these are acceptable as long as the optimized setup
              Are your optimized process and assembly settings documented in a procedure or              instructions are documented for the personnel who are responsible for performing the
              specification?                                                                             setup.
        5. Lead Free manufacturing risks
              Have you identified and documented the key manufacturing and process risks that must
                                                                                                         Based on the DOE work in questions 4.1 to 4.3, the supplier should have a list of key
              be controlled in your "Lead Free" manufacturing process (i.e. stencil design, PCBA
SQE 4.1 5.1                                                                                              manufacturing risks, manufacturing controls, process setup requirements, etc. that are
              design changes, temperature profile parameters, use of Nitrogen, inspection criteria, part
                                                                                                         verified when setting up the process for a new Lead Free part number.
              number control, segregation from non-lead free materials, etc.)?



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                                                                                                              The supplier should have pre-defined controls, quality checks / audits, process set up
SQE 4.2   5.2                                                                                                 check list, etc. to ensure that the identified risks are controlled. Typically, a PFMEA will
                                                                                                              be performed on the optimized process to identify these risks and define control plans.
                 Do you have risk mitigation control plans identified for each risk?
                                                                                                              This is only required as the supplier is developing and implementing their Lead Free
                                                                                                              process. As risk areas are identified (from the suppliers DOE or PFMEA), they should
SQE 4.3   5.3                                                                                                 document their findings. We are asking the supplier to provide Dell with a copy of
               Are you providing Dell a monthly status on the implementation of each risk mitigation          whatever report they are using internally to track the progress on evaluating and
               control plan?                                                                                  eliminating these risks.
          6. Component MSL Controls
                                                                                                              Due to the higher reflow, wave solder, and rework temperatures some components will
                 Higher assembly and rework process temperatures will require components to be                have a higher moisture sensitivity level (MSL) than equivalent SnPb components. The
SQE 5.1   6.1    controlled at higher MSL levels. Do you have documentation that identifies the MSL           supplier should have a list of the moisture sensitivity levels, as identified by the
                 levels for all "Lead Free" components and assemblies for your Optimized "Lead Free"          component vendor, for all moisture sensitive devices (MSD) used on Lead Free
                 assembly process?                                                                            products.
                                                                                                              The supplier should have the appropriate Moisture Sensitive Device controls and
SQE 5.2   6.2    Do you have procedures, equipment, storage facilities, etc. in place to implement the        procedures in place for the MSL for each component. Controls and procedures for Lead
                 appropriate controls for each MSL level?                                                     Free MSD's are specified in J-STD 02D.
                                                                                                              The supplier's Quality Department should have audit records where they are verifying
SQE 5.3   6.3    Do you have documentation or audit records to verify that the appropriate MSL controls       that components are being properly stored and handled per each components MSL
                 are being properly implemented and controlled in your "Lead Free" assembly process?          requirements.

                                                                                                              Once a component is rejected by the SMT placement machines, it is very difficult for any
                                                                                                              supplier to accurately track the exposure time out of package for any MSD. You should
                                                                                                              review the controls / system the supplier has in place to ensure that rejected components
                                                                                                              are accurately tracked and controlled with the appropriate MSL procedures. If rejected
SQE 5.4   5.4                                                                                                 components are moved to the rework / repair area of use on repaired boards, then the
                                                                                                              supplier must have a method in place to accurately track the total exposure time on any
                                                                                                              MSD. One method of control is to require baking of any rejected SMT components
                                                                                                              before being taken to the repair area MSD storage. This will provide a know MSD
                                                                                                              condition for all components in the rework area.
                 Are MSL controls in place for components rejected from the SMT placement machines?
                                                                                                              Audit the suppliers MSD component storage, tracking, and controls for replacement
                                                                                                              components in the rework areas. Verify where the replacement components come from.
SQE 5.5   5.5                                                                                                 Components pulled form new stock, taken from the SMT lines, or rejected from the
                                                                                                              process floor will have a different exposure time when placed in storage in the rework
                Do you have MSL controls in place for your "Lead Free" rework / repair process?               area.
          7. "Lead Free" pass / fail criteria
                                                                                                              Verify that the supplier has what is an acceptable Pass / Fail criteria for a Pb Free solder
                                                                                                              joint. SnAgCu solder joints reflowed in air will have a very dull, grainy appearance
SQE 6.1   7.1
                                                                                                              compared to SnPb solder joints. If the supplier says that the pass / fail criteria has not
                 Has the pass / fail criteria for "Lead Free" assemblies been updated?                        changed, then they should not get credit for this question.
                                                                                                              Verify that the supplier has updated documentation for their inspectors and quality
                                                                                                              auditors that identifies the pass / fail criteria for a SnAgCu / Pb free solder joint. These
SQE 6.2   7.2                                                                                                 will be different. If the suppliers says the criteria are the same or has not changed, then
                 Have the inspection procedures been updated for the new "Lead Free" pass / fail              they should not get credit for this question. The solder joints will look different, so the
                 criteria?                                                                                    Quality inspectors will need updated instructions.
                 Have the inspection and assembly training documentation been updated for the new             The Operator / Inspector training material should be updated to include the new pass /
SQE 6.3   7.3
                 "Lead Free" pass / fail criteria.                                                            fail criteria for SnAgCu / Pb free solder joints.

                                                                                                              Verify that the suppliers has a lead free solder joint workmanship inspection guideline
N/A       7.4    Have all Personnel been trained for Lead-Free solder joint inspection? Requires a copy       and training process. Audit training materials and training records to verify compliance.
                 of training documentation and instruction process.
                                                                                                              The suppliers inspection process should include instructions to inspect for thermal
                                                                                                              related damage to the components and PCB's. These instructions should in include
          7.5
                Does your lead free pass / fail criteria include criteria for identifying thermal damage of   criteria for identification of thermal damage, such as warpage, discoloration,
                the PWB and components?                                                                       delamination, etc., along with examples of each type of damage.
          8. Lead Free Product Segregation Controls
                 Have all operating procedures and documentation been updated to include "Lead Free" Verify that the operating instructions, training procedures, etc. have been updated to
                 product / materials segregation and handling requirements to prevent mixing "Lead Free" include the requirements for keeping leaded and lead free materials and assemblies
SQE 7.1   8.1    from "Lead Containing" product?                                                         separated (segregation controls).
                                                                                                         Verify that any Pb Free labeling / marking requirements that the supplier has
                                                                                                         implemented for segregation control have been included in the appropriate procedures /
                                                                                                         instructions. You are trying to verify if the supplier has documented their labeling /
                                                                                                         marking / segregation controls for Pb Free product. If any of the controls the supplier
                 Have all labeling and marking documentation or specifications been updated to include   has described to you are not documented in their procedures, then they should not get
SQE 7.2   8.2    "Lead Free" labeling and marking requirements?                                          credit for this question.

                                                                                                              Verify that all lead free manufacturing areas, rework areas, storage areas, WIP storage
                 Are all lead-free manufacturing, rework and storage areas for raw materials, WIP, and        (racks, carts, etc), and finished goods are labeled and isolated from leaded materials.
N/A       8.3    finished goods clearly labeled and isolated from each other?
                                                                                                              You are looking for audit records to verify that the supplier is performing internal audits of
                                                                                                              the Pb Free segregation controls. If the supplier is not doing internal audits, or does not
                 Do you have audit requirements and results to verify compliance with your "Lead Free"
                                                                                                              have records of the audits, then they should not get credit for this question.
SQE 7.3   8.4    segregation and labeling procedures?
                 Do you have a documented procedure to prevent returned "Lead Free" product (from             The supplier must have a documented procedure that explains to their personnel how to
                 Dell manufacturing lines or Field returns) from being mixed with "Lead Containing"           sort Leaded from Lead Free product that is returned to their factory. This may be part of
SQE 7.4   8.5    product?                                                                                     their overall Pb Free product segregation control procedure.
                                                                                                              You will need to evaluate the suppliers Pb Free segregation control procedure for
                                                                                                              exposure to operator error. If the controls are manual and require an operator to decide
                                                                                                              how to sort or store Pb Free product, then it the control is subject to human error.
                                                                                                              Eventually, a mistake will be made. You are looking for an automated system (preferably
                                                                                                              bar code / scanner driven), that will eliminate the possibility of human error.
SQE 7.5   8.6    Is this procedure automated and not subject to failure caused by operator error?
                                                                                                              This question on applies if the supplier is using more than one Pb Free alloy in their
                                                                                                              factory. They may have different Pb Free requirements from other customers. If this is
                                                                                                              the case, then all of their Pb Free segregation controls must also include identifying
                                                                                                              which Pb Free alloy is to be used or has been used. If multiple alloys are used and the
                 If you use more than one alloy of Lead Free solder for SMT, Wave Solder, or rework,          Pb Free controls does not identify which ally has been used, then the supplier should not
                 then you must have procedures and controls in place to identify and segregate products       get credit for the Pb Free segregation control questions.
SQE 7.6   8.7    with each alloy. Are these procedures and controls in place?
                Do you have an identification / marking system in place to validate labeling of leaded and Verify that the final packaging has a unique part number and / or labeling for leaded and
                lead-free assemblies prior to shipment? Reference Dell Inbound Packaging Specification lead free assemblies.
N/A       8.8 P\N 15000.
          9. Lead Free Part Number and BOM Control

                                                                                                              The supplier must have a documented policy requiring a unique part number for Lead
                                                                                                              Free components and materials from their sub-tier suppliers, when an equivalent leaded
                                                                                                              component or material is available. If the supplier does not have this policy, or if it is not
                 Do you have a corporate specification requiring unique part numbers for Lead Free            documented, then they should not receive credit for this question.
SQE 8.1   9.1    components and materials from your sub-tier suppliers?




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                                                                                                       The supplier must have a documented policy requiring a unique part number for Lead
                                                                                                       Free assemblies they produce, when the equivalent assemble is produced with leaded
              Do you have a corporate specification or procedure requiring a new part number for Lead components or materials. If the supplier does not have this policy, or if it is not
SQE 8.2 9.2   Free assemblies shipped to your customers?                                               documented, then they should not receive credit for this question.
                                                                                                       The supplier should be able to identify if a component is Lead Free by looking at their
              Have all for your internal BOM structures been modified to identify lead free components internal BOM or in their MRP system. This will require the supplier to add a Lead Free
SQE 8.3 9.3   and materials?                                                                           designation for each part number.
              Have the updated Lead Free BOM's been released in your MRP system to drive               The supplier's MRP system should be driving orders for Lead Free materials for Dell's
SQE 8.4 9.4   requirements for Lead Free products per Dell's schedule?                                 Lead Free products.
                                                                                                       Verify that any components or assemblies that have a leaded and lead free version have
              Do all lead-free components and assemblies have unique part numbers from equivalent a unique part number for each version. If unique part numbers are not assigned to each
N/A     9.5 lead containing components or assemblies?                                                  version, the supplier should not get credit for this question.
        10. Design Guideline
                                                                                                          Has the supplier identified any PCBA design changes that are unique requirements for
             Have you identified any product design guideline changes required by your "Lead Free"        their Optimized Lead Free process? Examples are pad design changes, component
ENG 5.1 10.1 assembly process, test process, or lead free materials?                                      spacing, test pad layout / size, tester probe specification, etc.

               Have these design changes been documented in a "Lead Free" design guide or                 If any changes have been identified in question 10.1, have they been documented in a
ENG 5.2   10.2 specification?                                                                             procedure, specification, design guide, etc.?

                                                                                                          Has the supplier identified any process design changes that are unique requirements for
               Have you identified any assembly process design changes (such as a Solder Paste            their Optimized Lead Free process?
ENG 5.3   10.3 Stencil, support tooling, etc) for your "Lead Free" assembly and test process?
                                                                                                          If any changes have been identified in question 10.3, have they been documented in a
ENG 5.4   10.4 Have these process design changes been documented in a procedure or specification?         procedure, specification, design guide, etc.?
                                                                                                         The supplier should have data or documentation that evaluates the impact of Pb-Free
                                                                                                         solder on ICT test pad performance. Pb-Free solder is harder than Sn-Pb solder which
                                                                                                         may require a stronger pin force for the ICT test probes. Pb-Free flux may also be
                                                                                                         harder than Sn-Pb flux which will require a stronger pin force. The supplier should
               Have you identified and documented your design rule for acceptability of lead free solder document their Design Guide requirements for acceptability of Pb-Free solder paste or
          10.5 on ICT test pads?                                                                         wave solder (and associated flux residues) on ICT test pads.

                                                                                                          Pb-Free PWB's and components will require a higher insertion force for press fit
                                                                                                          components due to the albescence of the lubricating properties of Pb. The higher press
                                                                                                          fit force may have to be offset by adjustments in the pin and hole diameter. These new
               Have you identified and documented the design rules for you lead free press fit            press fit design criteria must be reflected in the suppliers lead free design guide.
          10.6 component assembly process?
          11. PWB

                                                                                                        Dell's Pb-Free PWB surface finish plan of record is Immersion Ag. This surface finish
                                                                                                        provides the best overall performance for boards with multiple reflow cycles, wave solder,
                                                                                                        and rework. However, simpler PCBA's (such as single reflow or single reflow with wave
                                                                                                        solder) may have acceptable results with OSP (Entek). The supplier should have test
                                                                                                        data showing the wetting performance for each surface finish after each step of their
                                                                                                        assembly process to document the optimum surface finish for their assembly process. If
               Have you identified and documented to Dell the optimum lead free surface finish for each the supplier does not have data to justify their choice of surface finish, they should not
               of your lead free assembly process flows (such as single sided SMT, double sided SMT, receive credit for this question.
          11.1 double sided SMT with wave solder, etc.)?
                                                                                                        The supplier must have documented limits on how long PCBA's can be held between
                                                                                                        each thermal excursion (reflow, wave solder, rework) without causing damage or
               Have you identified and documented the hold time rules established for each surface      degradation of the PWB surface. This data must be available for each surface finish
          11.2 finish between each major thermal process step?                                          they will use.
                                                                                                        The supplier must have documented handling and storage procedures for each Pb-Free
               Have you documented and implemented the appropriate physical handling procedures         PWB surface finish they will use. These procedures must be implemented in the
          11.3 for each PWB surface finish?                                                             suppliers Pb-Free production process.
                                                                                                          The supplier must have data documenting their evaluation of the compatibility of the
                                                                                                          solder mask used by their PWB vendors with the suppliers Pb-Free assembly and rework
               Have you evaluated and qualified the PWB solder mask with your lead free assembly          process. This evaluation should include evaluation for solder ball formation, thermal
          11.4 process?                                                                                   damage, discoloration, etc.)

                                                                                                          The supplier should have controls in place to prevent damage to Immersion Silver
                                                                                                          PWB's. Contact with any source of Acid or Sulfur will cause a yellow or black tarnish on
                                                                                                          the PWB finish. Clean gloves should be worn at all times. The PWB's should be kept in
                                                                                                          a sulfur and acid free environment at all times. Any paper that comes in contact with the
                                                                                                          PWB should be acid and sulfur free paper. No labels, stickers, defect markers, ink
               Do you have the necessary handling controls in place to prevent Sulfur and / or acid
                                                                                                          stamps, markers, or rubber bands should come in contact with solderable areas of the
               contamination of Immersion Silver plated PWB's? Reference MacDermid Assembly
                                                                                                          PWB. Refer to the two MacDermid Sterling documents identified in the question for
               Guideline Tech Report No 209/309 and MacDermid Sterling Horizontal Process
                                                                                                          more details.
          11.1 Operating Guide, Rev 20.
          12. General Questions

                                                                                                          The supplier should have a documented procedure for setting up the ICT fixture for Pb-
               Have you qualified your ICT equipment / test probe set up with your lead free assembly     Product. This procedure should include the style of test probe and any ICT set up
N/A       12.1 process?                                                                                   parameters that are determined to be different from Sn-Pb product.
                                                                                                          Any location outside of the manufacturing factory the performs solder repair must be
                                                                                                          qualified for lead free soldering process capability prior to the factory shipping Lead Free
               Have you qualified all of your non-factory repair locations for Lead Free capability and   product to Dell. Each repair location must also be audited and qualified for proper Lead
N/A       12.2 compliance?                                                                                Free segregation and marking controls.
                                                                                                   The supplier should have validated their PWB impedance testing procedure on all Pb-
               Have you qualified and documented your PWB impedance testing process with your lead Free PWB's. Any changes that are required must be documented in a new Pb-Free
          12.3 free PWB's?                                                                         PWB impedance testing procedure.

                                                                                                          Many SnAgCu Pb-Free alloys will form an irregular toe fillet, or no toe fillet at all during
                                                                                                          reflow. This will require significant modification of AOI inspection programs. In some
                                                                                                          cases, AOI may no be a useful tool for solder joining inspection, although it will still be
                                                                                                          useful for verification of presence / absence of components, orientation of components,
                                                                                                          component markings, etc. The supplier must documented any changes that are required
               Have you identified and documented the AOI inspection capability for your lead free        in setting up and programming their AOI machines.
          12.4 assembly process?




                                                                                                                                                                                                         Page 9 of 34
         Dell Confidential                                                                                                                                                                                                                    Document No. COR.40.WWP.SQ.0023 Rev 4.0


 Lead Free Supplier                                                                                                          PCBA Quality Process Audit
 Assessment Ref. #                                                                                                                         Add a 'Y' to the Box if the Process Was Assessed
                                                                                                                                                                                                                              Menu



                      Lead Free Assessment                                                                                                                                                                           Lead Free Instructions


                       #                                                                             Audit Criterion                                                                                     3,2          1        RMA       Actual               Audit Comments
                      1. Definition of Lead Free                                                                                                                                                     Enter 1 or 0. NA may be a valid response for shaded cells.^
ENG 1.1a1.1                Have you received the "General Specification for Allowable Levels of Lead (Pb) in Dell Products" (Dell P/N D4394)?
ENG 1.1b1.2                Do you agree with the definitions?
ENG 1.2 1.3                Have you identified all parts that require exemption to the RoHS requirements with detailed information surrounding why the exemption is required?
ENG 1.3 1.4                Do you have an action plan for every part that is non-RoHS compliant and does not have an exemption?
                      2. Lead Free Sub-Tier Management                                                                                                                                                   3,2          1        RMA       Actual
                           Does your company have a Corporate wide "Lead Free" specification that defines your companies requirements for "Lead Free" raw materials and finished
SQE 1.1 2.1
                           product?
SQE 1.2               2.2 Has a copy of your Corporate "Lead Free" specification been provided to Dell?
SQE 1.3               2.3 Have you established a complete list of your sub-tier suppliers to be used to track compliance with your "Lead Free" requirements?
SQE 1.4               2.4 Have you sent a copy of your "Lead Free" specification and requirements to all of your sub-tier suppliers?
SQE 1.5               2.5 Do you have an updated list of your sub-tier suppliers that acknowledge receipt of your "Lead Free" specification and requirements?
SQE 1.6               2.6 Do you have an updated list that tracks the compliance status of each sub-tier supplier to your "Lead Free" specification and requirements?
                           Do you have an Operating Procedure in place at your receiving or incoming inspection area that documents procedures for verification of compliance with your
SQE 1.7               2.7
                           "Lead Free" specification for incoming materials?
SQE 1.8               2.8 Do you have records that demonstrate your Incoming Materials area is in compliance with the Verification operating procedure?
                           Do you have analytical testing capability, either at your incoming inspection area or at a local 3rd party analytical testing vendor, available to perform testing on a
SQE 1.9               2.9
                           sample basis to verify Lead Free compliance of incoming materials?
N/A                   2.10 Can you define, control and provide traceability thereof for the solder alloy mix being used by your sub-tier suppliers?
                      3. Tin-Silver-Copper (Sn-Ag-Cu) Alloy Process Development                                                                                                                          3,2          1        RMA       Actual
ENG 3.1 3.1                Have you provided Dell a copy of the specifications on your Lead Free solder paste?
                           Have you completed a Design of Experiments (DOE) to evaluate multiple SnAgCu solder paste alloys, surface finishes, and process parameters for your SMT
SQE 2.1 3.2
                           process?
                           Do you have DOE qualification data for your SnAgCu SMT process that meets the requirements of Dell's "Lead Free Qualification Requirements", document
SQE 2.2 3.3
                           D4559?
ENG 3.2 3.4                Have you provided specifications on your Lead Free Wave Solder (Flow Solder) alloy?
ENG 3.3 3.5                Have you provided specifications on your Lead Free Wave Solder (Flow Solder) flux?
                           Have you completed a Design of Experiments (DOE) to evaluate multiple SnAgCu or SnCu solder alloys, surface finishes, and process parameters for your
SQE 2.3 3.6
                           Wave Solder process?
                           Do you have DOE qualification data for your SnAgCu or SnCu Wave Solder process that meets the requirements of Dell's "Lead Free Qualification
SQE 2.4 3.7
                           Requirements", document D4559?
SQE 2.5 3.8
             Do you have documentation from your Wave Solder equipment vendor that verifies that the equipment is compatible with the SnAgCu or SnCu alloy selected?
ENG 3.4 3.9 Have you provided specifications on your Lead Free rework / repair solder alloy?
ENG 3.5 3.10 Have you provided specifications on your Lead Free rework / repair flux?
             Have you completed a Design of Experiments (DOE) to evaluate multiple SnAgCu solder alloys, surface finishes, and process parameters for your rework
SQE 2.6 3.11
             process for each major component form factor (BGA, QFP, 0603, PTH, etc.)?

SQE 2.7 3.12 Do you have DOE qualification data for each SnAgCu component rework process that meets the requirements of Dell's "Lead Free Qualification Requirements",
             document D4559? Rework can be qualified as part of the SMT and Wave Solder process qualification as forced rework locations on the test boards.
             Have you identified all new requirements for your Lead Free rework tool set, for each major component package type? Examples would include a new type of
SQE 2.8 3.13
             rework tool, a different rework tool material of construction, Nitrogen atmosphere requirement, etc.
SQE 2.9 3.14 Have rework risks have been documented for each major component package type (board warpage, component delamination, etc.).
                      4. Optimization of SnAgCu Alloy Process                                                                                                                                            3,2          1        RMA       Actual
                           Has each step of the assembly process (screen print, placement, reflow, fabrication, assembly, test, rework, etc.) been optimized by the use of a DOE or other
SQE 3.1 4.1
                           statistical process tool?
SQE 3.2 4.2                Are the DOE plans and results documented to support your optimized process settings?
SQE 3.3 4.3                Are your optimized process and assembly settings documented in a procedure or specification?
                      5. Lead Free manufacturing risks                                                                                                                                                   3,2          1        RMA       Actual
                           Have you identified and documented the key manufacturing and process risks that must be controlled in your "Lead Free" manufacturing process (i.e. stencil
SQE 4.1 5.1                design, PCBA design changes, temperature profile parameters, use of Nitrogen, inspection criteria, part number control, segregation from non-lead free
                           materials, etc.)?
SQE 4.2 5.2                Do you have risk mitigation control plans identified for each risk?
SQE 4.3 5.3                Are you providing Dell a monthly status on the implementation of each risk mitigation control plan?
                      6. Component MSL Controls                                                                                                                                                          3,2          1        RMA       Actual
                           Higher assembly and rework process temperatures will require components to be controlled at higher MSL levels. Do you have documentation that identifies the
SQE 5.1 6.1
                           MSL levels for all "Lead Free" components and assemblies for your Optimized "Lead Free" assembly process?
SQE 5.2 6.2                Do you have procedures, equipment, storage facilities, etc. in place to implement the appropriate controls for each MSL level, per J-STD 020B?
                           Do you have documentation or audit records to verify that the appropriate MSL controls are being properly implemented and controlled in your "Lead Free"
SQE 5.3 6.3
                           assembly process?
SQE 5.4 5.4                Are MSL controls in place for components rejected from the SMT placement machines?

                                                                                                                                                                                                                                                                         Page 10 of 34
      Dell Confidential                                                                                                                                                                                           Document No. COR.40.WWP.SQ.0023 Rev 4.0

SQE 5.5 5.5       Do you have MSL controls in place for your "Lead Free" rework / repair process?
           7. "Lead Free" pass / fail criteria                                                                                                                                     3,2        1       RMA      Actual
SQE 6.1    7.1    Has the pass / fail criteria for "Lead Free" assemblies been updated?
SQE 6.2    7.2    Have the inspection procedures been updated for the new "Lead Free" pass / fail criteria?
SQE 6.3    7.3    Have the inspection and assembly training documentation been updated for the new "Lead Free" pass / fail criteria?
N/A        7.4    Have all Personnel been trained for Lead-Free solder joint inspection? Requires a copy of training documentation and instruction process?
N/A        7.5    Does your lead free pass / fail criteria include criteria for identifying thermal damage of the PWB and components?
           8. Lead Free Product Segregation Controls                                                                                                                               3,2        1       RMA      Actual
                  Have all operating procedures and documentation been updated to include "Lead Free" product / materials segregation and handling requirements to prevent
SQE 7.1    8.1    mixing "Lead Free" from "Lead Containing" product?
SQE 7.2    8.2    Have all labeling and marking documentation or specifications been updated to include "Lead Free" labeling and marking requirements?
N/A        8.3    Are all lead-free manufacturing, rework and storage areas for raw materials, WIP, and finished goods clearly labeled and isolated from each other?
SQE 7.3    8.4    Do you have audit requirements and results to verify compliance with your "Lead Free" segregation and labeling procedures?
                  Do you have a documented procedure to prevent returned "Lead Free" product (from Dell manufacturing lines or Field returns) from being mixed with "Lead
SQE 7.4 8.5       Containing" product?
SQE 7.5 8.6       Is this procedure automated and not subject to failure caused by operator error?
                  If you use more than one alloy of Lead Free solder for SMT, Wave Solder, or rework, then you must have procedures and controls in place to identify and
SQE 7.6 8.7       segregate products with each alloy. Are these procedures and controls in place?
                  Do you have an identification / marking system in place to validate labeling of leaded and lead-free assemblies prior to shipment? Reference Dell Inbound
N/A        8.8    Packaging Specification P\N 15000.
           9. Lead Free Part Number and BOM Control                                                                                                                                3,2        1       RMA      Actual
SQE 8.1    9.1    Do you have a corporate specification requiring unique part numbers for Lead Free components and materials from your sub-tier suppliers?
SQE 8.2    9.2    Do you have a corporate specification or procedure requiring a new part number for Lead Free assemblies shipped to your customers?
SQE 8.3    9.3    Have all for your internal BOM structures been modified to identify lead free components and materials?
SQE 8.4    9.4    Have the updated Lead Free BOM's been released in your MRP system to drive requirements for Lead Free products per Dell's schedule?
N/A        9.5    Do all lead-free components and assemblies have unique part numbers from equivalent lead containing components or assemblies?
           10. Design Guideline                                                                                                                                                    3,2        1       RMA      Actual
ENG 5.1    10.1   Have you identified any product design guideline changes required by your "Lead Free" assembly process, test process, or lead free materials?
ENG 5.2    10.2   Have these design changes been documented in a "Lead Free" design guide or specification?
ENG 5.3    10.3   Have you identified any assembly process design changes (such as a Solder Paste Stencil, support tooling, etc) for your "Lead Free" assembly and test
ENG 5.4    10.4   Have these process design changes been documented in a procedure or specification?
N/A        10.5   Have you identified and documented your design rule for acceptability of lead free solder on ICT test pads?
N/A        10.6   Have you identified and documented the design rules for you lead free press fit component assembly process?
           11. PWB                                                                                                                                                                 3,2        1       RMA      Actual
                Have you identified and documented to Dell the optimum lead free surface finish for each of your lead free assembly process flows (such as single sided SMT,
N/A        11.1 double sided SMT, double sided SMT with wave solder, etc.)?
N/A        11.2 Have you identified and documented the hold time rules established for each surface finish between each major thermal process step?
N/A        11.3 Have you documented and implemented the appropriate physical handling procedures for each PWB surface finish?
N/A        11.4 Have you evaluated and qualified the PWB solder mask with your lead free assembly process?
                Do you have the necessary handling controls in place to prevent Sulfur and / or acid contamination of Immersion Silver plated PWB's? Reference MacDermid
N/A        11.5 Assembly Guideline Tech Report No 209/309 and MacDermid Sterling Horizontal Process Operating Guide, Rev 20.
           12. General Questions                                                                                                                                                   3,2        1       RMA      Actual
N/A        12.1   Have you qualified your ICT equipment / test probe set up with your lead free assembly process?
N/A        12.2   Have you qualified all of your non-factory repair locations for Lead Free capability and compliance?
N/A        12.3   Have you qualified and documented your PWB impedance testing process with your lead free PWB's?
N/A        12.4   Have you identified and documented the AOI inspection capability for your lead free assembly process?
                                                                                                                                                               Maximum Score       70        70        70        70
                                                                                                                                                                Score Obtained     0          0        0         0
                                                                                                                                                              Score Percentage
                                                                                                                                                               Pass Percentage    80%       80%       80%       80%
                                                                                                                                                                                   Not       Not       Not       Not
                                                                                                                                                                      Outcome
                                                                                                                                                                                 Audited   Audited   Audited   Audited
                  ^ See Instructions for details on when NA may be an appropriate entry.




                                                                                                                                                                                                                                             Page 11 of 34
      Dell Confidential                                                                                                                                                                Document No. COR.40.WWP.SQ.0023 Rev 4.0


                                                                                                   PCBA Quality Process Audit                                                                                         Menu
                                                                                                                  Add a 'Y' to the Box if the Process Was Assessed
Paste Printing
 #                                                                              Audit Criterion                                                                          1, 2       3, 4        5, 6       7, 8      9, 10     Actual
1. Work Instructions                                                                                                                                                 Enter 1 or 0. NA may be a valid response for shaded cells.^
        Is there a revision controlled Operator Work Instruction which contains unique details for the specific product being built? (Score 0 if any
1.1
        unsigned/undated handwritten instructions or any handwritten instructions more than 48 hrs old)
1.2     Are Work Instructions readily available to the operator and are they followed at Paste Print?
1.3     Is the Solder Paste specified in the Paste Printing program or on Work Instructions?
1.4     Is the Solder Paste manufacturer, number, & mesh defined in the Paste Print Program or on Work Instructions?
1.5     Is the Stencil's identification specified in the Paste Printing program or on Work Instructions?
1.6     Is the Stencil's identification traceable to a specific PWB part number, revision level and board side?
1.7     Is the Stencil loading orientation specified on the Stencil or on Work Instructions?
1.8     Is the Squeegee in use specified in the Paste Print program or Work Instructions?
1.9     Is the number, location, type and height of the Support Blocks/Pins specified on Work Instructions?
1.10    Are all hand tools needed by the operator listed with their descriptions on Work Instructions?
1.11    Has the use of metal tools for the application and/or removal of paste been specifically disallowed?
1.12    Is the PWB part number and Revision specified on the Work Instruction or line set-up instructions?
1.13    Is the PWB orientation to the Stencil identified in the Work Instructions or line set-up instructions?
1.14    Is the machine Program Name specified on the Work Instruction or line set-up instructions?
2. Solder Paste                                                                                                                                                          1, 2       3, 4        5, 6       7, 8      9, 10     Actual
2.1     Is there a Standard Operating Procedure for the cold storage of solder paste?
2.2     Is the cold storage temperature within the manufacturers' recommended range for all solder paste in cold storage?
2.3     Is the Solder Paste FIFO controlled while in cold storage? A gravity feed rack is preferred.
2.4     Does the cold storage unit have a temperature recorder, which can be read without opening the unit, to record temperature over time?
2.5     Is there a documented requirement to periodically check that the recorded temperature is within the required storage limits?
2.6     Is there evidence to demonstrate that action was taken when the temperature was outside the defined storage limits?
2.7     Is the cold storage expiration date of the Solder Paste specified on the Solder Paste container?
2.8     Is the date and time that the Solder Paste has been removed from cold storage specified on its container?
2.9     Is the date and time that the Solder Paste is available for use, after removal from cold storage, specified on its container?
2.10    Is the date and time that the Solder Paste expires at ambient temperature with its 'seal broken' documented and known?
2.11    Is the date and time that the Solder Paste expires at ambient temperature with its 'seal in place' documented and known?
2.12    Is there evidence to demonstrate that this information has been correctly completed and that this process is fully understood by users?
2.13    Are Screen Print Operators required to wear gloves when handling Solder Paste?
2.14    Is there a specification readily available for the Solder Paste?
2.15    Is the mesh for the Solder Paste used suitable for the pitch technology on the board being built?
2.16    Is the maximum time that the Solder Paste is allowed to remain on a board prior to reflow documented, known, & followed?
2.17    Is the Solder Paste lot code recorded and fully and easily traceable to the individual product serial number product?
3. Stencil                                                                                                                                                               1, 2       3, 4        5, 6       7, 8      9, 10     Actual
3.1     Are all Stencils adequately stored in a manner to avoid potential damage and to keep out foreign or airborne materials?
3.2     Are all Stencils identified with process proof labels or plates which are visible when the stencil is in its rack or mounted in the Printer?
3.3     Is the Stencil cleaned in a automatic stencil cleaner at the end of a production run or after a fixed time has elapsed?
3.4     Is there a documented requirement to inspect a Stencil for damage once cleaned?
3.5     Is the evidence of cleaning and inspection documented?
3.6     Is there a documented Stencil Cleaning process which identifies the chemicals, wash times, dry times, & consumables to be used?
3.7     Is there a documented Stencil Cleaner maintenance procedure which defines frequency for checking filters and solution levels?
3.8     Is there evidence to demonstrate that the Stencil Cleaner's Maintenance procedure and records are adequate and up-to-date?
3.9     Is there a documented requirement to periodically check the Stencil tension and is there evidence that this is done?
3.10    Is there a document which specifies Stencil ordering requirements with respect to size, thickness, ratio, orientation, identification, etc.?
3.11    Is there a document which specifies the conditions for when Laser vs. Chemical Etched vs. Electroformed Nickel, should be used?
3.12    Is there evidence to demonstrate that the Stencil ordering requirements are followed?
3.13    Is there a documented Stencil First Article procedure which checks, tension, thickness, aperture sizes and design, first print, etc.?
3.14    Is there evidence to demonstrate that the Stencil First Article procedure and records are adequate and up-to-date?
4. Squeegee                                                                                                                                                              1, 2       3, 4        5, 6       7, 8      9, 10     Actual
4.1     Are the Squeegees length, angle, style/durometer, defined to ensure correct Squeegee selection?
4.2     Is there evidence to demonstrate that the Squeegee used is correct and is fully and easily traceable to the product and stencil?

                                                                                                                                                                                                                       Page 12 of 34
      Dell Confidential                                                                                                                                                            Document No. COR.40.WWP.SQ.0023 Rev 4.0
4.3     Are all Squeegees adequately stored in a manner to avoid potential damage?
4.4     Is there evidence that Squeegees inspected for damage prior to use and prior to storage?
4.5     Is there a requirement to ensure the Squeegee is leveled either automatically or manually documented, prior to use?
5. Vacuum Blocks and Tooling                                                                                                                                        1, 2      3, 4        5, 6      7, 8     9, 10    Actual
5.1     Is there a documented requirement to indicate that Blocks, Support Pins or Vacuum Blocks are needed for specific products?
5.2     Are all Vacuum Blocks identified with a name or tooling number that is fully and easily traceable to the product and board side?
5.3     Are all Vacuum Blocks clean and adequately stored in a manner to avoid potential damage?
6. PCB                                                                                                                                                              1, 2      3, 4        5, 6      7, 8     9, 10    Actual
6.1     Are there satisfactory methods in place to control PCB handling and exposure?
6.2     Does the PWB part number and Revision cross-reference to the PCBA part number and Revision?
6.3     Is a unique tracking label or PPID label placed on the PWB for tracking purposes at Paste Print? Score NA if Dell Assy Dwg does not require.
6.4     Does the unique tracking label or PPID label date code specify the date the PWB was paste printed?
6.5     Are misprinted PWBs cleaned in an automatic board cleaner using appropriate fixturing?
6.6     Is there a documented Board Cleaning process which identifies the chemicals, wash times, dry times, & consumables to be used?
7. Machine Capability                                                                                                                                               1, 2      3, 4        5, 6      7, 8     9, 10    Actual
7.1     Is the Paste Printing technology suitable for the product being built?
7.2     Is the Paste Printing operation automated with fiducial camera alignment?
7.3     Is contact printing with stainless steel stencils and squeegees being used?
7.4     Does the Printing machine have the capability to automatically wet and dry wipe the Stencil?
7.5     Does the Printing machine use the automatic wet and dry wipe capability?
7.6     Does the Printing machine have Vacuum Stencil clean capability?
7.7     Does the Printing machine use Vacuum Stencil clean?
7.8     Is there a documented minimum frequency for stencil clean specified based on the technology used on the board?
7.9     Are stencil wet and/or dry automatic clean rates specified for each product and shown in the program?
7.10    Are all materials used to wipe the stencil specified as low lint or preferably lint free?
7.11    Are changes to clean rates approved based only upon performance feedback?
7.12    Does the Printing machine have the capability to automatically dispense Solder Paste?
7.13    Does the Printing machine use automatic Solder Paste dispense?
7.14    Does the Printing machine flag when the Solder Paste container is near empty?
7.15    Are all Printers enclosed in order to keep out foreign or airborne materials?
7.16    Are localized climate control units installed and in use on all Paste Printers?
7.17    Is the Printing machine programmable? If not score 0 for next 4 questions.
7.18    Is the machine Program Name revision controlled to show traceability of program changes?
7.19    Is the machine Program Name traceable to the PCB and PCBA part number?
7.20    Is access to the machine program password protected with restricted access?
7.21    Do program changes to critical parameters during machine control remain unsaved unless approved by a technician/engineer?
8. Solder Paste                                                                                                                                                     1, 2      3, 4        5, 6      7, 8     9, 10    Actual
8.1     Is automatic 2D or 3D solder paste inspection deployed and effective? Review ICT or AOI/AXI results to determine effectiveness.
8.2     Can it be demonstrated that the machine calls are reviewed by the operator to determine if real or false?
8.3     Is the 2D or 3D coverage % calculated based on the total # of pads with 2D or 3D vs the total # of apertures on the stencil?
8.4     Does the exit conveyor from the API Equipment, stop to allow for verification of defects so that defective boards may be captured?
8.5     Are rejected boards automatically stopped on this conveyer for operator false call validation?
8.6     Are changes to 2D or 3D coverage made based only on performance feedback? Is this reflected in the Program Revision?
8.7     Is there a document which defines the effect of changing critical Paste Printing parameters on the quality of the output?
9. PCBA                                                                                                                                                             1, 2      3, 4        5, 6      7, 8     9, 10    Actual
9.1     Are outputted boards at least sample inspected for print quality to ensure process control?
9.2     Is there a documented frequency for checking print quality?
9.3     Is there evidence to demonstrate that this print quality inspection is conducted?
9.4     Is there a specification that defines acceptability of paste printing, available and used at the Paste Printer?
                                                                                                                                             Maximum Score          91        91          91        91        91        91
                                                                                                                                             Score Obtained         0         0           0          0         0         0
                                                                                                                                           Score Percentage
                                                                                                                                            Pass Percentage        80%       80%         80%       80%       80%       80%
                                                                                                                                                                    Not       Not         Not       Not       Not       Not
                                                                                                                                                  Outcome
                                                                                                                                                                  Audited   Audited     Audited   Audited   Audited   Audited
        ^ See Instructions for details on when NA may be an appropriate entry.                                                                                0




                                                                                                                                                                                                               Page 13 of 34
Dell Confidential                                                                                                                                                                Document No. COR.40.WWP.SQ.0023 Rev 4.0


                                                                                       PCBA Quality Process Audit                                                                                        Menu
                                                                                                    Add a 'Y' to the Box if the Process Was Assessed
Component Placement
 #                                                                     Audit Criterion                                                                        1, 2        3, 4       5, 6       7, 8      9, 10     Actual
1. Work Instructions                                                                                                                                       Enter 1 or 0. NA may be a valid response for shaded cells.^
       Is there a revision controlled Operator Work Instruction which contains loading information for the specific product being built? (Score 0 if any
1.1
       unsigned/undated handwritten instructions or any handwritten instructions more than 48 hrs old)
1.2    Are Work Instructions readily available to the operator and are they followed at Component Placement?
1.3    Are component part numbers and descriptions included on the Work Instructions?
1.4    Are component descriptions sufficiently detailed to check at first-article that the correct components are being used?
1.5    Is the machine head/slot number for component loading specified for each part number on Work Instructions?
1.6    Are the reference designators and the quantity per part number specified on Work Instructions?
1.7    Is the component feeder type/size specified on Work Instructions or otherwise for each component package type?
1.8    Is the machine Program Name specified on the Work Instruction or line set-up instructions?
2. Component Loading and Verification                                                                                                                         1, 2        3, 4       5, 6       7, 8      9, 10     Actual
2.1    Is there an automated bar coded component loading verification aid in order to reduce the probability of incorrect loading? Note*
2.2    Are the component loading verification aids hard linked to the placement program so that loading is verified against program data?
2.3    Can traceability of component lot codes be demonstrated for critical devices?
2.4    Is component loading/changes verified and cross checked by an individual other than the set-up operator at product changeover? Note*
2.5    Is a component loading/changes verification log signed by the set-up operator and countersigned by the cross checker before start up? Note*
2.6    Is the correct feeder loading base used to facilitate real to feeder loading?
2.7    Are first-built boards verified against documentation for missing/misplaced components and for correct component polarity?
2.8    Are first-articles conducted using AOI methods and complemented with description verification and value metering?
2.9    Are all Resistors & Capacitors measured for a value within the tolerance (one per part number) at first-article & at reel change?
2.10   Is a first-article log signed to verify acceptance before start up?
2.11   Is the orientation of Tantalum SMT capacitors, Diodes, etc in tape format, standardized and documented for polarity orientation?
2.12   Is the IC tray loading polarity standardized for each type of polarity indicator that can be used for each component?
2.13   Is loading polarity referenced both from the tray and the component so as to ensure retrayed components are correctly loaded?
3. Nozzles, Feeders, and Tooling                                                                                                                              1, 2        3, 4       5, 6       7, 8      9, 10     Actual
3.1    Is there a document which details the standardized nozzle diameter set-up selected for each type of placement equipment?
3.2    Are these standardized nozzle diameter set-up documents readily available for when nozzles need to be replaced or changed?
3.3    Is there a document which details the range of component XYZ body sizes that each selected nozzle type can successfully place?
3.4    Is there a documented requirement to conduct daily nozzle centering and is there evidence that this is done?
3.5    Is each feeder identified with its own unique serial number?
3.6    Is there a documented and effective Feeder Maintenance Program? Records (s/w or otherwise) must be by Feeder Serial Number.
3.7    Are database records maintained for each feeder serial number for the purpose of tracking its maintenance history and performance?
3.8    Is feeder maintenance history used to monitor feeder life so that problematic feeders can be removed from the process?
3.9    Can it be demonstrated that the number of feeder indexes is counted & monitored for each unique feeder using software or otherwise?
3.10   Is this information used to flag that feeder preventative maintenance is required after x number of indexes?
3.11   Is there a documented requirement to indicate that Blocks or Support Pins are needed for specific products?
3.12   Is the No, location, type and height of Support Blocks/Pins identified on a product by product basis? Score NA if in 3.11 there are not needed.
3.13   Are the Support Pin locations identified for each product using templates/tooling or some other effective solution? Comment as above.
4. Moisture Sensitive Devices                                                                                                                                 1, 2        3, 4       5, 6       7, 8      9, 10     Actual
4.1    Are components stored before loading and after unloading in a manner which prevents damage?
4.2    Are the Moisture Sensitive Devices (MSDs) and their sensitivity level readily known to the operator?
4.3    Are MSDs time stamped at opening and their exposure time monitored against pre determined limits?
4.4    Is there a flag to indicate that the exposure time has been exceed for any given device in a dry box?
4.5    Is there a flag to indicate the MSD exposure has expired for any MSD device currently loaded in the placement machines?
4.6    Have MSD procedures been updated to reflect the JEDEC standard for MSD control? (J-STD-033A MSD released in July 2002)
4.7    Is there evidence of correct implementation of J-STD-0033A for all MSD devices?
4.8    Are there MSD procedures in place to ensure MSD shelf life is reduced based on measured Relative Humidity conditions?
4.9    Is there a method in place to address the time spent in dry storage and its effect on remaining life based on MS Level and RH Level?
4.10   Is it clearly understood that MSD 'shelf life' continues to degrade during dry cabinet storage of some MSD devices?
4.11   If MSDs are on both sides of a PCBA, is there an effective method to account for time between 1st and 2nd reflow?
4.12   Can MSD control be demonstrated for MSD devices that need internal/external pre-programming?
4.13   Can MSD control be demonstrated for rejected devices and devices used for rework?
4.14   Have MSD recovery methods been defined and adequate for all component types?
4.15   Does the control of Moisture Sensitive Components include those components on reels?

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Dell Confidential                                                                                                                                                               Document No. COR.40.WWP.SQ.0023 Rev 4.0
4.16 Is the baking or hot room storage time and temperature documented and controlled for component recovery?
4.17 Has this time and temp been determined based on the component supplier's guidelines / J-STD-0033A?
4.18 Is there evidence to demonstrate that the control process for MSDs is in use and is effective?
5. Machine Capability                                                                                                                                         1, 2      3, 4       5, 6      7, 8     9, 10      Actual
5.1    Are Component Placement Programs generated from CAD XY coordinate data?
5.2    Is there a standardized nomenclature for Shape Code definition?
5.3    Can this nomenclature be used to determine the most appropriate shape code to allocate to a given part of given dimensions?
5.4    Are localized fiducials used for fine pitch devices when localized component fiducials exist on the board?
5.5    Has manual component moving been eliminated given correct CAD, nozzle set-up, Shape Code allocation, local fiducials, Cam speed, etc?
5.6    Does the Fine Pitch placement machine have the capability to check lead Coplanarity in xyz?
5.7    Does the Fine Pitch placement machine use its coplanarity capability on all leads of 20 mil pitch or less, and all programmed parts?
5.8    Does the Fine Pitch placement machine have the capability to check ball arrays? If no such device, score NA.
5.9    Does the Fine Pitch placement machine use its ball array verification capability for all BGA devices? If no such device, score NA.
5.10   Is the machine Program Name revision controlled to show traceability of program changes?
5.11   Is the machine Program Name traceable to the PWB and PCBA part number?
6. PCBA                                                                                                                                                       1, 2      3, 4       5, 6      7, 8     9, 10      Actual
6.1    Are outputted boards at least sample inspected pre reflow for placement positional accuracy for machine control purposes?
6.2    Is the frequency for this verification defined and documented, and is there evidence to suggest it is followed?
6.3    Is there a visual aid available which identifies the populated locations with polarity, and also the no-pop locations?
6.4    Is there a placement standard pre reflow to validate placement accuracy for the shape code, nozzle allocation, etc. parameters used?
6.5    Is there evidence to demonstrate that action is taken to adjust the machines performance for when this standard is exceeded?
7. Attrition Rates and Rejected Components                                                                                                                    1, 2      3, 4       5, 6      7, 8     9, 10      Actual
7.1    Is attrition rate monitoring conducted systematically to ensure feeder and/or nozzle problems are captured at least hourly?
7.2    Is there documented evidence to ensure attrition rates are checked and actioned at least hourly to ensure process control?
7.3    Is there a specification defined for acceptable attrition rates for the individual feeders?
7.4    Is there a specification defined for the maximum allowable number of nozzle skips per machine before it is shut down for repair?
7.5    Are these specifications determined based on a percentage combined with the number of placements for a given time period?
7.6    Is there evidence to demonstrate that attrition rate monitoring is conducted, effective, and used to make process control decisions?
7.7    Is there a documented process for the disposition or reuse of machine rejected components? Rs and Cs must not be reused even for rework.
7.8    Are rejected components reviewed and repaired to ensure conformance before reuse, even if only used for rework?
7.9    Are there repair blocks available or a lead conditioner in use for repairing 'real' Coplanarity rejects? Score 0 if parts not repaired.
7.10   Does the re-traying process always ensure that component polarity wrt the tray and the component loading polarity is preserved?
7.11   Is there a documented Process Deviation procedure to manage machine skips for hand placement if hand placement is allowed?
8. Process Capability                                                                                                                                         1, 2      3, 4       5, 6      7, 8     9, 10      Actual
8.1 Has a Process Capability Analyses (PCA) been conducted and the Cpk acceptable for the suite of shape codes in use?
8.2 Were shape code allocations, component nozzle allocations, cam speeds, etc. recorded for this PCA?
8.3 Are the recorded shape code allocations, component nozzle allocations, and cam speeds, the same as those used today?
                                                                                                                                   Maximum Score              82        82         82        82        82          82
                                                                                                                                    Score Obtained             0         0          0         0         0           0
                                                                                                                                  Score Percentage                                                                 0%
                                                                                                                                   Pass Percentage           80%       80%        80%       80%       80%         80%
                                                                                                                                                              Not       Not        Not       Not       Not         Not
                                                                                                                                              Outcome
                                                                                                                                                            Audited   Audited    Audited   Audited   Audited     Audited
       ^ See Instructions for details on when NA may be an appropriate entry.                                                                           0
       Note*: If 2.1 scores 1, then 2.4 and 2.5 may score NA




                                                                                                                                                                                                               Page 15 of 34
Dell Confidential                                                                                                                                                                         Document No. COR.40.WWP.SQ.0023 Rev 4.0


                                                                                                  PCBA Quality Process Audit                                                                                       Menu
                                                                                                                 Add a 'Y' to the Box if the Process Was Assessed
Reflow Soldering
 #                                                                              Audit Criterion                                                                        1, 2       3, 4       5, 6       7, 8      9, 10     Actual
1. Work Instructions                                                                                                                                                Enter 1 or 0. NA may be a valid response for shaded cells.^
       Is there a revision controlled Operator Work Instruction which contains set-up information for the specific product being reflowed? (Score 0 if
1.1
       any unsigned/undated handwritten instructions or any handwritten instructions more than 48 hrs old)
1.2    Are Work Instructions readily available to the operator and are they followed at Reflow?
1.3    Is the conveyor speed set point specified on the Work Instruction and is it the same as that specified in the program?
1.4    Are the temperature set points specified on the Work Instruction and are they the same as those specified in the program?
1.5    Do Work instructions indicate if pallets or other tooling are required?
1.6    When center rail support is required, do Work instructions indicate this requirement and is the location specified?
1.7    Is the machine Program Name specified on the Work Instruction or set-up sheets?
2. Machine Capability                                                                                                                                                  1, 2       3, 4       5, 6       7, 8      9, 10     Actual
2.1    Is the Reflow technology in use suitable for the product being built? Must be full forced Convection with sufficient zone count.
2.2    Are air flow controllers or a centralized control system used to balance exhaust flow rates for each individual exhaust drop?
2.3    Are exhaust flow rate ranges specified and monitored on a regular basis to insure compliance?
2.4    Is the machine Program Name revision controlled to show traceability of program changes?
2.5    Is the machine Program Name traceable to the PWB and PCBA part number?
2.6    Is access to the machine program password protected with restricted access?
2.7    Do program changes to critical parameters during machine control remain unsaved unless approved by a technician/engineer?
3. Temperature Profile                                                                                                                                                 1, 2       3, 4       5, 6       7, 8      9, 10     Actual
3.1    Is there available a Temperature Profile for the product currently being built?
3.2    Is the Temperature Profile assessable and readily available to operators / technicians as and when required?
3.3    Were the Temperature Set Points and Conveyor Speed logged for that Thermal Profile when it was conducted?
3.4    Do the Temperature Set Points & Conveyor Speed written on the Thermal Profile correspond to the current Program settings?
3.5    Is there available an Engineering based specification to detail the acceptable process window for Temperature Profiles?
3.6    Was the Engineering based spec. derived from the Paste & Component manufacturer's recommendations but controlled to a narrower window?
3.7    Does the product Temperature Profile fall within the Engineering based specification for the process window?
3.8    Does the product Temperature Profile fall within the Engineering based specification for glass transition temperature requirements?
3.9    Can any excursions outside of the process window be justified and supported with hard evidence and logical analysis?
3.10   Does the product Temperature Profile meet the reflow requirements for the SMT components according to the component manufactures?
3.11   Are the boards used to establish the initial Thermal Profile kept as engineering samples?
3.12   Is there evidence that a once off comparison study been conducted for a loaded versus an unloaded oven?
3.13   Have at least five thermocouples been used at various points on the board to establish the Thermal Profile? Note*
3.14   Is there a documented and systematic approach used to identify the most appropriate locations to attach the thermocouples?
3.15   Can it be demonstrated that a BOM review was conducted to verify that the chosen profile is appropriate for all specific component conditions?
3.16   Is there evidence that each thermocouple ball was bonded to a board joint using Hi Temp. Solder or Conductive Epoxy?
3.17   Is there the capability to detect a temperature zone failure and to trigger an alarm automatically if this occurs?
3.18Has a Calibration Profile been established in order to detect machine long term performance degradation?
3.19Is there a documented frequency for running a Calibration Profile and was it established based upon historical performance data?
3.20Is there evidence to demonstrate that Calibration Profiles are conducted and that records are up-to-date?
3.21Is the practice of comparing the current Calibration Profile to the Standardized Calibration Profile used to identify changes?
3.22Is the current Calibration Overlay/Profile used to determine if a variation in the ovens thermal characteristics has occurred?
3.23Is the current Calibration Overlay/Profile used to determine if a variation in conveyor speed has occurred?
3.24Is there evidence to demonstrate that action was taken when the Calibration Profile was different to the Standard?
3.25Is a standardized tool, like an OvenRider, used with a standardized profile to conduct a Calibration Profile?
4. Manual Inspection (NA allowed, for questions in this section if AOI is deployed)                                                                                    1, 2       3, 4       5, 6       7, 8      9, 10     Actual
4.1 Are outputted boards at least sample inspected pre reflow for placement, missing components, and solder defects?
4.2 Are Workmanship Standards defined for placement and soldering, and are they accessible and used to determine board acceptability?
4.3 Are Inspection Templates available and used to identify missing & unpopulated components and component polarity post reflow?
4.4 Are Inspection Templates or Visual Aids used to identify ICT not tested components post reflow?
4.5 Are Templates readily accessible for verification purposes?
4.6 Are Inspection Templates revision controlled and traceable to the current product ECO level?
4.7 Is there a point and click software tool post reflow which is linked to CAD or program data to facilitate component identification for rework?
4.8 Is there a documented requirement to conduct at least sampling X-ray inspection for BGA devices, and is there evidence that it is practiced?



                                                                                                                                                                                                                          Page 16 of 34
Dell Confidential                                                                                                                                                                 Document No. COR.40.WWP.SQ.0023 Rev 4.0

5. Automatic Inspection (NA allowed, for the cells indicated)                                                                                                   1, 2      3, 4      5, 6      7, 8     9, 10     Actual
5.1    Are AOI/AXI complementary methods, which include solder joint inspection, used for all reflowed parts?
5.2    Is the AOI coverage % calculated based on the board OFE for a given side vs the total # of joints/components inspected?
5.3    Are the components/joints not covered by AOI documented and known and targeted for visual inspection?
5.4    Is there evidence that the AOI coverage is verified periodically by using ICT and manual inspection feedback data?
5.5    Can it be demonstrated that the machine calls are reviewed by the operator to determine if real or false?
5.6    Can it be demonstrated that the operator been fully trained and certified to interpolate the AOI images presented?
5.7    Does the ICT pareto of defects suggest that AOI is being 100% deployed and is being effective?
5.8    Can it be demonstrated that AOI detectable ICT failures are feed back to AOI to improve program and operator effectiveness?
5.9    Are rejected boards automatically stopped on the line post operator false call validation?
5.10   Are changes to AOI coverage made based only on performance feedback?
6. Process Control                                                                                                                                              1, 2      3, 4      5, 6      7, 8     9, 10     Actual
6.1    Is there evidence that the SPC used to monitor output post reflow, is effective at identifying & correcting process performance issues?
6.2    Is the processes DPMO and the products DPU monitored in real time? ('real-time'=now)
6.3    Is OFE data readily available and calculated in accordance to the Dell documented procedures? (Doc. No. COR.40.WWP.SQ.0209)
6.4    Is AOI data used to calculate SMT's DPMO? Score 0 if AOI deployed and not done.
6.5    Are ICT debug results used to re-calculate SMT DPMO as a true measure of SMT DPMO?
6.6    Is the data collected meaningful and can it be demonstrated that it is used to make process control decisions?
                                                                                                                                        Maximum Score           63        63         63       63        63         63
                                                                                                                                         Score Obtained          0         0          0        0         0          0
                                                                                                                                      Score Percentage                                                             0%
                                                                                                                                       Pass Percentage         80%       80%       80%       80%       80%        80%
                                                                                                                                                                Not       Not       Not       Not       Not        Not
                                                                                                                                             Outcome
                                                                                                                                                              Audited   Audited   Audited   Audited   Audited    Audited
       ^ See Instructions for details on when NA may be an appropriate entry.                                                                             0
       Note*: Thermocouples must be placed on top and bottom side of board for double sided boards.




                                                                                                                                                                                                                Page 17 of 34
       Dell Confidential                                                                                                                                                Document No. COR.40.WWP.SQ.0023 Rev 4.0


                                                                                        PCBA Quality Process Audit                                                                                      Menu
                                                                                                      Add a 'Y' to the Box if the Process Was Assessed
Manual Assembly
 #                                                                       Audit Criterion                                                                      1, 2     3, 4        5, 6       7, 8      9, 10    Actual
1. Work Instructions                                                                                                                                     Enter 1 or 0. NA may be a valid response for shaded cells.^
       Are revision controlled Work Instructions displayed for the operator at each assembly station? (Score 0 if any unsigned/undated
1.1
       handwritten instructions or any handwritten instructions more than 48 hrs old)
1.2    Are component part numbers and their descriptions specified on Work Instructions?
1.3    Are component descriptions sufficiently detailed to ensure the correct component is being used?
1.4    Are the reference designators and the quantity per part number specified on Work Instructions?
1.5    Is component polarity or its non-existence consistently and unambiguously specified on Work Instructions?
1.6    Are the components on the Work Instructions listed by the most appropriate order of insertion?
1.7    Is the layout of lin bins/trays defined on Work Instructions for each assembly station?
1.8    Are all lin bins/trays located in the correct position as per Work Instructions for each assembly station?
1.9    Do Work instructions indicate if solder pallets/carriers or breakers must be used?
1.10   Do Work instructions indicate if a top hat, separators, plugs, Kapton tape, finger protection, etc. must be used?
1.11   Does the direction of build for the board align with the orientation of the board on the Work Instructions and Wave direction?
1.12   Do Work Instructions not only indicate what components need to be inserted but also the buddy check components?
1.13   Is the conveyor at entry to the wave, slower than the wave conveyor speed, and documented on Work Instructions?
1.14 Is there a documented process for the identification and control of non-completed boards resulting from breaks, shift changes, etc.
1.15 Is the PWB part number and Revision specified on the Work Instruction or line set-up instructions?
1.16 Does the PWB part number and Revision cross-reference to the PCBA part number and Revision?
2. Station Breakout                                                                                                                                           1, 2     3, 4        5, 6       7, 8      9, 10    Actual
2.1    Is there a document available which describes the guidelines for station breakout at Manual Assembly?
2.2    Has the number of assembly stations required been determined scientifically in order to maximize throughput within constraints?
2.3    Is there evidence that the line is evenly balanced with the defined number of stations and the defined station breakout?
2.4    Is there evidence to demonstrate that the assembly operators follow the defined station breakout on the Work instructions?
2.5    Is there evidence that sufficient time is allocated for component insertion at each station, as determined by the beat rate of the line?
2.6    Does following the breakout ensure that the insertion of subsequent components is not restrictive or increased in difficulty?
2.7    Does following the breakout ensure that 'snap-in' type components are inserted first or off-line?
2.8    Does following the breakout ensure that components that 'look' alike are assembled at different and non-adjacent stations where possible?
2.9    Does following the breakout ensure that components that 'fit' alike are assembled at different and non-adjacent stations, where possible?
3. Line Set-Up and Verification                                                                                                                               1, 2     3, 4        5, 6       7, 8      9, 10    Actual
3.1    Are all Manual Assembly station set-ups verified according to Work Instructions and a log signed prior to start-up & re-start?
3.2    Are first-built boards verified against documentation for missing components, value, and for correct polarity pre Wave?
3.3    Are the components supplied to Manual Assembly appropriately prepped with correct lead length, forming and pitch, etc.?
3.4    Is it evident that lead snipping has been minimized through adequate component prep and/or pallet support design?
3.5    Are all totes or tray locations identified with printed part numbers, descriptions, circuit designators, station number, and/or layout information?
3.6    Are boards conveyed along the line automatically without the need to manually push the board forward or pull the board back?
4. Tooling                                                                                                                                                    1, 2     3, 4        5, 6       7, 8      9, 10    Actual
4.1    Is tooling used to provide underside support on all sides, to minimize flexing, for the insertion of components that require a force or snap-in fit?
4.2    Is tooling used and is it adequate to prevent board flexing during all component insertion?
4.3    Is tooling used for snap-in components prone to bent pins, to verify the pin straightness prior to their insertion?
4.4    Is there a document available which describes the guidelines for pallet/carrier design?
4.5    Are footprint, co-planarity, depth below datum, ID, clamping mechanisms, chamfering, direction of flow, criteria addressed?
4.6    Are pallets/carriers identified by a name or tooling number which is traceable to the PCBA part number and revision?
4.7    Is pallet/carrier orientation to the line specified or indicated and correct?
4.8    Are pallets/carriers designed such a way that they support all non-snap-in components without the use of weights?
4.9    Are pallets/carriers appropriately milled out to avoid shadowing and insufficients?
4.10   Do selective wavesolder pallets/carriers use built in solder thieves to help reduce the occurrence of solder bridging?
4.11   Is there a documented requirement to clean pallets/carriers and to regularly inspect them for damage and is there evidence of this?
4.12   Are pallets/carriers in a good state of repair, clean, and satisfactorily stored to prevent damage?
5. Manual Inspection                                                                                                                                          1, 2     3, 4        5, 6       7, 8      9, 10    Actual
5.1    Are outputted boards 100% inspected pre wave (Top Side) for missing components, value and polarity?


                                                                                                                                                                                                       Page 18 of 34
       Dell Confidential                                                                                                                                              Document No. COR.40.WWP.SQ.0023 Rev 4.0
5.2    Is there evidence to demonstrate that this quality inspection is conducted?
5.3    Is there a visual aid (hard copy or otherwise) which identifies the populated locations with polarity, and also the no-pop locations?
5.4    Is there a buddy check system used between stations to ensure the previous operation has been fully completed?
5.5    Is there evidence to demonstrate that a buddy check system is deployed between assembly stations?
5.6    Is the touch method used as part of the buddy system?
5.7    Are manually inserted components that are not tested by ICT specifically targeted for inspection in addition to the buddy check?
5.8    Is there evidence to demonstrate that at least an hourly defect feedback process to Manual Assembly is in operation and effective?
5.9    Is accountability for Manual Assembly defects traceable to a specific workstation and operator/supervisor?
5.10   Are snap-in connectors inspected for bent pins post-insertion? (Tooling or an alternate method with proven effectiveness must be used).
                                                                                                                                    Maximum Score           53        53        53        53        53        53
                                                                                                                                     Score Obtained         0         0          0        0         0          0
                                                                                                                                   Score Percentage                                                           0%
                                                                                                                                    Pass Percentage        80%       80%       80%       80%       80%       80%
                                                                                                                                                            Not       Not       Not       Not       Not       Not
                                                                                                                                         Outcome
                                                                                                                                                          Audited   Audited   Audited   Audited   Audited   Audited
       ^ See Instructions for details on when NA may be an appropriate entry.                                                                         0




                                                                                                                                                                                                   Page 19 of 34
Dell Confidential                                                                                                                                                                 Document No. COR.40.WWP.SQ.0023 Rev 4.0


                                                                                       PCBA Quality Process Audit                                                                                           Menu
                                                                                                     Add a 'Y' to the Box if the Process Was Assessed
Wave Soldering
 #                                                                     Audit Criterion                                                                          1, 2       3, 4       5, 6        7, 8      9, 10       Actual
1. Work Instructions                                                                                                                                        Enter 1 or 0. NA may be a valid response for shaded cells.^
       Is there a revision controlled Operator Work Instruction which contains set-up information for the specific product being processed? (Score 0 if
1.1
       any unsigned/undated handwritten instructions or any handwritten instructions more than 48 hrs old)
1.2    Are Work Instructions readily available to the operator and are they followed at Wave?
1.3    Do Set-Up Sheets specify the Solder, the Flux, and the thinners (as applicable) to be used?
1.4    Do Set-Up Sheets specify the Spray Flux parameter settings such as delay, duration, traverse speed, pressure, etc?
1.5    Do Set-Up Sheets specify the Pre-Heater set points and the Solder Pot Temperature and are they the same as those on the machine?
1.6    Do Set-Up Sheets specify the Conveyor Speed and is it the same as that in the program?
1.7    Do Set-Up Sheets specify the Lead Clearance and is it the same as that set by the machine?
1.8    Do Set-Up Sheets specify Wave Type (Chip/Lambda/Omega) to be used?
1.9    Do Set-Up sheets specify the Solder Pot Hot Air Knife Pressure and Temperature settings?
1.10   Do Set-Up sheets specify if the Finger Cleaner must be on? No Finger Cleaner = 0
1.11   Is the machine Program Name specified on the Work Instruction or set-up sheets?
1.12   Do the all the above wave parameter settings correspond to those settings on the machine?
1.13   Are Generic Wave Set-Up Parameters documented? These are the parameters which are not changed for product changeovers.
1.14   Do these Generic Wave Set-Up Parameters include, pressure settings, conveyor angle, etc.
2. Machine Capability                                                                                                                                           1, 2       3, 4       5, 6        7, 8      9, 10       Actual
2.1    Is the flux application technology in use suitable for the product being built?
2.2    Is the wave technology in use suitable for the product being built in terms of the ability control critical parameters to achieve desired results?
2.3    Does the wave use a top side pre-heater to ensure PTH barrel fill meets IPC 610 specs given the mass of the board, carrier, and the top hat?
2.4    Are air flow controllers or a centralized control system used to balance exhaust flow rates for each individual exhaust drops?
2.5    Are exhaust flow rate ranges specified and monitored on a regular basis to insure compliance?
2.6    Is Automatic Wave Height control installed to control the laminar wave height?
2.7    Is there a Solder Pot Hot Air Knife installed and used on the wave equipment?
2.8    Is there an automatic Finger Cleaner installed and used on the wave equipment with an appropriated cleaning fluid? No FC = 0
2.9    Is the machine Program Name revision controlled to show traceability of program changes?
2.10   Is the machine Program Name traceable to the PCB and PCBA part number?
2.11   Is access to the machine program password protected with restricted access?
2.12   Do program changes to critical parameters during machine control remain unsaved unless approved by a technician/engineer?
2.13   Is the safety equipment and protective clothing provided adequate and are they used? Must include boots, apron, gloves, face shield, etc
3. Flux Application                                                                                                                                             1, 2       3, 4       5, 6        7, 8      9, 10       Actual
3.1    Is flux applied using either a fixed nozzle or moving nozzle spray application method? Any other application method = 0
3.2    Can the sequence of; detection, delay, trigger, duration, and stop, be clearly explained by a technician? Other method = 0
3.3    Is the detection, delay, trigger, duration, and stop, controls performing as expected? Other method = 0
3.4    Is there a feedback link between the conveyor speed and the flux applicator to auto-compensate for changes? Other method = 0
3.5    Is there an automatic sensor that indicates when a flux drum is near empty?
3.6    Is there a method to determine if the quantity of flux applied to the board to ensure it adequate? Not too much and not too little.
3.7    Is there a test used to check the coverage of flux applied to the board to ensure it is sufficient?
4. Wave Set-Up                                                                                                                                                  1, 2       3, 4       5, 6        7, 8      9, 10       Actual
4.1    Has specifying the Solder Pump Speed value been discontinued as a way to achieve the desired Wave Height?
4.2    Is the relationship between Wave Height set-up and Contact Area/Length known for the product being processed?
4.3    Is there a Quartz Plate available to verify Contact Area/Length achieved for the board being processed?
4.4    Is the documented Contact Area/Length being achieved for the Wave Height set-up used?
4.5    Does the shape of the Contact Area indicate parallelism?
4.6    Does the Contact Length coupled with the Conveyor Speed, achieve the documented dwell time requirement?
4.7    Is there evidence that Contact Area/Length and shape verified after Solder Pot removal and replacement, and maintenance?
4.8    Is there evidence that the Contact Area/Length and shape verified on addition of solder or on adjustment of lead clearance?
4.9    Does the board/pallet exit the Solder Pot in the stagnant area for the set conveyor angle and lead clearance?
4.10   Are all conveyor Fingers in a good state of repair?
4.11   Is the quantity, type and spacing of each Finger design defined for the conveyor?
4.12   Has the pot been set up to run with an intermittent wave so as to reduce dross build up? If gap between subsequent PCBAs too small, score 1
4.13   Does the level of Dross in the pot suggest that the pot is dedrossed at least once every 8 hours?


                                                                                                                                                                                                                    Page 20 of 34
Dell Confidential                                                                                                                                                                  Document No. COR.40.WWP.SQ.0023 Rev 4.0

5. Temperature Profile                                                                                                                                           1, 2      3, 4        5, 6      7, 8     9, 10       Actual
5.1    Is there available a Temperature Profile for the product currently being built?
5.2    Is the Temperature Profile assessable and readily available to operators / technicians as and when required?
5.3    Were the Pre-Heat Set Points, Conveyor Speed, and Solder Temperature logged for that Thermal Profile when it was conducted?
5.4    Do the Set Points, Conveyor Speed & Solder Temp written on the Thermal Profile correspond to the current Machine settings?
5.5    Is there available an Engineering based specification to detail the acceptable process window for Temperature Profiles?
5.6    Was the Engineering based spec. derived from the Flux manufacturer's recommendations but controls to a narrower window?
5.7    Does the product Temperature Profile fall within the Engineering based specification for the process window?
5.8    Does the product Temperature Profile fall within the Engineering based specification for glass transition temperature requirements?
5.9    Can any excursions outside of the process window be justified and supported with hard evidence and logical analysis?
5.10   Does the product Temperature Profile meet the requirements of the SMT components already attached to the PCBA?
5.11   Are the boards used to establish the initial Thermal Profile kept as engineering samples?
5.12   Have at least five thermocouples been used at various points on the board to establish the Thermal Profile? Note*
5.13   Is there a documented and systematic approach used to identify the most appropriate locations to attach the thermocouples?
5.14   Is there evidence that each thermocouple ball was bonded to a board joint using Hi Temp. Solder or Conductive Epoxy?
5.15   Is the top side Temperature Profile low enough to prevent secondary reflow? Must be below 160 degrees C.
5.16   Has a Calibration Profile been established in order to detect machine long term performance degradation?
5.17   Is there a documented frequency for running a Calibration Profile and was it established based upon historical performance data?
5.18   Is there evidence to demonstrate that Calibration Profiles are conducted and that records are up-to-date?
5.19   Is the practice of comparing the current Calibration Profile to the Standardized Calibration Profile used to identify changes?
5.20   Is the current Calibration Overlay/Profile used to determine if a variation in the wave's thermal characteristics has occurred?
5.21   Is the current Calibration Overlay/Profile used to determine if a variation in conveyor speed has occurred?
5.22   Is there evidence to demonstrate that action was taken when the Calibration Profile was different to the Standard?
5.23   Is a standardized tool, like a WaveRider, used with a standardized profile to conduct a Calibration Profile?
6. Solder Analysis                                                                                                                                               1, 2      3, 4        5, 6      7, 8     9, 10       Actual
6.1    Is there a documented frequency for conducting Solder Analysis and was this frequency established based upon historical results?
6.2    Is there evidence to demonstrate that Solder Analysis records are up-to-date?
6.3    Does the Solder Analysis results suggest that contaminants in the solder pot are within acceptable levels?
6.4    Is there evidence to demonstrate that action was taken when Solder Analysis results were unsatisfactory?
7. Manual Inspection                                                                                                                                             1, 2      3, 4        5, 6      7, 8     9, 10       Actual
7.1    Are outputted boards at least sample inspected post wave for wave solder defects as part of machine performance control?
7.2    Are Workmanship Standards defined for soldering, and are they accessible so that machine performance can be measured accurately?
       Is Defect Density Charting used to identify the common location of defects so that actions may be take to eliminate them? This may include
7.3
       addition of solder thieves, pallet/carrier modification, etc.
7.4    Is there evidence of the use of at least sampling X-ray to ensure via penetration and barrel fill are to acceptable standards?
                                                                                                                                         Maximum Score           78        78          78        78        78           78
                                                                                                                                          Score Obtained          0         0           0         0         0            0
                                                                                                                                        Score Percentage                                                                0%
                                                                                                                                         Pass Percentage        80%       80%          80%      80%       80%          80%
                                                                                                                                                                 Not       Not         Not       Not       Not         Not
                                                                                                                                               Outcome
                                                                                                                                                               Audited   Audited     Audited   Audited   Audited     Audited
       ^ See Instructions for details on when NA may be an appropriate entry.                                                                              0
       Note*: Thermocouples must be placed on top and bottom side of board for double sided boards.




                                                                                                                                                                                                                  Page 21 of 34
        Dell Confidential                                                                                                                                                          Document No. COR.40.WWP.SQ.0023 Rev 4.0


                                                                                      PCBA Quality Process Audit                                                                                         Menu
                                                                                                   Add a 'Y' to the Box if the Process Was Assessed
Post Wave Soldering
 #                                                                    Audit Criterion                                                                           1, 2      3, 4      5, 6       7, 8      9, 10     Actual
1. Automatic Inspection                                                                                                                                   Enter 1 or 0. NA may be a valid response for shaded cells.^
1.1    Are AOI/AXI complementary methods, which include solder joint inspection, used for assembled components?
1.2    Is the AOI/AXI coverage % calculated based on joints/components inspected versus those not inspected?
1.3    Is AOI/AXI coverage at 100% with a sample size of 100% for New Product Introductions (NPI), until capability has been established?
1.4    Post NPI, has AXI coverage and sample size been optimized based on cycle time and the use of complementary AOI strategies?
1.5    If sample size is not 100%, can AOI/AXI process control be evidenced based on Dell Metric 2 performance?
1.6    Are the components/joints not covered by AOI/AXI documented and known and targeted for visual inspection (except BGA joints)?
1.7    Can it be demonstrated that the machine calls are reviewed by the operator to determine if real or false?
1.8    Can it be demonstrated that operators have been fully trained and certified to interpolate the AOI/AXI images presented?
1.9    Does the ICT pareto of defects suggest that AOI/AXI is being effectively deployed as evidenced by Dell AXI/AOI Metric 2?
1.10   Can it be demonstrated that AOI/AXI detectable ICT failures are feed back to AOI/AXI to improve program and operator effectiveness?
1.11   Are changes to AOI/AXI coverage made based only on performance feedback?
2. Work Instructions                                                                                                                                            1, 2      3, 4      5, 6       7, 8      9, 10     Actual
       Is there a revision controlled Operator Work Instruction which contains information for the specific product being inspected? (Score 0 if any
2.1
       unsigned/undated handwritten instructions or any handwritten instructions more than 48 hrs old)
2.2    Do the Work Instructions specify the specific solder/flux/cleaning agent etc. to be used?
2.3    Do the Work Instructions define acceptable lead lengths and/or specific customer requirements?
2.4    Have the specific connector heights/lean acceptance and assembly requirements been addressed from the PCBA Assembly Drawings?
2.5    Are Work Instructions also used as an alert to flag specific customer or known issues?
2.6    Do the Work Instructions specify the specific inspection stamps and locations to be used? Score 1 if tracked using Forced Routing.
2.7    Do Work Instructions require AOI/AXI Paper Less Repair (PLR) data to be evaluated?
3. Manual Inspection (NA allowed, for questions 3.1 to 3.5 if AOI or AXI is deployed)                                                                           1, 2      3, 4      5, 6       7, 8      9, 10     Actual
3.1    Are outputted boards 100% inspected for wave solder defects and for lead evidence?
3.2    Are outputted boards 100% inspected for missing PTH components & polarity, and raised/tilted PTH components?
3.3    Are outputted boards 100% inspected for those components and joints not covered by ICT or AOI/AXI?
3.4    Are Workmanship Standards defined for soldering, and are they accessible and used to determine board acceptability?
3.5    Is there a visual aid available which identifies the populated PTH locations with polarity, and also the no-pop locations?
3.6    Are AOI/AXI Paper Less Repair (PLR) Stations effectively used at inspection for the evaluation of AOI/AXI defect calls?
3.7    Is there a point and click software tool post reflow which is linked to CAD or program data to facilitate component identification for rework?
3.8    Is it evident that lead snipping has been minimized through adequate component prep and/or pallet support design?
3.9    Is there a tool available and used to check component lead length against the required lead length specification?
3.10   Is it evident that only those leads which exceed the specification for component lead length are snipped?
3.11   Are magnification & lighting tools available at the inspection station? Magnification must be as per IPC based on component type.
4. Process Control                                                                                                                                              1, 2      3, 4      5, 6       7, 8      9, 10     Actual
4.1    Is there evidence that the SPC used to monitor output post reflow, is effective at identifying & correcting process performance issues?
4.2    Is the processes DPMO and the products DPU monitored in real time? ('real-time'=now)
4.3    Is OFE data readily available and calculated in accordance to the Dell documented procedures? (Doc. No. COR.40.WWP.SQ.0209)
4.4    Is AOI/AXI data used to calculate Wave DPMO? Score 0 if AOI/AXI is deployed and not done.
4.5    Are ICT debug results used to re-calculate Wave DPMO as a true measure of Wave DPMO?
4.6    Is the data collected meaningful and can it be demonstrated that it is used to make process control decisions?
                                                                                                                                       Maximum Score            35        35        35         35         35        35
                                                                                                                                       Score Obtained            0        0          0          0          0         0
                                                                                                                                     Score Percentage                                                               0%
                                                                                                                                      Pass Percentage          80%       80%       80%       80%        80%        80%
                                                                                                                                                                Not       Not       Not       Not        Not        Not
                                                                                                                                                Outcome
                                                                                                                                                              Audited   Audited   Audited   Audited    Audited    Audited
       ^ See Instructions for details on when NA may be an appropriate entry.                                                                             0




                                                                                                                                                                                                                   Page 22 of 34
        Dell Confidential                                                                                                                                                  Document No. COR.40.WWP.SQ.0023 Rev 4.0


                                                                           PCBA Quality Process Audit                                                                                                           Menu
                                                                                        Add a 'Y' to the Box if the Process Was Assessed
Mechanical Assembly
 #                                                               Audit Criterion                                                                    1, 2       3, 4       5, 6        7, 8      9, 10          RMA     Actual
1. Work Instructions                                                                                                                             Enter 1 or 0. NA may be a valid response for shaded cells.^
       Is there a revision controlled Operator Work Instruction which contains details of how to assemble the product? (Score 0 if any
1.1
       unsigned/undated handwritten instructions or any handwritten instructions more than 48 hrs old)
1.2    Are Work Instructions readily available to the operator and are they followed at Assembly?
1.3    Are component part numbers and descriptions included on the Work Instructions?
1.4    Are components sufficiently identified to ensure the correct component is being used?
1.5    Is the layout of totes/trays defined on Work Instructions for each assembly station?
1.6    Are all totes/trays located in a defined position as per Work Instructions for each assembly station?
1.7    Do Work Instructions contain clear pictures to aid the operator & ensure the correct assembly method is understood?
1.8    Are torque settings and the sequence of screw insertion specified for screw assembly operations?
1.9    Are all torque drivers set to the required torque and screws inserted in the right sequence?
1.10   Is there evidence that torque drivers are checked with a calibrated tool at least once a day to ensure the correct torque requirements?
1.11   Do all torque drivers have 'lock nuts' to fix the torque setting after calibration to prevent operator adjustment?
1.12   Are protective guides used to ensure that torque drivers cannot cause damage to the product due to operator error?
1.13   Are all hand tools needed by the operator listed with their descriptions on Work Instructions?
2. Board Tooling / Depanelization                                                                                                                   1, 2       3, 4       5, 6        7, 8      9, 10          RMA     Actual
2.1    Is breakout tooling specifically designed for the board or is a line-side Router or v-score machine used? Manual breakout=0.
2.2    Can it be demonstrated that board flexing has been minimized and clearance is sufficient by using such tooling?
2.3    For v-scored boards, are boards positioned using a fixture so that the cutting tool and can only cut occur along the v-score?
2.4    Can it be demonstrated that the board is supported before and after the cut so as to prevent board damage due to dropping?
2.5    Does the press fit tooling use force feedback control that provides repeatable installation and prevents PWB damage?
2.6    Has all tooling used at Mechanical Assembly been designed to minimize board flexing?
3. Heatsinks and Mechanical Bonding                                                                                                                 1, 2       3, 4       5, 6        7, 8      9, 10          RMA     Actual
3.1    Is heatsink installation tooling used to align heatsinks to the required orientation and position tolerance?
3.2    Is the force applied to the heatsink and the duration of the applied force documented on Work Instructions and controlled?
3.3    Is the dry time for the solvent document on Work Instructions and controlled?
3.4    Is there a process to control the volume of thermal adhesive and activator applied to ensure the required bond strength?
3.5    Is the cure time for the thermal adhesive documented on Work Instructions and controlled?
4. Line Set-Up and Verification                                                                                                                     1, 2       3, 4       5, 6        7, 8      9, 10          RMA     Actual
4.1    Are first-assembled boards verified against documentation to ensure mechanical items have been assembled correctly?
4.2    Are all totes or tray locations identified with printed part numbers, descriptions, locations, and layout information?
4.3    Is the Mechanical Assembly work cell laid out ergonomically with components & assembly tools within easy reach?
4.4    Are mechanical items stored before and during use in a manner which prevents damage?
4.5    Are color coding techniques deployed for parts, tools, work instructions etc. in an attempt to error proof the process?
5. Manual Inspection                                                                                                                                1, 2       3, 4       5, 6        7, 8      9, 10          RMA     Actual
5.1    Is there evidence to demonstrate that a defect feedback process is in operation to Mechanical Assembly?
5.2    Are cosmetic standards are readily available to the assembly operator on the assembly line?
                                                                                                                           Maximum Score            31         31          31         31         31            31          31
                                                                                                                            Score Obtained          0          0           0          0          0             0           0
                                                                                                                          Score Percentage
                                                                                                                           Pass Percentage         80%       80%         80%        80%         80%        80%          80%
                                                                                                                                                    Not       Not         Not        Not         Not        Not          Not
                                                                                                                                    Outcome
                                                                                                                                                  Audited   Audited     Audited    Audited     Audited    Audited      Audited
       ^ See Instructions for details on when NA may be an appropriate entry.                                                                    0




                                                                                                                                                                                                           Page 23 of 34
       Dell Confidential                                                                                                                                             Document No. COR.40.WWP.SQ.0023 Rev 4.0



                                                                                PCBA Quality Process Audit                                                                                              Menu
                                                                                             Add a 'Y' to the Box if the Process Was Assessed
In Circuit Test            See Note*
 #                                                                 Audit Criterion                                                                 1, 2      3, 4       5, 6       7, 8      9, 10      RMA      Actual
1. Operator and Work Instructions                                                                                                               Enter 1 or 0. NA may be a valid response for shaded cells.^
     Is there a revision controlled Test Instruction which contains unique details for the specific product being tested? (Score 0 if any
1.1
     unsigned/undated handwritten instructions or any handwritten instructions more than 48 hrs old)
1.2 Are Work Instructions readily available to the test operator and are they followed?
1.3 Is the Fixture ID specified on Work Instructions?
1.4 Is the Fixture ID traceable to a specific PCBA part number and revision level and to the Unit Under Test?
1.5 Is the Batch File specified on Work Instructions?
1.6 Is the Batch File traceable to a specific PCBA part number and revision level and to the Unit Under Test?
1.7 Is the Vacuum setting and range specified on Work Instructions?
1.8 Is the PCB orientation to the Fixture identified in the Work Instructions or on the Fixture?
1.9 Does the test Operator have the Standard Operating Procedure (SOP) for the tester available to them at all times?
1.10 Is there evidence that the Operator has been trained and certified against the Standard Operating Procedure for the Tester?
1.11 Does the Operator know the content of the Standard Operating Procedure for the Tester and do they and follow it?
1.12 Are Operators required to log in at the Test station and does this provide an automatic verification of training status?
2. ICT Fixture                                                                                                                                     1, 2      3, 4       5, 6       7, 8      9, 10      RMA      Actual
2.1   Is the ICT fixture identified with a name or number?
2.2   Is the Preventative Maintenance / Calibration sticker on the ICT fixture current and up to date?
2.3   Is there a Preventative Maintenance procedure and schedule for ICT fixtures?
2.4   Is there evidence to demonstrate that Preventative Maintenance records are up-to-date?
2.5   Are spare test fixture parts (excluding probes) stocked?
2.6   Are spare test fixture probes stocked for each design required to support Dell fixtures?
2.7   Is the inventory of spare test fixture parts adequately controlled?
2.8   Are ICT fixtures adequately stored in such a way that the tester interface is protected?
3. ICT System Hardware                                                                                                                             1, 2      3, 4       5, 6       7, 8      9, 10      RMA      Actual
3.1   Is there a vacuum gauge on the line connected to the test system?
3.2   Is a calibrated vacuum gauge visible to the test operator and is it at the correct setting within an acceptable range?
3.3   Is the Preventative Maintenance / Calibration sticker on the Test System current and up to date?
3.4   Is there a Preventative Maintenance procedure and schedule for ICT Test Systems?
3.5   Are the test systems pin electronics verified daily using the internal test?
3.6   Is there evidence to demonstrate that Preventative Maintenance records are up-to-date?
3.7   Are spare test system parts stocked?
3.8   Are spare test system pin electronics boards stocked?
3.9   Are the inventory of spare test system parts adequately controlled?
4. ICT Software                                                                                                                                    1, 2      3, 4       5, 6       7, 8      9, 10      RMA      Actual
4.1   Are all ICT test systems networked to a server?
4.2   Is the ICT software downloaded from a central server when the program is called up or at least compiled once per day?
4.3   Is the ICT software revision controlled for program changes?
4.4   Are all changes to an ICT program, no matter how insignificant the change is considered, logged in the program or otherwise?
4.5   Is it impossible for unapproved ICT s/w changes to remain on the test system longer than 24 hours before recompiling the program?
4.6   When changes are made, is there evidence that change details are sent to Dell for approval?
5. Test Operation                                                                                                                                  1, 2      3, 4       5, 6       7, 8      9, 10      RMA      Actual
5.1   Is there an automated method of loading test programs (i.e. the batch file).
5.2   Is the Fixture ID used to select and automatically load the correct ICT program for the unit under test?
5.3   If the same ICT fixture is used for different PCBA part numbers, does the Batch file automatically differentiate? NA may be used.
5.4   Is there a foolproof method to ensure that product A will not pass ICT if Batch File B is used? NA may be used.
5.5   Is there a foolproof method to ensure that product B will not pass ICT if Batch File A is used? NA may be used.


                                                                                                                                                                                                     Page 24 of 34
        Dell Confidential                                                                                                                                                   Document No. COR.40.WWP.SQ.0023 Rev 4.0

5.6    Is the PCBA orientation to the fixture identified or is required to be checked before board loading?
5.7    Is the test program uniquely identified on the test system display after the test program has been loaded?
5.8    Is there a documented and agreed convention outlining the storage of untested, failed, and pass boards?
5.9    Are boards marked in some way to facilitate the implementation of this convention? (Forced Routing is acceptable.)
5.10   Are boards awaiting test identified and stored separately according to the convention OR routed via a dedicated conveyor?
5.11   Are passing boards identified and stored separately according to the convention OR routed via a dedicated conveyor?
5.12   Are failing boards identified and stored separately according to the convention OR routed via a dedicated conveyor?
5.13   Are pass and failed boards stored on different storage carts OR routed via a unique conveyor?
5.14   Is SPC data collected and effectively used at this process point?
5.15   Is the content of the SPC data chart up-to-date?
5.16   Are out of control SPC data points effectively actioned?
5.17   Are ICT buffer trigger points established to ensure process shut down should the limits be exceeded?
5.18   Has a Gauge R&R study been completed in accordance with Dell GR&R Procedures? (Doc No. COR.40.WWP.SQ.0207)
5.19   Has test coverage been calculated using the 7 Dell Metrics for ICT coverage, and is this readily available and known?
6. ICT WIP Tracking                                                                                                                                       1, 2      3, 4      5, 6      7, 8     9, 10      RMA       Actual
6.1    Is a Forced Board Routing system and WIP Tacking system fully deployed throughout the test process?
6.2    Does the system verify the 'last' step processed and compare it to the expected 'last' step?
6.3    Do boards that PASS have an identifying mark to indicate their pass status? (Forced Routing is acceptable.)
6.4    Do boards that FAIL have an identifying mark to indicate their fail status? (Forced Routing is acceptable.)
6.5    Do failed boards have ICT fail listings attached for debug purposes? (Paperless repair is acceptable)
6.6    Do all debugged boards have an identifying mark to indicate a debug status? (Forced Routing is acceptable.)
6.7    Is there a software link between ICT Test results & the Forced Routing/Quality Data System?
6.8    Does this software link eliminate manual intervention to indicate the test result status?
6.9    Is this link fully automated and used to log Test Yield/First Pass Yield & Board Yield data?
6.10   Is FPY and BY readily known and has it been calculated in accordance with Dell definitions and specified retry conditions?
6.11   For boards tested in panel format, is the failed board identified before the panel is removed from the fixture?
7. Debug and FA Capability                                                                                                                                1, 2      3, 4      5, 6      7, 8     9, 10      RMA       Actual
7.1    Are boards awaiting debug identified and stored to one side of the operator or routed via dedicated conveyor?
7.2    Are debug buffer trigger points established to ensure process shut down should the limits be exceeded?
7.3    Can it be demonstrated that a technician qualification or formal training is required for debug and failure analysis activity?
7.4    Can it be demonstrated that all debug personnel meet the above requirements ?
7.5    Is there adequate debug equipment available at each debug station ?
7.6    Is ICT debug and repair conducted real-time (on-line) whenever possible?
7.7    Can it be demonstrated that a tool is used to capture fail codes, their fixes, and then recommend the most common fix?
7.8    Does the ICT debug technician access the ICT system via a display unit to better understand to root cause of failure?
7.9    Is a test point location map available to the repair/failure analysis operator?
7.10   Are there detailed instructions on determining false failures?
7.11   Are false failure rates tracked, monitored, and documented?
7.12   Are there goals for false failure reduction? (I.e. goals to increase FPY)
                                                                                                                                     Maximum Score        77        77         77       77        77          77          77
                                                                                                                                      Score Obtained      0         0          0        0         0           0           0
                                                                                                                                   Score Percentage
                                                                                                                                    Pass Percentage      80%       80%       80%       80%       80%        80%       80%
                                                                                                                                                          Not       Not       Not       Not       Not        Not       Not
                                                                                                                                         Outcome
                                                                                                                                                        Audited   Audited   Audited   Audited   Audited    Audited   Audited
       ^ See Instructions for details on when NA may be an appropriate entry.                                                                          0
       Note*: ICT may not be deployed in some cases for products of complexity 9 and 10 as determined by Dell.




                                                                                                                                                                                                          Page 25 of 34
       Dell Confidential                                                                                                                                                     Document No. COR.40.WWP.SQ.0023 Rev 4.0


                                                                                  PCBA Quality Process Audit                                                                                                Menu
                                                                                               Add a 'Y' to the Box if the Process Was Assessed
Functional Test                See Note*
 #                                                                   Audit Criterion                                                                  1, 2     3, 4       5, 6        7, 8      9, 10       RMA      Actual
1. Operator and Work Instructions                                                                                                                 Enter 1 or 0. NA may be a valid response for shaded cells.^
        Is there a revision controlled Test Instruction which contains unique details for the specific product being tested? (Score 0 if any
1.1
        unsigned/undated handwritten instructions or any handwritten instructions more than 48 hrs old)
1.2     Are Work Instructions readily available to the test operator and are they followed?
1.3     Is the Test File name and number specified on Work Instructions?
1.4     Is the Test File traceable to a specific PCBA part number and revision level and to the Unit Under Test?
1.5     Does the test Operator have the Standard Operating Procedure (SOP) for the tester available to them at all times?
1.6     Is there evidence that the Operator been trained and certified against the Standard Operating Procedure for the Tester?
1.7     Does the Operator know the content of the Standard Operating Procedure for the Tester and do they and follow it?
1.8     Are Operators required to log in at the Test station and does this provide an automatic verification of training status?
2. Fn Test Fixture                                                                                                                                    1, 2     3, 4       5, 6        7, 8      9, 10       RMA      Actual
2.1     Is the Test fixture identified with a name or number?
2.2     Is the Preventative Maintenance / Calibration sticker on the fixture current and up to date?
2.3     Is there a Preventative Maintenance procedure and schedule for each Test fixture?
2.4     Is there evidence to demonstrate that Preventative Maintenance records are up-to-date?
2.5     Are NDF rates used to flag a test station maintenance schedule?
2.6     Are there goals for NDF reduction specified for each product and each fixture?
2.7     Are spare parts for test stocked?
2.8     Is the inventory of spare test parts adequately controlled?
3. Fn Test Software                                                                                                                                   1, 2     3, 4       5, 6        7, 8      9, 10       RMA      Actual
3.1     Are all Fn Test systems networked to a server?
3.2     Is the Functional Test software downloaded from a central server when the program is called up and at least daily thereafter?
3.3     Is the Fn Test software revision controlled for program changes?
3.4     Is a control method used to log all changes to the Fn Test program and is it available?
4. Test Operation                                                                                                                                     1, 2     3, 4       5, 6        7, 8      9, 10       RMA      Actual
4.1     Is there an automated method of loading test programs?
4.2     Is there a documented and agreed convention outlining the storage of untested, failed, and pass boards?
4.3     Are boards marked in some way to facilitate the implementation of this convention? (Forced Routing is acceptable.)
4.4     Are boards awaiting test identified and stored separately according to the convention OR routed via a dedicated conveyor?
4.5     Are passing boards identified and stored separately according to the convention OR routed via a dedicated conveyor?
4.6     Are failing boards identified and stored separately according to the convention OR routed via a dedicated conveyor?
4.7     Are pass and failed boards stored on different storage carts OR routed via a unique conveyor?
4.8     Is SPC data collected and effectively used at this process point?
4.9     Is the content of the SPC data chart up-to-date?
4.10    Are out of control SPC data points effectively actioned?
4.11    Are Fn Test buffer trigger points established to ensure process shut down should the limits be exceeded?
4.12    Has a Gauge R&R study been completed in accordance with Dell GR&R Procedures? (Doc No. COR.40.WWP.SQ.0207)
4.13    Is test coverage calculated based on the total number of functions and features versus those that are exercised? (See Dell Feature Summary)
5. Fn Test WIP Tracking                                                                                                                               1, 2     3, 4       5, 6        7, 8      9, 10       RMA      Actual
5.1     Is a Forced Board Routing system and WIP Tacking system fully deployed throughout the test process?
5.2     Does the system verify the 'last' step processed and compare it to the expected 'last' step?
5.3     Do boards that PASS have an identifying mark to indicate their pass status? (Forced Routing is acceptable.)
5.4     Do boards that FAIL have an identifying mark to indicate their fail status? (Forced Routing is acceptable.)
5.5     Do failed boards have Fn fail details attached for debug purposes?
5.6     Do all debugged boards have an identifying mark to indicate a debug status? (Forced Routing is acceptable.)
5.7     Is there a software link between Fn Test results & the Forced Routing/Quality Data System?
5.8     Does this software link eliminate manual intervention to indicate the test result status?
5.9     Is this link fully automated and used to log Test Yield/First Pass Yield & Board Yield data?
5.10    Is FPY and BY readily known and has it been calculated in accordance with Dell definitions?
5.11    Can it be demonstrated that there are no boards in the debug analysis loop for longer than 30 days?
5.12    Can it be demonstrated that boards in the Fn Debug Loop have had their ICT Pass mark removed before being returned to ICT?
                                                                                                                                                                                                            Page 26 of 34
       Dell Confidential                                                                                                                                                     Document No. COR.40.WWP.SQ.0023 Rev 4.0
6. Debug and FA Capability                                                                                                                              1, 2     3, 4     5, 6       7, 8     9, 10     RMA       Actual
6.1     Are boards awaiting debug identified and stored to one side of the operator or routed via dedicated conveyor?
6.2     Are debug buffer trigger points established to ensure process shut down should the limits be exceeded?
6.3     Can it be demonstrated that a technician qualification or formal training is required for debug and failure analysis activity?
6.4     Can it be demonstrated that all debug personnel meet the above requirements ?
6.5     Is there adequate debug equipment available at each debug station ? E.g. Multimeter, oscilloscope, bus emulator, etc.
6.6     Can it be demonstrated that a tool is used to capture fail codes, their fixes, and then recommend the most common fix?
6.7     Are schematics for the latest revision of the board available?
6.8     Has it been demonstrated that component replacement data is logged by board serial number?
6.9     Is it clear which components have been replaced on each board in the repair/failure analysis area? (Use Shop Floor Data System)
6.10    Has it been demonstrated that each board has a record showing the number of components replaced? (Use Shop Floor Data System)
6.11    Is lot level traceability maintained for any critical components that have been replaced?
6.12    Are there detailed instructions on determining false failures?
6.13    Are false failure rates tracked, monitored, and documented?
6.14    Are there goals for false failure reduction? (i.e. goals to increase FPY)
                                                                                                                                      Maximum Score     59       59        59        59        59        59         59
                                                                                                                                       Score Obtained    0        0         0        0          0         0          0
                                                                                                                                    Score Percentage
                                                                                                                                     Pass Percentage80%         80%       80%       80%       80%       80%       80%
                                                                                                                                                     Not         Not       Not       Not       Not       Not       Not
                                                                                                                                          Outcome
                                                                                                                                                   Audited     Audited   Audited   Audited   Audited   Audited   Audited
        ^ See Instructions for details on when NA may be an appropriate entry.                                                                    0
        Note*: Functional Test may not be deployed in some cases for products of complexity 9 and 10 at determined by Dell.




                                                                                                                                                                                                         Page 27 of 34
       Dell Confidential                                                                                                                                                          Document No. COR.40.WWP.SQ.0023 Rev 4.0


                                                                                     PCBA Quality Process Audit                                                                                                      Menu
                                                                                                   Add a 'Y' to the Box if the Process Was Assessed
General Process
 #                                                                     Audit Criterion                                                                        1, 2       3, 4       5, 6       7, 8      9, 10      RMA      Actual
1. Environmental and ESD Control                                                                                                                           Enter 1 or 0. NA may be a valid response for shaded cells.^
1.1     Are there temperature & humidity sensors in the Manufacturing area to monitor temperature & humidity over time?
1.2     Are there documented upper & lower specification limits for temperature and humidity to assure Paste viscosity, ESD & MSD control?
1.3     Is there evidence to demonstrate that effective action was taken when the temperature/humidity was outside the defined limits?
1.4     If AC Ground is used as Earth Ground for ESD purposes, is it clearly understood that AC Ground must be connected to a grounding rod?
1.5     Is ESD Earth Ground impedance (grounding rod to earth) measured at least annually?
1.6     Does the above measurement result comply with established specifications?
1.7     Is either an ESD Conductive or Static Dissipative floor installed in the Manufacturing areas? ESD Matting also scores 0, except for 7 thru 10.
1.8     Is there evidence that the floor was installed using conductive adhesive with copper earth grounding straps?
1.9     Is there evidence that the floor is cleaned in accordance with the floor/coating manufacturer's specification?
1.10    Are fixed material storage racks for components/assemblies earth grounded?
1.11    Do portable material storage racks for components/assemblies use conductive wheels or drag chains to contact the ESD floor?
1.12    Are all machines ESD Earth Grounded?
1.13    Are timed Resistance-to-Ground tests conducted using an ESD Meter to periodically evaluate ESD performance?
1.14    Is there evidence that at least five tests are taken per 5000 square feet of production floor space?
1.15    Is there evidence of periodic performance testing of the floor, fixtures, and all work and material storage surfaces in the ESD protective area?
1.16    Are ESD protective areas appropriately marked and labeled?
1.17    Is there evidence that anyone in the ESD protective area is required to wear ESD Smocks and two ESD Shoe Straps/ESD Shoes? Note*
1.18    Is there evidence that anyone seated must use a wired ESD strap while handling components in addition to Shoe Straps/ESD Shoes?
1.19    Is there evidence that the chairs used are ESD safe and are they in conductive contact with the floor?
1.20    Is there evidence that Shoe Straps/ESD Shoes and wired wrist/ankle straps are tested each time ESD Protective items are garbed?
1.21    Is there evidence that the materials used in operator tools inside the ESD protective area ESD safe?
1.22    Is there evidence that Antistatic & Static dissipative material (usually pink) is not used outside the ESD area for component storage?
1.23    Is there evidence that Static Shielded material (usually gray) is used outside the ESD area for component storage?
1.24    Is there evidence that periodic Static Audits are conducted to verity the ESD grounding system deployed in the ESD area?
2. Line Set-Up and Control                                                                                                                                    1, 2       3, 4       5, 6       7, 8      9, 10      RMA      Actual
2.1 Is a Forced Board Routing system and WIP Tacking system fully deployed throughout SMT, PTH and Test?
2.2 Are all boards tracked through the process by serial number and is board history available for traceability purposes?
2.3 Does the system verify the 'last' step processed and compare it to the expected 'last' step?
2.4 Are quality performance or buffer trigger points established to ensure machine shut down should the limits be exceeded?
2.5 Are line shutdown criteria clearly specified for both quality and buffer limiting requirements?
2.6 Is there a documented checklist available and in use to ensure successful product changeover?
3. Machine Maintenance (Select any machine used in the PCBA Manf. process and answer all questions below base on selection)                                   1, 2       3, 4       5, 6       7, 8      9, 10      RMA      Actual
3.1 Is there a recommended Spare Parts list for the selected machine?
3.2 Are on-hand stock quantities and minimum reorder points set and controlled using a database?
3.3 Does the on-hand stock balance reflect the physical stock quantities for two samples taken?
3.4 Are Daily Maintenance logs kept at the machine and are they up to date?
3.5 Is a Preventative Maintenance System used to flag when periodic Preventative Maintenance is required?
3.6 Is there evidence to demonstrate that Preventative Maintenance records are up-to-date?
3.7 Are problem descriptions and their closure recorded and verified on the Daily and Preventative Maintenance logs?
4. Machine Operator (Select any machine operator in the PCBA Manf. area and answer all questions below base on selection)                                     1, 2       3, 4       5, 6       7, 8      9, 10      RMA      Actual
4.1 Does the Operator have the Standard Operating Procedure (SOP) for the machine available to them at all times?
4.2 Are WIs & SOPs free of hand written updates? Temporary hand written updates are OK if signed and dated with expiration date <48 hrs.
4.3 Is there evidence that the Operator has been trained and certified against the Standard Operating Procedure for the Machine?
    Does the Operator know the content of the Standard Operating Procedure for the Machine and do they and follow it? (Score 1 if the operator
4.4
    has not memorized the contents, but can quickly reference the SOP to answer the auditors questions.)
4.5 Are Operators required to log in at the Machine station and does this provide an automatic verification of training status?
5. PCBA Inspector (select any inspector in the PCBA Manufacturing area and answer all questions below base on selection)                                      1, 2       3, 4       5, 6       7, 8      9, 10      RMA      Actual
5.1 Is the Inspector required to wear gloves or finger cots when handling boards and do they wear them?
5.2 Does the Inspector have the IPC-610 standard available to them at all times? (Score 1 if a copy of IPC 610 is available in the general area.)

                                                                                                                                                                                                                  Page 28 of 34
      Dell Confidential                                                                                                                                                         Document No. COR.40.WWP.SQ.0023 Rev 4.0
5.3    Is there evidence that the Inspector has been trained and certified against the IPC-610 Standard and on component identification?
5.4    Does the Inspector know the content of the IPC-610 Standard and are they able to read component identification markings?
5.5    Are Operators required to log in at the inspection station and does this provide an automatic verification of training status?
5.6    Do quality inspectors have access to sampling plans (e.g. ANSI, MIL, ASQ) at all times?
5.7    Does the quality inspector know the sampling plan and switching rules for increased/decreased sample sizes?
5.8    Does quality inspector have access to product specific reference tools, (e.g. golden unit, templates)?
5.9    Is there evidence that quality inspector has been trained/certified in basic quality practices and statistics/SQC?
6. Chemical Compatibility                                                                                                                                     1, 2      3, 4     5, 6       7, 8     9, 10      RMA      Actual
6.1  Is there a master matrix which outlines the Chemical Compatibility for solder wire, fluxes, flux pens, cleaning solutions, etc?
6.2  Was a study conducted to assure the chemical compatibility of the consumables on the list and is it available?
6.3  Are specifications readily available for the various types of solder, flux, cleaning agents, etc. being used?
6.4  Are Chemical Industry standard labeling used to identify all chemicals used, e.g. flux, alcohol, etc?
7. Programmed Parts (Score NA if programming is subcontracted to a supplier)                                                                                  1, 2      3, 4     5, 6       7, 8     9, 10      RMA      Actual
     Are revision controlled Work Instructions displayed for the operator at the programming station? (Score 0 if any unsigned/undated
7.1
     handwritten instructions or any handwritten instructions more than 48 hrs old)
7.2 Are component part numbers and their descriptions specified on Work Instructions?
7.3 Are component descriptions sufficiently detailed to ensure the correct blank component is being used?
7.4 Are label part numbers identified and a drawing/picture of the label contents included on the Work Instruction if labels are required?
7.5 Is the orientation of the label on the component consistent and does it include the correct checksum information if required?
7.6 Are parts only labeled post programming with the program information if such info is required as per Dell's specification drawings?
7.7 Is there evidence to demonstrate that programmed parts are clearly segregated from unprogrammed parts?
7.8 Is the Master Program name/number and revision indicated on the Work Instructions and traceable to the current PCBA revision?
7.9 Do Work Instructions indicate the orientation for loading blank components into the programmer?
7.10 Are the Moisture Sensitive Devices (MSDs) readily known to the operator?
7.11 Are MSDs time stamped at opening and their exposure time recorded as a result of programming?
7.12 Can MSD control, according to J-STD-033A,l be demonstrated for MSD devices that need programming?
7.13 Is the orientation of programmed parts in their packaging preserved before and after programming?
7.14 Is there evidence that a defined process for non-conforming material such as damaged, failing or programmable parts is in operation?
                                                                                                                                       Maximum Score          69        69        69        69        69         69           69
                                                                                                                                       Score Obtained         0         0          0         0         0          0            0
                                                                                                                                     Score Percentage
                                                                                                                                      Pass Percentage        80%       80%       80%       80%       80%       80%        80%
                                                                                                                                                              Not       Not       Not       Not       Not       Not        Not
                                                                                                                                           Outcome
                                                                                                                                                            Audited   Audited   Audited   Audited   Audited   Audited    Audited
       ^ See Instructions for details on when NA may be an appropriate entry.                                                                           0
       Note*: Due to a safety concern some personal may not be required to wear ESD Smocks and two ESD Shoe Straps / ESD Shoes?




                                                                                                                                                                                                              Page 29 of 34
      Dell Confidential                                                                                                                                                           Document No. COR.40.WWP.SQ.0023 Rev 4.0


                                                                                  PCBA Quality Process Audit                                                                                                          Menu
                                                                                                Add a 'Y' to the Box if the Process Was Assessed
Rework and Repair
 #                                                                   Audit Criterion                                                                       1, 2        3, 4       5, 6       7, 8       9, 10     RMA        Actual
1. General Repair Capability                                                                                                                            Enter 1 or 0. NA may be a valid response for shaded cells.^
1.1     Is the capability of each piece of rework equipment defined to ensure the correct equipment is used for the correct rework operation?
1.2     Is the rework process and equipment used appropriate to meet established industry standards and Dell standards?
1.3     Is the age, limit quantity, and ECO level of boards in a repair loop monitored?
1.4     Is there a tracking system in place to monitor and limit the number of Reworks conducted on any given unique board serial number?
1.5     Is there a demonstrated method in place to highlight differences between a board's ECO level and the current board's ECO level?
1.6     Does this method flag the rework path necessary to bridge the ECO gap?
1.7     Is minimal shippable ECO information available and a reliable method in place to ensure it is kept current?
1.8     Is there a reliable tool available to provide ASL details for each component reference designator for the current BOM revision?
1.9     Is there a reliable method in place to ensure BOM information is kept current?
2. General Rework and Repair                                                                                                                               1, 2        3, 4       5, 6       7, 8       9, 10     RMA        Actual
2.1     Is rework conducted real time and on the production line except for rework requiring specialized equipment?
2.2     Is there a documented Rework Standard Operating Procedure for board preparation, rework techniques, and post rework practices?
2.3     Are all reworks carried out to IPC 7711 & 7721 standards?
2.4     Prior to replacing a passive device is the operator required to verify its value using multimeter and do they?
2.5     Is there a documented frequency for the calibration and maintenance of Soldering Irons? Score 1 if Self Calibrating (SC).
2.6     Is Solder Iron calibration conducted for the combination of a specific handheld iron with a specific control box? Score 1 if SC.
2.7     Does the handheld iron in use correspond to the control box used as indicated by the calibration records? Score 1 if SC.
2.8     Is there evidence to demonstrate that Soldering Iron calibration and maintenance is adequate and that records are up-to-date?
2.9     Are the operating temperatures and tip sizes to be used for the different component types clearly defined?
2.10    Are all Soldering Irons in use grounded?
2.11    Are rework consumables, i.e. Solder Wire, Flux, Cleaning agents, conditions of use documented?
2.12    Are components required for rework stored a manner as to prevent damage prior to use?
2.13    Does the reworker have access to visual aids/tools which will identify the value, location & polarity of components to be replaced ?
2.14    Are the MSD devices being used in the replacement process stored and used according to their moisture level sensitivity rating?
2.15    Is there evidence to demonstrate that the control process in use for MSDs is effective and complies with J-STD-0033A?
2.16    Is there evidence that a board must be slow baked prior to MSD removal for when an MSD component is needed for failure analysis?
2.17    Is the bake procedure compliant with JEDEC standard J-STD-033A?
2.18    Is there evidence that the date code/lot code, part number and source of failed ICs is recorded for future failure analysis?
2.19    Is there evidence that the date code/lot code, of the replacement IC is recorded against the board serial number for traceability?
3. BGA Rework                                                                                                                                              1, 2        3, 4       5, 6       7, 8       9, 10     RMA        Actual
3.1     Are all BGA devices replaced using dedicated BGA Replacement Equipment with bottom side board heating and split prism alignment?
        Is there a documented Standard Operating Procedure for the setup and operation of BGA Replacement Equipment? (Score 0 if any
3.2
        unsigned/undated handwritten instructions or any handwritten instructions more than 48 hrs old)
3.3     Does the procedure specify the program name, nozzle & nest to be used for each type of BGA component?
3.4     Are specific removal and replacement reflow profiles available for each type of BGA component based on package type or part number?
        Is there a revision controlled Operator Work Instruction for site preparation (cleaning PWB pads, application of flux/paste, etc.)? (Score 0
3.5
        if any unsigned/undated handwritten instructions or any handwritten instructions more than 48 hrs old)
3.6     Is there a consistent & repeatable process for the application of flux &/or paste to the PWB or new BGA, defined in the Work Instruction?
        Are all materials required for the application process listed in the Work Instruction and in a good state of repair? (This includes fixtures,
3.7
        micro-stencils, tools, consumables, etc.)
        Is alignment of the micro-stencil to the PWB/BGA accomplished via automated methods or fixturing? Score 0 if only manual visual
3.8
        alignment is used.
3.9     Is micro-stencil print quality inspected after printing? Sample inspection allowed if DOE and post re-work test results support sampling.
3.10    Are flux/paste usage conditions (cold storage, thaw time, expiration, etc.) know and followed? (Reference "Paste Worksheet" section 2)
3.11    Has it been verified that the Flux/Paste used is compatible with the original solder paste used during the manufacturing process?
3.12    Is the removed BGA isolated from good product and dispositioned correctly?
3.13    Post BGA Rework, is the replaced BGA X-Rayed to verify replacement quality and to provide timely feedback on success or failure?




                                                                                                                                                                                                                 Page 30 of 34
      Dell Confidential                                                                                                                                                       Document No. COR.40.WWP.SQ.0023 Rev 4.0
3.14 Is there evidence that the date code/lot code, part number and source of failed BGA is recorded for future failure analysis?
3.15 Is there evidence that the date code/lot code, of the replacement BGA is recorded against the board serial number for traceability?
4. Mini-Wave Rework                                                                                                                                       1, 2       3, 4     5, 6       7, 8     9, 10     RMA      Actual
     Is there a documented Standard Operating Procedure for the setup and operation of Mini-Wave Equipment ? (Score 0 if any
4.1
     unsigned/undated handwritten instructions or any handwritten instructions more than 48 hrs old)
4.2 Does the procedure specify the solder type, its temperature setting, and the flux type to be used ?
4.3 Does the procedure specify the nozzle for specific component type & the solder exclusion pallet to be used for each board?
4.4 Has it been verified that the solder and other consumables are compatible with the original materials used during manufacturing?
4.5 Can it be demonstrated that solder exclusion pallets are used exclusively to minimize heat exposure to the rest of the board?
4.6 Has the use of Kapton tape been minimized/reduced due to the use of solder exclusion pallets?
4.7 Does the Mini-Wave set-up allow the operator to use both hands to replace the component?
4.8 Are components being used in the replacement process identified and stored correctly?
4.9 Are the components being used in the replacement process stored in their original packaging up to the point of use?
4.10 Is the removed component isolated from good product and dispositioned correctly?
4.11 Does the procedure specify the process and chemicals to be used for excess flux residue removal?
5. Post Rework and Repair Inspection and Feedback                                                                                                         1, 2       3, 4     5, 6       7, 8     9, 10     RMA      Actual
5.1     Are magnification & lighting tools available at the inspection station? Magnification must be as per IPC based on component type.
5.2     Are repaired boards 100% inspected post repair not only for the repair undertaken but for possible repair damage??
5.3     Is it documented that boards repaired in the offline repair area be processed through all possible test steps (AOI, AXI, ICT, FCT/FVS, QT, etc.)?
5.4     Is the data collected meaningful and can it be demonstrated that it is used to make process control/improvement decisions?
5.5     Is the rework conducted traceable to a specific rework operator?
5.6     Is there evidence that operators receive timely feedback related to the quality of their work?
5.7     Are rework quality goals tracked on a by-operator basis with trigger limits set for re-training/re-assignment if quality goals are not met?
5.8     Are reworked or forced re-worked boards run through PCBA reliability testing at least on an annual basis? (This may include cross
        sectioning, 3D x-ray, HALT/HASS, etc.)
5.9     Is there evidence that the board has been appropriated cleaned post rework?
                                                                                                                                       Maximum Score       63        63        63        63        63        63        63
                                                                                                                                        Score Obtained      0        0          0         0         0         0         0
                                                                                                                                     Score Percentage
                                                                                                                                      Pass Percentage     80%       80%       80%       80%       80%       80%       80%
                                                                                                                                                           Not       Not       Not       Not       Not       Not       Not
                                                                                                                                               Outcome
                                                                                                                                                         Audited   Audited   Audited   Audited   Audited   Audited   Audited
        ^ See Instructions for details on when NA may be an appropriate entry.                                                                         0




                                                                                                                                                                                                           Page 31 of 34
        Dell Confidential                                                                                                                                                               Document No. COR.40.WWP.SQ.0023 Rev 4.0


                                                                                             PCBA Quality Process Audit                                                                                                      Menu
                                                                                                           Add a 'Y' to the Box if the Process Was Assessed
RMA / Service Repair
 #                                                                        Audit Criterion                                                                             1, 2      3, 4       5, 6       7, 8      9, 10      RMA      Actual
1. RMA WIP Flow and Tracking                                                                                                                                       Enter 1 or 0. NA may be a valid response for shaded cells.^
1.1    Are Dell Returns logged into the RMA tracking system by serial number upon receipt?
1.2    Are all failure details supplied by Dell entered into the tracking system for each board serial number? (e.g. RTV & DSP details.)
1.3    Does the tracking system have the proven capability to segregate factory returns from field returns using forced routing?
1.4    Does the tracking system have the proven capability to capture a specific serial number that has been flagged by Dell Engineering ?
1.5    Does the tracking system have the proven capability to record Warranty & ECO status on Dell Returns?
1.6    Does the tracking system have the proven capability to report both the manufacturing history & previous RMA history by serial number?
1.7    Does the tracking system have the proven capability to identify the receipt of 2nd or 3rd time Dell Returns?
1.8    Does the tracking system include a flag to identify when Dell Returns should be scrapped? (Dell Requirement is to scrap upon 3rd time return)
1.9    Does the tracking system have the proven capability to monitor the turn around time by board serial number and to conduct full WIP age analysis?
1.10   Can it be demonstrated that there are no boards in the RMA loop for longer than 30 days?
1.11   Does the tracking system have the proven capability to capture repair and defect information for every board serial number?
1.12   Does the tracking system have the proven capability to capture and highlight the lot code of critical components replaced as a result of rework?
1.13   Does the tracking system have the proven capability to allow traceability between the reworked board and the reworker who completed the rework?
1.14   Does the tracking system have the proven capability to provide an analysis Report for boards undergoing RMA and boards completed RMA?
1.15   Is a Forced Board Routing system and WIP Tacking system fully deployed to monitor and control RMA Process Flows?
1.16   Does the system verify the 'last' step processed and compare it to the expected 'last' step? (True Forced Routing)
1.17   Does the forced routing system have the proven capability to automatically re-route NFF boards for additional special processing?
1.18   Has it been demonstrated that RMA pass/fail data is logged real-time to the forced routing system by serial number and is available?
1.19   Does the system ensure that only boards that have passed through all stages of the RMA Process will be returned to Dell?
1.20   Does the layout of the RMA area indicate that it has been process engineered to avoid product mixing?
2. Process for Failure Verification                                                                                                                                   1, 2      3, 4       5, 6       7, 8      9, 10      RMA      Actual
       Are there available revision controlled RMA Process Flow Charts for processing Dell Field and Line Returns? (Score 0 if any unsigned/undated
2.1
       handwritten modifications more than 48 hrs old)
2.2    Does the Process Flow indicate that all Dell Returns are fully inspected for workmanship issues prior to test processing?
2.3    Does the Process Flow indicate that all Dell Returns are fully inspected for damage prior to test processing?
2.4    Does the Process Flow indicate that all Dell Returns are reviewed for ECO status prior to test processing?
2.5    If workmanship or damage is detected, does the Process Flow require details to be recorded in the RMA tracking system prior to repair?
2.6    If workmanship or damage is detected, does the Process Flow require product to be HMUed for failure mode verification prior to repair?
2.7    Does the Process Flow indicate that workmanship or damage should only be repaired post HMU failure verification?
2.8    Does the Process Flow indicate that ECO upgrade should only take place post HMU failure verification?
2.9    Does the Process Flow indicate that Dell Returns must not be upflashed at HMU verification without first determining if the original flash was corrupted?
       Does the Process Flow require that the top components on the failure Pareto be captured and preserved for Component Analysis? (These components
2.10
       must represent either the top 5 failures or the top 80% of failures)
2.11   Are the top component replacements verified on a socketed board before they are returned to the supplier for Failure Analysis ?
       Does the Process Flow indicate that repaired boards are processed through all applicable testing (ICT, Functional Test, HMU, AOI, AXI, etc.) prior to
2.12
       shipping?
2.13   Does the Process Flow ensure that all boards to be shipped to Dell are reflashed to the correct revision of Bios, Firmware, CMOS, etc?
       Does the Process Flow ensure that all board repairs correlate to the reported failing symptom prior to shipping? Also score 1 if uncorrelated boards are
2.14
       routed for special CND/NDF processing.
2.15   Can it be demonstrated that RMA data is used to improve Production Processes?
3. Control of No Defect Found (NDF)                                                                                                                                   1, 2      3, 4       5, 6       7, 8      9, 10      RMA      Actual
3.1    Does Process Flow indicate how No Defect Found (NDF) boards are processed on completion of the failure verification process?
3.2    Is there a documented procedure which defines an NDF and the process for handling and processing NDFs?
3.3    Is the percentage of NDFs less than 5% of total for Dell Line Returns due to on-site failure verification at Dell factories? Score NA if no OSV.
3.4    Can it be demonstrated that the supplier utilizes additional 'special processes' in an attempt to 'force' an NDF to fail?
3.5    Do these additional special processes include such processes as 'Burn-in Test', or 'Extended Test', or 'Configuration Tests', etc?
3.6    Can it be demonstrated that the supplier utilizes configuration matching in an attempt to 'force' an NDF to fail for a specific config?
3.7    Can it be demonstrated for Dell Line Return boards, that NDFs that continue to pass all tests and special processes are held for Test Correlation? Note*
3.8    Is it documented that a Test Correlation exercise must be conducted between RMA Test and Dell factory Test for Dell Line Returns?
3.9    Is there evidence available to demonstrate that Test Correlation exercises are conducted at least every 6 months?

                                                                                                                                                                                                                        Page 32 of 34
        Dell Confidential                                                                                                                                                             Document No. COR.40.WWP.SQ.0023 Rev 4.0
3.10 Can it be demonstrated that Test Correlation data is used to improve Test Coverage?
4. Debug and FA Capability                                                                                                                                        1, 2       3, 4       5, 6        7, 8     9, 10      RMA       Actual
4.1    Can it be demonstrated that a technician qualification or formal training is required for debug and failure analysis activity?
4.2    Can it be demonstrated that all debug personnel meet the above requirements ?
4.3    Is there adequate debug equipment available at each debug station ?
4.4    Is a mulitmeter available at each debug station?
4.5    Is an oscilloscope available in each debug area?
4.6    Is a bus emulator tool available, like Antron, in each debug area?
4.7    Can it be demonstrated that all debug personnel can demonstrate the use of all debug equipment ?
4.8    Can it be demonstrated that a tool is used to capture fail codes, their fixes, and then recommend the most common fix?
4.9    Can it be demonstrated that the Test Software used to verify the fail at HMU is current to that which is used in Production?
4.10   Can it be demonstrated that the Test Software used during Debug is current to that which is used in Production?
4.11   Are adequate Spare Parts stocked of all Test Equipment ?
4.12   Is there evidence that rework operators receive feedback on the quality of the rework performed?
5. PCBA Documentation                                                                                                                                             1, 2       3, 4       5, 6        7, 8     9, 10      RMA       Actual
5.1    Are the latest schematics for the PCBA available at each debug/failure analysis station?
5.2    Do debug personnel have access to all down-rev revisions of schematics ?
5.3    Are all schematics available to all debug personnel?
5.4    Are the latest Bill of Materials and AVL for the PCBA available at each debug/failure analysis station?
                                                                                                                                            Maximum Score         61          61         61         61        61         61           61
                                                                                                                                             Score Obtained        0           0          0          0         0          0            0
                                                                                                                                           Score Percentage
                                                                                                                                            Pass Percentage         80%         80%       80%      80%       80%        80%       80%
                                                                                                                                                                     Not        Not        Not      Not       Not        Not       Not
                                                                                                                                                        Outcome
                                                                                                                                                                   Audited Audited Audited        Audited   Audited    Audited   Audited
       ^ See Instructions for details on when NA may be an appropriate entry.                                                                                     0
       Note*: Test Correlation refers to understanding why a product fails at Dell (OSV) and passes once returned to a supplier. It is not necessarily about equipment and software copy exact.




                                                                                                                                                                                                                      Page 33 of 34
       Dell Confidential                                                                                                                                                               Document No. COR.40.WWP.SQ.0023 Rev 4.0


                                                                                          PCBA Quality Process Audit                                                                                                       Menu
                                                                                                        Add a 'Y' to the Box if the Process Was Assessed
Packing
 #                                                                        Audit Criterion                                                                            1, 2      3, 4       5, 6       7, 8      9, 10      RMA          Actual
1. Board Packing                                                                                                                                                  Enter 1 or 0. NA may be a valid response for shaded cells.^
       Is there a revision controlled Operator Work Instruction which contains packing information for the specific product being packed? (Score 0
1.1
       if any unsigned/undated handwritten instructions or any handwritten instructions more than 48 hrs old)
1.2    Is the part number for the box (and inserts), etc. indicated on the Work Instructions? (Note: This includes single-pack boxes when applicable)
1.3    Is the part number and dimensions for the static bag indicated on the Work Instructions?
1.4    Is the part number and location for all box labels to be attached defined?
1.5    Are any board 'Handling/Packing Sensitive' areas highlighted on the work instruction? Parts which protrude or elevated parts are most sensitive.
1.6    Is every PCBA scanned prior to packing to ensure it has completed all process and test steps in the correct sequence? Note*
1.7    Is there a significant automatic alarm raised if a board scanned at packing is not ready for shipment? Note*
1.8    Has the orientation of loading the PCBA into the static bag and the box been defined?
1.9    Is the method of folding and/or sealing the static bag defined once the PCBA has been inserted?
1.10   Is every PCBA scanned, placed in the static bag, placed in the box, in that sequence, before beginning to pack another PCBA? Note*
1.11   Does the scanning operation verify through a forced routing system that all routed operations have been competed? Note*
1.12   Is the Dell Shipping label (or product ID) attached to the box before the box is sealed?
1.13   Do the labels and packaging requirements comply with the current Dell Packaging Specification requirements? Dell p/n 00121 &13190
2. Palletization                                                                                                                                                     1, 2      3, 4       5, 6       7, 8      9, 10      RMA          Actual
       Is there a revision controlled Operator Work Instruction for box stacking on the pallet? (Score 0 if any unsigned/undated handwritten
2.1
       instructions or any handwritten instructions more than 48 hrs old)
2.2    Is the pallet type and dimensions indicated on the Work Instructions?
2.3    Does the instruction require boxes to be cross weaved for stability, unless otherwise approved by Dell?
2.4    Does this instruction require the outer box label for each box to be visible for every box on the pallet?
                                                                                                                                    Maximum Score                    17         17         17        17         17         17           17
                                                                                                                                    Score Obtained                   0          0          0         0          0          0            0
                                                                                                                                  Score Percentage
                                                                                                                                   Pass Percentage                  80%       80%        80%       80%        80%         80%       80%
                                                                                                                                                                     Not       Not        Not       Not        Not         Not       Not
                                                                                                                                                          Outcome
                                                                                                                                                                   Audited   Audited    Audited   Audited    Audited     Audited   Audited
       ^ See Instructions for details on when NA may be an appropriate entry.                                                                                     0
       Note*: Some Dell PCBAs do not require a Dell PPID and thus this question may be NA in such cases.




                                                                                                                                                                                                                       Page 34 of 34

				
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