DAG-Aware AIG Rewriting
Alan Mishchenko, Satrajit Chatterjee, Robert Brayton
Department of EECS, University of California Berkeley
Presented by Rozana Bashir
Date 04/02/06
Overview
Introduction
Basic Definitions
Previous work
Proposed technique of AIG Rewriting
Experimental Results
Advantages and Disadvantages of AIG Rewriting
Conclusion
References
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Introduction
AIG – Representation of combinational logic using a network
of two input ANDs and Inverters
DAG Aware AIG Rewriting – A technique for the
optimization of multi-level logic networks during the logic
synthesis
Traditional Combinational Logic Synthesis – SIS, MVSIS
Drawbacks
Relies on trial and error of optimization scripts
Improvements measured using the reduction of literals in the factored
forms of the node SOPs
Complicated and hard to implement
Since traditional synthesis involves the computation of internal don’t
cares, it is slow.
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DAG-Aware AIG Rewriting
Proposed technique- DAG Aware AIG Rewriting [1]
Optimizes the multi-level logic networks
Technique for preprocessing combinational logic before
technology mapping
Optimization works as follows
By alternating the DAG aware AIG rewriting that reduces the
area by sharing the common logic without increasing delay
By alternating AIG balancing that minimizes delay without
increasing area
Why is the AIG Rewriting DAG aware?
Because it makes use of logic sharing
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Basic Definitions
CUT – A cut C of node n is a set of nodes of the network,
called leaves, such that each path from PIs to n passes through
at least one leaf
Trivial CUT – The node itself is a trivial cut of the node
K-feasible CUT – If the number of node in a cut does not
exceed K, then the cut is K-feasible
Level of a node – Length of the longest path from any PI to the
node
Network depth – Largest level of an internal node in the
network
NPN equivalent – Two boolean functions F & G are said to be
NPN equivalent if F can be derived from G by negating and
permuting the inputs and then negating the outputs
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Previous work
In [2] , rewriting in two phases
In the first phase, all two level AIG sub-graphs are pre-computed and
stored in a hash table (by their functionality) containing all non-
redundant AIG.
The second phase involves the traversing the AIG of the circuit in a
topological order
The two level AIG subgraph is found at each node and its boolean
function is computed.
The computed function is used to access the hash table to find and
replace the current subgraph in the circuit with equivalent
subgraphs that leads to largest improvement in the number of nodes
Zero cost replacements- If none of the new subgraphs leads to
improvement but a new graph that keeps the number of nodes
constant is used for rewriting
The zero cost replacements is a heuristic method that may lead to
improvements in subsequent rewriting
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A simple example of AIG rewriting
Subgraph 1 Subgraph 2
Subgraph 1 Subgraph 2 Subgraph 3
a
a b a b a c b c
Subgraph 2 Subgraph 1
a b a c b c a c
Figure 1. Examples of different AND-
Inverter structures for the same a
function
a b b c a c
a b a c
Figure 2. A simple example of AIG
rewriting ( one node less in each case)
AIG Subgraphs for the function F = abc 7
Proposed technique of AIG Rewriting
Improvements compared to the previous work
Use of 4-input cuts instead of two-level subgraphs
Delay aware AIG rewriting by improving the number of
logic levels
Variations of AIG rewriting – minimization of area and
delay is taken into account
AIG refactoring
AIG balancing
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Using 4-input cuts
All 4-input cuts of all nodes are found for the purpose of AIG rewriting
4-variable functions can be manipulated faster because they are stored using
16-bit bitstrings representing truth table
For each cut, the boolean function is computed and its NPN-equivalence
class is determined by a table look-up
The new subgraph that leads to the largest improvement at a node is chosen
If there is no improvement but the zero placements are enabled, a new
subgraph that does not increase the number of node is used
Using 4-input cuts, instead of the two-level subgraphs extends the scope of
rewriting
For each cut, there are an average of three 4-feasible cuts, instead of just one
two-level subgraph
For each cut, we can try on an average of 5 different subgraphs
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Delay-aware AIG rewriting
An incremental computation of the slacks at each internal AIG
node is performed
Slack at a node – Largest increase of its level that does not lead to an
increase in level of POs
After trying each new subgraph, the level of the root node is
computed using the slack
If the resulting increase in the number of the AIG levels
exceeds the slack, the subgraph replacement is not accepted
Slack is incrementally updated after the subgraph replacement
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Variations of AIG rewriting
AIG refactoring – tries to recover area
Rewriting technique for processing subgraphs with more than four
inputs or with larger cuts
One K-feasible cut is computed for all AIG node
The CUT is selected heuristically such that the number of CUT leaves is
minimized while the number of reconvergent paths covered by the CUT is
maximized
The boolean function of the CUT is computed using BDDs and
converted into SOP
The SOP is factored, resulting in an AIG subgraph that is processed
during AIG rewriting
AIG balancing – tries to recover delay
The associative transform a(bc) = (ab)c = (ac)b is applied at each node
to reduce the number of AIG levels
Interleaving AIG balancing with AIG rewriting or refactoring is a very
good heuristic approach
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A realistic example of AIG rewriting
POs
3-node 3-level
4-node 3-level subgraph
subgraph
PIs
ISCAS benchmark s27.blif
Triangles stand for PIs/Pos; rectangles denote latch outputs/inputs
Bubbles denote two-input ANDs; the dotted edges have complemented
attributes
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Experimental Results
AIG Rewriting technique is implemented in the ABC tool - A System for
Sequential Synthesis and Verification
Experiments were conducted on several sets of benchmark circuits and
the AIG Rewriting is compared with the traditional logic synthesis tools,
SIS and MVSIS
The resulting netlists were verified using a SAT based equivalence
checker
Results shows that the AIG Rewriting is better than SIS and MVSIS in
terms of both Area and Delay
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Advantages and Disadvantages
Advantages of AIG rewriting compared to the traditional logic
synthesis
It is much simpler
It is faster
Disadvantages of AIG rewriting compared to the traditional
logic synthesis
Improvements are measured by counting the total number of AIG
nodes and the maximum number of AIG levels. A direct translation
between these two cost functions leads to distortion
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Conclusion
AIG Rewriting is much faster compared to SIS and MVSIS
AIG Rewriting also recovers area
The proposed technique has a potential for replacing the
traditional logic synthesis in the CAD tools
QUESTIONS?
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References
[1] A. Mishchenko, S. Chatterjee, and R. Brayton, "DAG-aware AIG
rewriting: A fresh look at combinational logic synthesis", Accepted to DAC
'06, Department of EECS, University of California, Berkeley.
[2] P. Bjesse and A. Boralv, "DAG-aware circuit compression for formal
verification", Proc. ICCAD '04, pp. 42-49
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