CE Logic Design HW8 by HC111204232212

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									7.1Assume that registers R1 and R2 in Figure 7-6 hold two unsigned numbers. When select input X is
equal to 1, the adder-subtractor circuit performs the arithmetic operation "R1 + 2s complement of R2."
This sum and output carry Cn are transferred into R1 and C when K1 = 1 and a positive edge occurs on the
clock.

a) Show that if C = 1, then the value transferred to R1 is equal to R1 - R2, but if C = 0, the value
transferred to R1 is the 2s complement of R2 - R1.

b) Indicate how the value in the C bit can be used to detect a borrow after the subtraction of two unsigned
numbers.

7.3Given the 16-bit operand 00111010 00110110, what operation must be performed and what operand
must be used

a) to clear all odd bit positions to 0? ( Assume bit positions are 15 through 0 from left to right.)

b) to set the rightmost 3 bits to 1?

c) to complement the most significant 8 bits?

7.5Modify the register of Figure 7-11 so that it will operate according to the following function table,
using mode selection inputs S1 and S0.

S1       S0       Register Operation
0        0        No Change
0        1        Load parallel data
1        0        Shift down
1        1        Clear register to 0

7.7A switch-tail counter (also called twisted ring counter, Johnson counter) uses the complement of the
serial output of a right shift register as its serial input.

a) Starting from an initial state of 000, list the sequence of states after each shift until the register returns
to 000.

b) Beginning in state 00...0, how many states are there in the count sequence of an n-bit switch-tail
counter?

c) Design a decoder to be driven by the counter that produces a one-hot code output for each of the states.
Make use of the don't-care states in your design.

7.11a) Using the synchronous binary counter of Figure 7-14 and an AND gate, construct a counter that
counts from 0000 through 0100.

b) Repeat for a count from 0000 to 1101. Minimize the number of inputs to the AND gate.

7.15Use D-type flip-flops and gates to design a binary counter with each of the following repeated binary
sequences:
              a) 1,2,6   b) 1,2,6,7

Figure 7-6




Figure 7-11
Figure 7-14

								
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