Chapter 9
Counters
1
Asynchronous Counter
Operation
Figure 9--1 A 2-bit asynchronous binary counter.
2
Figure 9--2 Timing diagram for the counter of Figure 9-1. As in previous chapters, output
waveforms are shown in green.
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4
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Figure 9--3 Three-bit asynchronous binary counter and its timing diagram for one cycle.
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Figure 9--4 Propagation delays in a 3-bit asynchronous (ripple-clocked) binary counter.
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Figure 9--5 Four-bit asynchronous binary counter and its timing diagram.
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Figure 9--6 An asynchronously clocked decade counter with asynchronous recycling.
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Figure 9--7 Asynchronously clocked modulus-12 counter with asynchronous recycling.
10
Figure 9--8 The 74LS93A 4-bit asynchronous binary counter logic diagram. (Pin numbers
are in parentheses, and all J and K inputs are internally connected HIGH.)
11
Figure 9--9 Two configurations of the 74LS93A asynchronous counter. (The qualifying
label, CTR DIV n, indicates a counter with n states.)
12
Figure 9--10 74LS93A connected as a modulus-12 counter.
13
Synchronous Counter
Operation
Figure 9--11 A 2-bit synchronous binary counter.
14
Figure 9--12 Timing details for the 2-bit synchronous counter operation (the propagation
delays of both flip-flops are assumed to be equal).
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Figure 9--13 Timing diagram for the counter of Figure 9-11.
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Figure 9--14 A 3-bit synchronous binary counter.
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Figure 9--15 Timing diagram for the counter of Figure 9-14.
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Figure 9--16 A 4-bit synchronous binary counter and timing diagram. Points where the
AND gate outputs are HIGH are indicated by the shaded areas. 20
Figure 9--17 A synchronous BCD decade counter.
21
Figure 9--18 Timing diagram for the BCD decade counter (Q0 is the LSB).
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23
Up/Down Synchronous
Counter
24
Figure 9--23 A basic 3-bit up/down synchronous counter.
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Figure 9—24 : Example 9-4 - Timing Diagram
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27
Design of Synchronous
Counters
Figure 9--27 General clocked sequential circuit.
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Step 1: State Diagram
Figure 9--28 State diagram for a 3-bit Gray code counter. 29
Step 2: Next-State Table
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Step 3: Flip-Flop Transition
Table
31
Step 4: Karnaugh Maps
Figure 9--29 Examples of
the mapping procedure for
the counter sequence
represented in Table 9-7
and Table 9-8.
32
Step 5: Logic Expressions for Flip-Flop Inputs
Figure 9--30 Karnaugh maps for present-state J and K inputs. 33
Step 6: Counter Implementation
Figure 9--31 Three-bit Gray code counter.
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Figure 9—32 : Example 9-5
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37
Figure 9--33
38
Figure 9--34
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Figure 9--35 Example 9-6 - State diagram for a 3-bit up/down Gray code counter.
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41
42
Figure 9--36 J and K maps for Table 9-11. The UP/DOWN control input, Y, is treated as a
fourth variable.
43
Figure 9--37 Three-bit up/down Gray code counter.
44
Cascaded Counters
Figure 9--38 Two cascaded counters (all J and K inputs are HIGH).
45
Figure 9--39 Timing diagram for the cascaded counter configuration of Figure 9-38.
46
Figure 9--40 A modulus-100 counter using two cascaded decade counters.
47
Figure 9--41 Three cascaded decade counters forming a divide-by-1000 frequency divider
with intermediate divide- by-10 and divide-by-100 outputs.
48
Figure 9—42 : Example 9-7 – Determine the overall modulus
49
Figure 9--43 A divide-by-100 counter using two 74LS160 decade counters.
50
Figure 9--44 A divide-by-40,000 counter using 74HC161 4-bit binary counters. Note that
each of the parallel data inputs is shown in binary order (the right-most bit D0 is the LSB in
each counter).
51
Counter Decoding
Figure 9--45 Decoding of state 6 (110). 52
Figure 9--46 : Example 9-9 - A 3-bit counter with active-HIGH decoding of count 2 and
count 7.
53
Figure 9--47 A basic decade (BCD) counter and decoder.
54
Figure 9--48 Outputs with glitches from the decoder in Figure 9-47. Glitch widths are exaggerated for
illustration and are usually only a few nanoseconds wide.
55
Figure 9--49 The basic decade counter and decoder with strobing to eliminate glitches.
56
Figure 9--50 Strobed decoder outputs for the circuit of Figure 9-49.
57
Counter Applications : Digital Clock
Figure 9--51 Simplified logic diagram for a 12-hour digital clock. Logic details using specific devices
58
are shown in Figures 9-52 and 9-53.
Figure 9--52 Logic diagram of typical divide-by-60 counter using 74LS160A synchronous
decade counters. Note that the outputs are in binary order (the right-most bit is the LSB).
59
Figure 9--53 Logic diagram for hours counter and decoders. Note that on the counter
inputs and outputs, the right-most bit is the LSB.
60
Counter Applications : Automobile
Parking Control
Figure 9--54 Functional block diagram for parking garage control.
61
Figure 9--55 Logic diagram for modulus-100 up/down counter for automobile parking
control.
62
Counter Applications : Parallel-to-Serial
Data Conversion (Multiplexing)
Figure 9--56 Parallel-to-serial data conversion logic.
63
Figure 9--57 Example of parallel-to-serial conversion timing for the circuit in Figure 9-56.
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Application
Figure 9--66 Traffic light control system block diagram and light sequence.
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Figure 9--67 Block diagram of the sequential logic.
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Figure 9--68 State diagram showing the 2-bit Gray code sequence.
67
Figure 9--69 Sequential logic.
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Figure 9--70
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Figure 9--71
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Figure 9--72
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