23 Wide-Swing Folded-Cascode OTA Routing Tutorial
Purpose of Tutorial
Creating Node Lists
Starting the Layout
Connecting the Next Level
23.1 Purpose of Tutorial
This tutorial is to show how to use LASI and some of its utilities to auto-route and simulate a
layout of a linear CMOS Operational Transconductance Amplifier from its schematic. The
schematic is from "CMOS Circuit Design, Layout and Simulation" mostly Chapter 25, and is a
combination of bias circuits and amplifier circuits. We will use the LASI drawing program and
the utilities LasiCkt, LasiDrc and LasiMx to do a layout using individual CMOS transistors (44
of them), not standard logic cells that are often used for auto-routing.
You should be running LASI on the OtaTutor drawing that is installed with LASI as you read
through this tutorial. You should also be familiar with running LasiCkt and LasiMx and the
terms used with them, such as "Node Text" or "Connector Bus".
23.2 Individual Transistor Cells
There is a small library of individual CMOS transistor cells, both P-channel and N-channel
types. Look at the cells with the List command.
The N-channel transistors are N2x16, N2X16SS, N2X16NS, N4X8 and N2X512SS.
The P-channel are P2X32, P2X32SW, P2X32NW, P4X16SW and P2X1024SW.
The suffix indicates that there is an internal connection. For example "SS" is Source to Substrate,
"SW" is Source to N-Well.
Each transistor has a corresponding schematic symbol cell, indicated by a additional "_SCH"
The numbers are the gate length and width in terms of standard MOSIS cell dimensions. That is,
the transistors are drawn for Lambda = 1um for a 2um process. LASI Scale is set to 100 basic
units/lam. The transistors are scalable and pass MOSIS SCMOS standard and submicron design
rules. The transistors are drawn so that they can be stacked side by side and not violate design
rules. They also have external connections (Connector Text for LasiCkt compile) placed so that
metal 2 can be run vertically to the connections from top or bottom, similar to more complex
logic cells when used for auto-routing.
The Connector Text points are in a 4 lam horizontal grid and are spaced at least 8 lam apart. A
transistor's width is a multiple of 4 lam. At the connection points, Connector Text numbering
corresponds to the schematic symbol, Drain =1, Gate =2, Source = 3, N-well or Substrate = 4.
N2X16, N2X16SS N-channel and P2X32, P2x32SW P-channel Transistors
One thing that might seem odd is that some transistors have no fourth P-substrate or N-well
connector. The Spice MOS model requires a fourth connection for the bulk region below the gate.
The transistor cells represent the most common ways of connecting P-substrate or N-well in
actual circuit applications. That is, sometimes you connect the substrate or well to the source, and
sometimes you connect them to a fixed potential. Other variations are not considered here.
To be consistent with Spice MOS transistor models, a 3-connector cell must be considered as a
subcircuit or SUBCKT. A 4-connector cell can also be considered as a subcircuit. SUBCKT
definitions are in the OTATUTOR.HDR file.
Preconnecting the substrate or N-well generally results in a much simpler layout.
23.3 Direct Routing
You first need to modify the original schematic for auto-routing. The original schematic is shown
below. It is a cell named OTA_SCH_0 in the drawing.
To modify the schematic,
1. Remove the external RC components.
2. Change transistor schematic symbol cells to the actual transistor schematic symbol cells.
For example, NMOS_SCH --> N2X16_SCH. Use the parameter text on the original
schematic to determine the size and Ccel to change the cell.
Tip: All P-channel have their N-wells connected to the Source. Use a Source-Well
connected transistor such as P2X32SW. There are two kinds of N-channel, those with
Source-Substrate connections and those with ungrounded Sources. Use a transistor such
as N2X16SS for the former and N2x16 for the latter.
3. Put Node Text "0" (layer 4) on any substrate connectors. Since all P-channel are source to
N-well connected there is no "Vdd" Node Text to add.
4. Precede Device Text (layer 6) with an "x" to indicate a subcircuit. Use the Text
command, click on the text reference point and edit the name. Spice is not case sensitive
so you can use lowercase.
5. Remove the Parameter Text (layer 7).
The result is shown in OTA_SCH_1 below.
The simplest way to do a layout would be to place the layout transistors side by side and run
LasiMx to interconnect them. This however would not be too efficient unless you want a long
For a more efficient layout, it would be better to put transistors side by side in 2 rows, P-channel
on top and N-channel on the bottom.
However there is a problem with this. For LasiMx you need to have cells that can have the
vertical connector bus (metal 2) run from top or bottom and not overlay or violate any spacing
design rules. If transistors are placed in rows, the Connector Text of the individual transistors
may not be correctly aligned horizontally, and LasiMx would probably place a connector bus
from one cell on top of the connector bus from another other cell, or at least violate design rules.
You can try this, and then move the buses so they don't interfere, but you might find it a
What you can do is place N-channel and P-channel in two rows and stagger them so that their
connector points do not overlap, and then try to compact the layout later.
You can run the schematic OTA_SCH_1 directly on LasiCkt, and using the NOD file created,
auto-route using LasiMx. After compacting transistors vertically and horizontally without
manually changing any routing and making a few touch-ups, the result is OTA_LAY_DIRECT
which is shown below.
This is still not a particularly efficient layout.
23.4 Nested Routing
Since LasiMx can work with nested levels of cell interconnect, it makes sense to separately
connect P-channel and N-channel sections and then connect the two sections. A discrete transistor
CMOS circuit tends to draw in P and N sections since it is complimentary by nature. For this
OTA circuit you can use LasiMx three times: to connect the N-channels, to connect the P-
channels, making "N" and "P" subcircuits, and then to connect those subcircuits together.
The number of interconnections is reduced at each stage. In this example, you will have about
143 connections when you start. By creating two cells you reduce the connections to 74 and 69.
At the final stage, you have 36 connections. The total number of connections is larger, but at each
stage, working with fewer connections greatly reduces the complexity.
23.5 Creating Node Lists
Refer to the OTA_SCH_1 schematic above. It was split into N and P sections by the following
1. "Cut lines" (layer 1) were added on the interconnect lines (layer 49) that separate P-
channel from N-channel sections
2. An extra "cut vertex" was inserted near the cut line.
3. Connector Text (layer 5) was added on each side of the cut vertex.
The text is "n1 to n18" and "p1 to p18". The text is numbered not only to help us to
remember which line on the N side connects to which on the P side, but also to be
recognized by LasiCkt as a connector.
4. After cuts were marked and text added, the vertices of the interconnect lines were
selected on each side of (and including) the cut vertex, along with all cells and text
belonging to the P or N sections. Then using the Copy command new cells N_SCH_1
and P_SCH_1 were created.
Load the N_SCH_1 cell and notice that it has been changed a bit so that the numbered
interconnect lines are lined up along the top edge. This is simply for neatness. This cell was
modified as follows:
1. Connector Text n1-n18 was copied onto the interconnect line and its layer has been
changed to the Node Text layer (layer 4).
2. The Node Text n4 was changed "0" was added to rename the n4 interconnect.
LasiCkt was then run on the N_SCH_1 cell making N_SCH_1.CIR and N_SCH_1.NOD files.
The parameters of each transistor schematic are in the Parameter Alias File OTATUTOR.PAF
that LasiCkt uses. You must also include OTATUTOR.HDR and OTATUTOR.LIB as header or
footer to make a correct CIR file.
Look at the N_SCH_1.NOD file using the Run button and NOTEPAD.EXE. Notice that nodes
have been created from the n1-n18 Node Text. Notice also that there are a few other node names
(including "0") that did not conflict with n1-n18, and a few virtual nodes that do not have a real
node name at all because they are internal connections.
Load P_SCH_1 and look at P_SCH_1.NOD. The same procedure was used to produce CIR and
NOD files for the P-channels. This time the Node Text "Vdd" has replaced n5.
23.6 Starting the Layout
Load the N_LAY_0 cell. This is the first attempt to put together the N section in a layout.
Transistors were set side by side in their approximate position in the schematic. There are many
ways to arrange the transistors, usually putting transistors that are near in the schematic near in
the layout is preferred. This helps to reduce the length of interconnects. Note also that connectors
fall into a 4 lam horizontal grid.
1. Device Text (layer 6) was added to indicate which layout transistor is the corresponding
schematic transistor. This is Important.
2. Parameter Text (layer 7) was not put on the layout. Remember the parameters of each
transistor subcircuit are in the Parameter Alias File OTATUTOR.PAF.
3. Using LasiMx a connected cell named N_LAY_1 was made from N_LAY_0, LasiMx
was setup as follows:
LasiMx Setup for N_lay Subcircuit
In this setup the node and Connector Bus Widths are 3 lam and Node Bus Spacing is 8
lam. This is to conform to MOSIS design rules. The Label Node Buses, Sort Node Buses
and Compact Node Buses options were set.
4. After LasiMx was run, the N_LAY_1.TLC file was imported into the LASI drawing
using the Import command.
The sort and compact options produced a node bus arrangement with the shorter buses
near to the transistors, and if a bus would fit, it was moved into a position closer to the
transistors. The node buses were set on a 8 lam grid.
The ground node bus "0" was moved below the cells and was expanded to 10 lam. You
can always move a node bus vertically as long as it does not violate design rules.
5. LasiDrc was run on the N_LAY_1 cell to look for design rule violations.
Note: Notice on the layout of N_LAY_1 that there is Connector Text on some of the node bus
ends. This came from the sequence number after the node name in the NOD file.
The final N_LAY_1 is shown below.
Load the P_LAY_1 cell. This cell was constructed similarly to N_LAY_1 with LasiMx, except
that the node buses were positioned differently and stepped in the negative direction. The final
P_LAY_1 is shown below.
23.7 Connecting the Next Level
Load the OTA_SCH_2 cell shown below. In this drawing a new schematic has been made from
the N_SCH_1 and P_SCH_1 schematic drawing cells.
There has been no attempt to make this look neat. Interconnect lines have simply been placed
between the corresponding connectors at any angle and even crossovers have been allowed since
LasiCkt does not connect them.
1. The Device Text Xn and Xp was added on the N_SCH_1 and P_SCH_1 cells. This is
important because the schematics N_SCH_1 and P_SCH_1 are subcircuits.
2. LasiCkt was then run on OTA_SCH_2 making the node list OTA_SCH_2.NOD.
Look at the OTA_SCH_2.NOD file using the Run button and NOTEPAD.EXE.
This file contains the subcircuit node lists for N_SCH_1 and P_SCH_1, and also contains the
main nodes that connect the two subcircuits. Note some of the nodes between the subcircuits have
Node Text (Vdd, etc.) names and that some have virtual names.
23.8 Subcircuit Placement
Load the OTA_LAY_0 cell. This is just the N_LAY_1 and P_LAY_1 cells placed approximately
where you might want them in a layout. The cells have been positioned so that their node buses
are on a 8 lam vertical grid and connectors are on a 4 lam horizontal grid.
LasiMx was setup as below then run on OTA_LAY_0 producing OTA_LAY_1 also shown
LasiMx Setup for OTA_LAY_1
There are at least a couple of things wrong with this layout.
1. There is a lot of empty space in OTA_LAY_1.
2. When you run LasiMx there will be two error messages indicating that there might be
connector bus Spacing Errors at X=332 and X=424.
The first problem is fixed by sliding the top section of the layout down. Try Wmov for this.
The second problem is fixed by determining which node buses can be moved to eliminate the
error. In both cases a node bus was simply shifted up or down into an empty space. This spacing
problem was the result of using cells N_LAY_1 and P_LAY_1 that have Connector Text that is
possibly misaligned with each other. It turned out that happened in two places in this example.
For neatness we also extended the inputs to the left and the output a bit to the right.
23.9 Final Layout
The cell OTA_LAY_FINAL shown below.
As an exercise, you might run LasiDrc and LasiCkt on this cell. You can also trace it out by
hand if you don't believe it is connected correctly.
23.10 Spice Simulation
OTA_LAY_DIRECT and OTA_LAY_FINAL were simulated using WinSpice3. The files
OTATUTOR.HDR, OTATUTOR.LIB and OTATUTOR.PAF were used in the LasiCkt setup,
and the CIR file was compiled. The amplifier was connected for a gain of about 50 with a 10k
load resistor, a 1K input resistor and 50K feedback resistor. Parasitic caps based on typical
process values were used. In the first graph below The direct version is shown. In the second
graph the two stage final version is shown.
With OTA_LAY_DIRECT there is ringing, showing some instability. OTA_LAY_FINAL has
slightly more ringing at a slightly higher frequency. OTA_LAY_DIRECT should have more
parasitic capacitance since it is less optimized. This higher capacitance seems to have the
expected effect of reducing the circuit's bandwidth.
OTA_LAY_DIRECT Pulse Response
OTA_LAY_FINAL Pulse Response
1. Trying to force a gain with feedback often shows instability, or even oscillation because
of circuit phase shift. Adding stability is left to the reader. You might try adding the
series RC combination shown in the original schematic above. Usually you can sacrifice
bandwidth for stability.
2. When Spice simulates you might get a warning about parasitic capacitors that have both
ends connected to ground (0). This is harmless and is caused by the capacitors having one
end connected to a virtual node in a subcircuit without knowing that eventually the node
will connect to ground in the higher cell.
You can prevent this warning by pre-marking the virtual node on the subcircuit with
Node Text, in this case "0". You can find a virtual node by checking the Report Virtual
Nodes in LasiCkt, which will list the objects on the node in the report file.
This is not particularly a layout to be proud of. It would be much better to try to make the
amplifier as a single cell. Doing so is fairly difficult. However, auto-routing the amplifier is a
useful first step because the layout can be used as a interconnection guide to make a more space
efficient layout cell.
Using a combination of the utilities LasiCkt, LasiMx and LasiDrc we have "wired" a fairly
complicated layout of a opamp in a systematic way. Whether you could have done it more
quickly directly is a matter of talent and experience.
There is some empty space still in the layout. As an exercise you might try to condense the layout
some more. There are also some unnecessary connector bus ends where two connector bus runs
come together on different cell levels that can be removed. Be sure to run LasiDrc and LasiCkt
on the circuit when you make changes, and then simulate it.
This tutorial was an example of working with several LASI utility programs. This was not just a
rote procedure. We used a number of "tricks" to simplify a fairly complicated problem. The real
purpose was to make you think and understand what you are really doing. The tricks come from
experience using the programs and working with layouts.