Boxcar FIR Filter by UbUW15

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									Boxcar FIR Filter
    Shadi Hawawini
      Pearl Yuan
     Amr Darwish
   Karun Malhotra
   Advisor: Dr. Parent
      May 8, 2006



                         1
          Agenda
          • Abstract
        • Introduction
              – Why
          – Simple Theory
      – Background Information
    • Summary of Results
• Project (Experimental) Details
           • Results
        • Cost Analysis
         • Conclusions             2
                   Abstract
• We designed a 4-bit Finite Impulse Response
  (FIR) Filter that operates at 200 MHz

 Impulse Response - A set of FIR coefficients,
  which represent all possible frequencies.

 Tap - A coefficient/delay pair. The number of FIR
  taps is an indication of the amount of memory
  required to implement the filter.

                                                      3
                 Introduction
• One of the most fundamental elements for a DSP
  system is an FIR Filter.
• There is no feedback, which results in a finite output
  value of zero.
• The filter is mathematically expressed using the
  following difference equation:
                        P
             y (n)   bi x(n  i )
                       i 0
                                                     4
              FIR Block Diagram



       •The FIR Filter consist of three main components:
         1) A D Flip-Flop to implement a simple delay.
2) A Multiplier to implement the coefficients, which in our case
  we are using a Boxcar filter, meaning all coefficients are 1.
    3) A Full adder to sum the nodes at the end of each Tap.

                                                             5
                Longest Path Calculations
CELL                  BIT# WN Load     WP Load    Ln Load    Lp Load Cg or Cin of load   N M        WN         WP
                             (cm)       (cm)        (cm)       (cm)         F                       cm         cm
xor2                    1                         6.00E-05   6.00E-05  2.0000E-14        6   6   4.26E-04   7.38E-04
xor2                    2  4.26E-04    7.38E-04   6.00E-05   6.00E-05  1.9536E-14        6   6   4.21E-04   7.28E-04
NAND2 (Slave)           3  4.21E-04    7.28E-04   6.00E-05   6.00E-05  1.9267E-14        1   2   3.51E-04   3.15E-04
Driver Mux (Slave)      4  3.51E-04    3.15E-04   6.00E-05   6.00E-05  1.1185E-14        1   3   1.57E-04   1.57E-04
NAND2 (Master)          5  1.57E-04    1.57E-04   6.00E-05   6.00E-05  5.2613E-15        1   2   3.06E-04   2.76E-04
Driver Mux (Master)     6  3.06E-04    2.76E-04   6.00E-05   6.00E-05  9.7671E-15        2   2   2.27E-04   4.03E-04
NAND2 (Slave)           7  2.27E-04    4.03E-04   6.00E-05   6.00E-05  1.0574E-14        1   2   2.17E-04   1.94E-04
Driver Mux (Slave)      8  2.17E-04    1.94E-04   6.00E-05   6.00E-05  6.9041E-15        1   3   2.19E-04   3.90E-04
NAND2 (Master)          9  2.19E-04    3.90E-04   6.00E-05   6.00E-05  1.0229E-14        1   2   2.12E-04   1.90E-04
Driver Mux (Master)    10 2.12E-04     1.90E-04   6.00E-05   6.00E-05  6.7344E-15        2   2   1.79E-04   3.18E-04
NAND2 (Slave)          11 1.79E-04     3.18E-04   6.00E-05   6.00E-05  8.3410E-15        1   2   1.82E-04   1.63E-04
Driver Mux (Slave)     12 1.82E-04     1.63E-04   6.00E-05   6.00E-05  5.8047E-15        1   3   1.98E-04   3.53E-04
NAND2 (Master)         13 1.98E-04     3.53E-04   6.00E-05   6.00E-05  9.2512E-15        1   2   1.96E-04   1.76E-04
Driver Mux (Master)    14 1.96E-04     1.76E-04   6.00E-05   6.00E-05  6.2529E-15        2   2   1.71E-04   3.05E-04
NAND2 (Slave)          15 1.71E-04     3.05E-04   6.00E-05   6.00E-05  7.9866E-15        1   2   1.77E-04   1.59E-04
Driver Mux (Slave)     16 1.77E-04     1.59E-04   6.00E-05   6.00E-05  5.6302E-15        1   3   1.95E-04   3.47E-04
NAND2 (Master)         17 1.95E-04     3.47E-04   6.00E-05   6.00E-05  9.0960E-15        1   2   3.53E-04   3.18E-04
Driver Mux (Master)    18 3.53E-04     3.18E-04   6.00E-05   6.00E-05  1.1248E-14        2   2   1.66E-04   3.00E-04


                                              5ns
                                       PHL       .28ns                                                      6
                                              18
Schematic




            7
Layout




         8
Successful DRC check




                       9
Successful Extraction Report




                               10
Successful LVS Report




                        11
Successful LVS Report cont.




                              12
Simulations




              13
Simulations




              14
Simulation




             15
Simulation




             16
Post Extraction




                  17
Post Extraction cont.




                        18
Propagation Delay Waveform




                             19
Propagation Delay




                    20
               Cost Analysis
• Estimated time spent on each phase of the
  project:
  –   Verifying Logic = 2 weeks
  –   Verifying Timing = N/A
  –   Layout = 15 hours
  –   Post Extracted Timing = 5 hours



                                              21
           Lessons Learned
• A project of this nature requires ample time
  to complete it, before its deadline.
• Verify logic of individual components.
• Extra care needed when designing the
  layout.



                                             22
                Summary

• Because FIR Filters are such an important
  element of DSP design, it was beneficial to
  do a project like this to strengthen
  understanding of the concept
• A low cost, easy to implement Boxcar FIR
  filter was designed and tested
• Due to the nature of DSP, FIR filters of
  some form will always be needed.
                                                23
   Acknowledgements


• Dr. Parent, for teaching us not to
    overcomplicate our designs.




                                       24

								
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