Latch-Up and its Prevention
• Latch is the generation of a low-
impedance path in CMOS chips
between the power supply and the
ground rails due to interaction of
parasitic pnp and npn bipolar
transistors. These BJTs for a
silicon-controlled rectifier with
positive feedback and virtually
short circuit the power and the
• This causes excessive current flows
and potential permanent damage to
• Analysis of the a CMOS Inverter
CMOS depicting the parasitics.
• The equivalent circuit shown has • Assume the Rwell and Rsub are
Q1 being a vertical double significantly large so that they
emmitter pnp transistor whose cause open circuit connections, this
base is formed by the n-well with a results in low current gains and the
high base to collector current gain
(b1). currents would be reverse leakage
currents for both the npn and pnp
• Q2 is a lateral double emitter npn
transistor whose base is formed by transistors.
the p-type substrate. • If some external disturbance
• Rwell represents the parasitic occurs, causing the collector
resistance in the n-well structure current of one of the parasitic
whose value ranges from 1KW to transistors to increase, the resulting
20kW. feedback loop causes the current
• The substrate resistance Rsub perturbation to be multiplied by
depends on the substrate structure. b1.b2
• This event triggers the silicon- • Some causes for latch-up are:
controlled rectifier and each – Slewing of VDD during start-up causing
enough displacement currents due to
transistor drives the other with well junction capacitance in the substrate
positive feedback eventually and well.
– Large currents in the parasitic silicon-
creating and sustaining a low controlled rectifier in CMOS chips can
impedance path between power and occur when the input or output signal
the ground rails resulting in latch- swings either far beyond the VDD level
or far below VSS level, injecting a
up. triggering current. Impedance
• For this condition if b1 *b1 is mismatches in transmission lines can
cause such disturbances in high speed
greater than or equal to 1 both circuits.
transistors will continue to conduct – Electrostatic Discharge stress can cause
latch-up by injecting minority carriers
saturation currents even after the from the clamping device in the
triggering perturbation is no longer protection circuit into either the substrate
available. or the well.
– Sudden transient in power or ground
buses may cause latch-up.
Guidelines For Avoiding Latch-Up
• Reduce the BJT gains by lowering the • Place source diffusion regions for
minority carrier lifetime through Gold the pMOS transistors so that they
doping of the substrate (solution might lie along equipotentials lines when
cause excessive leakage currents).
currents flow between VDD and p-
• Use p+ guardband rings connected to wells.
ground around nMOS transistors and n+
guard rings connected to VDD around • Avoid forward biasing of the
pMOS transistors to reduce Rw and Rsub source/drain junctions so as not to
and to capture injected minority carriers inject high currents , this solution
before they reach the base of the calls for the use of slightly doped
parasitic BJT. epitaxial layer on top of the heanily
• Place substrate and well contacts as doped substrate and has the effect
close as possible to the source of shunting the lateral currents
connections of the MOS transistors to
from the vertical transistor through
reduce the values of Rw and Rsub.
(solution to be used in your designs)
the low resistance substrate.