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					                     R/O concept of the MVD
                          demonstrator

       C.Schrader, S. Amar-Youcef, A. Büdenbender, M. Deveaux, D. Doering, J. Heuser,
      I. Fröhlich, J. Michel, C. Müntz, S. Seddiki, J. Stroth, T. Tischler, and B. Wiedemann




C.Schrader; Oct 2008, CBM Collaboration Meeting, Dubna, Russia
                                             Outline


  readout concept of the MVD demonstrator

        • hardware components

        • data processing                                        subjects of this talk


        • first results of measurements




C.Schrader; Oct 2008, CBM Collaboration Meeting, Dubna, Russia
           Overview of hardware components

2x mimosa20                           Demo-Aux-PCB                       MAPS add-on board



                                                   analogue output

                                                     sync. signals




                                                                                            data transfer: OP-link


                                                                                                                          data transfer: I/O-card
                                                                                                                     or
                                                                               monitoring
flex-print-cable                        support                   Trb2




                                                           PC storage



                                                                              data transfer:
                                                                              in future: optical link (trb2)
 C.Schrader; Oct 2008, CBM Collaboration Meeting, Dubna, Russia               at present: I/O-card
                 Functionality of demo-Aux board
                                                                                        MAPS




                                                                     50 PIN SUB-D Con
                                                                                        add-on-board




                                   Flex-Con
  Mi20           Mi20                         Demo-Aux-board

      Flex-cable
           < 5cm
                                                                   demo- Aux board:
mimosa20:                                                           analogue buffers for pixel data
                                                                      transfer
 4x analogue differential signal outputs
  for long-distance data transfer                                   low voltage regulated power supply
                                                                      for Mi20-chips
 LVTTL sync. signals for chip controlling                          chip slow control wire JTAG
 4x analogue signals for temperature                               convert of the analogue
    monitoring                                                        temperature signals to analog
                                                                      LVDS signals
status of the demo-Aux: advanced schematics                         convert of the LVTTL sync. signals
                                                                      from M20-chip to digital LVDS
                                                                      signals
  C.Schrader; Oct 2008, CBM Collaboration Meeting, Dubna, Russia
                 Functionality of the add-on board
  mimosa20                      demonstrator:
                                2x mimosa, parallel readout,                    CBM: ~2Gbit/s
                                360 x 640 pixel/frame, 50MHz                    compressed
                                 2.4Gbit/s, uncompressed
 This data rate is too high for data storage systems                           online data reduction



                                                           •       platform to study online data
                                                                   specification for data reduction
                                                           •       close to hardware for chip
                                                                   integration in future times
                                                           •       compatibility with HADES DAQ
add-on board with a FPGA                                           (Trb2) for testing purposes
as reconfigurable hardware


status: 12 layer board is completed
        and tested

  C.Schrader; Oct 2008, CBM Collaboration Meeting, Dubna, Russia
               Components of the add-on-board
                                                               4x diff. analogue    LVDS digital sync.
differential-to-differential amplifier to                     pixel data signals   signals
 balance the analogue input for the ADCs                                                             I/O from
                                                                                                     demo-Aux

4 x 12bit ADCs to read out
 the analogue output signal of the two chips

LVDS differential drivers and receivers
 for chip controlling

Virtex IV LX 40 FPGA and memory banks
 for online data-processing

two high-speed connectors (15Gbit/s)
  for data transfer towards the Trb2-board



                                                                                                  add-on-board
  C.Schrader; Oct 2008, CBM Collaboration Meeting, Dubna, Russia
                  Trb2 and Add-on board concept
 the Trb2 (HADES) has been designed in a way to be detector independent
  by using a flexible add-on board concept
 the MAPS Add-on board is mounted on the Trb2 back side

                                                      Trb2 provides:
                                                      • high data-rate digital interface
                                                         connector (15Gbit/s)
                                                      • FPGA configuration
                                                      • high data transfer with optical link
                                                         (2Gbit/s), in future
                                                      • application process interface (API)
                                                      • power supply +5V,10A
                                                      • clock distribution
the general-propose trigger and
readout board (Trb2)


                                                   status: the Trb2-Add-on concept is in use
 C.Schrader; Oct 2008, CBM Collaboration Meeting, Dubna, Russia
                                   Data processing
                                                                 pipelined algorithms
                                                                 for real-time application
                                                                 in stream mode
                                                                              processing steps:
                                                                              • correlated double
                                                                                 sampling (CDS)
                                                                              • bit reduction
                                                                              • threshold
                                                                                 (for hit identification)
                                                                              • cluster finding
                                                                                 (the hit and the 8
                zero suppression                                                 neighbor pixels are
                                                                                 important)




C.Schrader; Oct 2008, CBM Collaboration Meeting, Dubna, Russia
                                                                       ADC calibration
                                         devices intrinsic uncertainly: Integral Nonlinearity error (INL)
                                                                  = ±1.6LSB± 2LSB
                                     20
                                     18
                                                                                    ADC                       OP...
                                     16
                                     14
                                                                                                                                result: the difference of
                                     12
                                     10
                                                                                                                                ideal and actual value is:
                                      8                        with error bars                                                  ±2 ADC counts
                                      6
ideal - actual value [ADC counts]




                                      4                                                                                                 uncertainties are
                                      2
                                      0
                                                                                                                                dominated by ADC
                                     -2
                                      2050             2550               3050                  3550                  4050              readout chain is OK
                                     -4                             digital code [ADC counts]
                                     -6
                                     -8
                                    -10
                                    -12
                                    -14                                                            ADCA
                                    -16                                                            ADCB
                                    -18                                                            ADCC
                                    -20                                                            ADCD
                                    -22
                                                              without error bars                   idea ADC
                                    -24                                                            ADCA: y = 0,0073x - 34,131
                                    -26                                                            ADCB: y = 0,01x - 44,171
                                    -28                                                            ADCC: y = 0,0138x - 54,975
                                    -30                                                            ADCD: y = 0,0112x - 31,111
                                                                                                                                calibration terms are included
                                                                                                                                in data processing
                                    C.Schrader; Oct 2008, CBM Collaboration Meeting, Dubna, Russia
           First measurement results (mimosa20)
digital sync. signals for chip controlling




analogue raw pixel data converted by 12bit ADC
              marker pixel

                   32 µs




                                                                   measured sub matrix with pixel defects
  C.Schrader; Oct 2008, CBM Collaboration Meeting, Dubna, Russia
                                      Project status
Hardware:
 add-on board: design  manufacturing  test 

 I/O interface to PC side: installation  firmware development  test 

o demo-Aux board: specification  ongoing design, manufacturing Nov2008


Data processing:
 VHDL: CDS  bit-reduction  threshold  data-output-interface 
               cluster finding (S. Seddiki)‫ ‏‬specification  ongoing implementation
                                           :

 data acquisition and storage software for PC : development  installation  test 




C.Schrader; Oct 2008, CBM Collaboration Meeting, Dubna, Russia
THANK
 YOU
                                    Correlated double sampling
                                        by Self-Bias-Pixel


       Fig.8: The behaviour of SB-pixels                            1920




                                                        ADC units
            is observed by frames.                                   1910
                                                                    1900
            The constant current                                    1900
                                                                                            fx:px

            leakage in the capacitor                                1890
                                         threshold                                                                               pixel with hit
            is compensate through                                   1880                                                         pixel without hit
                                                                                         hit
            a diode. After hit the diode                            1870
            re-fill the capacitor                                   1860
                                                                                               fx-1:px
                                                                    1850
                                                                       1005   1010        1015           1020   1025   1030
                                                                                                                                readout cycle




                                                                     50
                                                       ∆ ADC



                                                                                         (fx:px - fx-1:px)‫‏‬
                                                                     40

                                                                     30

                                                                     20
Fig.9: Equivalent
                                           threshold                 10
     circuit diagram     of
                                                                      0
     SB-Pixel             Fig.10: After CDS clear                         0          5               10           15            20                   25
                                                                    -10
                               hit identification                                (fx-1:px - fx-2:px)‫‏‬                         acquisition cycle
                                                                    -20
                               is possible
                                        Threshold


                                                    The hit and the
                                                    8 neighbour pixels
                                                    are important




                                                       Result: not the complete matrix is
                                                           readout, only the hit with the
                                                           neighbour pixel


Fig.12: Data selection with threshold
                       Add-on board design




Fig.11: Add-on board
                                      bit-flipping

%
90,0   constant power supply: ~503mV± 10µV                         RESULT: last bit is flipping
                              80,4%
80,0

                                                         70,6 %
70,0



60,0
                                           53,3 % 53,9


50,0           46,1%                                                                              ADCA
                                                                              43,8 %              ADCB
                                                                                                  ADCC
40,0                                                                                              ADCD

                       29,4
30,0

                                                                  19,6%
20,0



10,0
         2,9

 0,0
               3078                               3079                                 3080
                                        Digital code [ADC counts]

				
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