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CSCE 932, Spring 2009 Yield Analysis and Product Quality 1 Outline Yield, defect level, and manufacturing cost Clustered defects and yield model Test data analysis Example: SEMATECH chip Summary 2 Test Performance ALL CHIPS Test FAIL PASS (Tester Yield) Bad Good Bad Good These two Good/Bad? Good/Bad? items determine the Bad Good Tested Bad Tested Good test As Bad As Good performance (Yield) (Yield Loss) (Ybg) (Overkill) (Reject Rate or DPM) 3 Reject Rate (DPM) Basics Reject Rate or Defectives per million (DPM) is a measure of product quality Zero DPM can be achieved by: Perfect yield (100% yield => no bad parts) Perfect test (100% coverage => all bad parts eliminated in testing, all good parts passed) Neither fabrication nor testing process is perfect hence non-zero DPM is a fact of life. DPM minimization is an important goal of quality-conscious companies. For commercial VLSI chips a DL greater than O(100) dpm is considered unacceptable. However, hard to measure. 4 Ways to Estimate DPM Field-Return Data Get customers to return all defective parts, then analyze and sort them correctly to estimate DPM DPM Modeling and Validation Analytical approach using yield and test parameters in the model to predict yield. Steps: 1. Develop a model 2. Calibrate it (Determine parameter values) 3. Estimate the DPM 4. Verify against actual measurements 5. Recalibrate in time and for new designs or processes 5 VLSI Chip Yield and Cost Manufacturing Defect: Chip area with electrically malfunctioning circuitry caused by errors in the fabrication process. Good Chip: One without a manufacturing defect. Yield (Y): Fraction (or percentage) of good chips produced in a manufacturing process is called the yield. Chip Cost: Cost of fabricatin g and testing a wafer Yield Number of chip sites on the wafer 6 Clustered VLSI Defects Good chips Faulty chips Defects Wafer Unclustered defects Clustered defects (VLSI) Wafer yield = 12/22 = 0.55 Wafer yield = 17/22 = 0.77 7 Yield Modeling Statistical model, based on distribution of defects on a chip: p(x) = Prob(number of defects on a chip = x) Yield = p(0) Empirical evidence shows that defects are not uniformly randomly distributed but are clustered. A form of negative binomial pdf for the distribution on a wafer is found to match well with observed data. 8 Binomial and Negative Binomial pdf Bernoulli trials: A biased coin with success probability = p is tossed repeatedly. Binomial: If the coin is tossed n times what is the probability of x successes? Negative Binomial: What is the probability of x failures occurring before the r-th success? 9 Mathematical Definitions Binomial: n p( x | n , p ) p x q( 1 x ) for x 0,1,...,n x Negative Binomial*: See a demo illustrating the r x 1 r 1 x distribution at the x p q p( x | r , p ) p Mathematica website r x 1 r x You may also get further info x p q from the Wikipedia web page. for x 0, 1, ... where,q (1-p) , “Negative” comes from the fact the distribution can also be written as r (1)r ( p)r q x x 10 Negative Bionomial Distribution* (From Wikipedia) 11 Generalized Negative Binomial Distribution When r is a non-integer, the above interpretation breaks down but the form is useful in modeling count data: (r x) p( x | r , p ) pr q x (r)(x 1) for x 0, 1, ... where,q (1-p) , 12 For modeling the defect distribution we make the following substitutions in the above eqn: Ad / 1 r , q , p 1 Ad / 1 Ad / where, d= Defect density = Average number of defects per unit of chip area A= Chip area = Clustering parameter 13 Defect Distribution Equation p(x) = Prob(number of defects on chip =x) ( x ) ( Ad / ) x x ( )( x 1 ) ( 1 Ad / ) 14 Yield Equation Y = Prob ( zero defect on a chip ) = p (0) Y = ( 1 + Ad / ) Example: Ad = 1.0, = 0.5, Y = 0.58 Unclustered defects: = , Y = e - Ad Example: Ad = 1.0, = , Y = 0.37 too pessimistic ! 15 Determination of DL from Test Data (Basic Idea) Combine tester data: #chips passing vs. test-pattern number with the fault coverage data: cum. fault coverage vs. test-pattern number to derive the data: #chips passing vs. fault coverage Extend the defect model to a fault model (yield of chips vs. fault coverage) and determine its parameters by curve fitting. 16 Modified Yield Equation Three parameters: Fault density, f = average number of stuck-at faults per unit chip area Fault clustering parameter, b Stuck-at fault coverage, T The modified yield equation: Y (T ) = (1 + TAf / b) - b Assuming that tests with 100% fault coverage (T =1.0) remove all faulty chips, Y = Y (1) = (1 + Af / b) - b 17 Defect Level Y (T ) - Y (1) DL (T ) = -------------------- Y (T ) b ( b + TAf ) = 1 - -------------------- b ( b + Af ) Where T is the fault coverage of tests, Af is the average number of faults on the chip of area A, b is the fault clustering parameter. Af and b are determined by test data analysis. 18 Example: SEMATECH Chip Bus interface controller ASIC fabricated and tested at IBM, Burlington, Vermont 116,000 equivalent (2-input NAND) gates 304-pin package, 249 I/O Clock: 40MHz, some parts 50MHz 0.45m CMOS, 3.3V, 9.4mm x 8.8mm area Full scan, 99.79% fault coverage Advantest 3381 ATE, 18,466 chips tested at 2.5MHz test clock Data obtained courtesy of Phil Nigh (IBM) 19 Test Coverage from Fault Simulator Stuck-at fault coverage Vector number 20 Measured Chip Fallout Measured chip fallout Vector number 21 Model Fitting Chip fallout and computed 1-Y (T ) Chip fallout vs. fault coverage Y (1) = 0.7623 Measured chip fallout Y (T ) for Af = 2.1 and b = 0.083 Stuck-at fault coverage, T 22 Computed DL 237,700 ppm (Y = 76.23%) Defect level in ppm Stuck-at fault coverage (%) 23 Summary VLSI yield depends on two process parameters, defect density (d ) and clustering parameter () Yield drops as chip area increases; low yield means high cost Fault coverage measures the test quality Defect level (DL) or reject ratio is a measure of the quality of shipped chips. DL can be determined by an analysis of test data For high quality: DL < 500 ppm, fault coverage ~ 99% 24 References For a defect-level estimation model used by Intel, see: V. D. Agrawal, S. C. Seth, and P. Agrawal, "Fault Coverage Requirements in Production Testing of LSI Circuits," IEEE Journal of Solid State Circuits, Vol. SC-17, pp. 57-61, February 1982. 25

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